1. A method for fabricating an electronic device, the method comprising:
providing a semiconductor substrate having a first surface;
doping at least a portion of the first surface;
forming a first compound semiconductor film over the first surface of the substrate, the first compound semiconductor film being doped with a first dopant type;
forming a second compound semiconductor film over the first compound semiconductor film; and
forming a third compound semiconductor film over the second compound semiconductor film, the third compound semiconductor film being doped with a second dopant type.
2. The method of claim 1 wherein the first dopant type is selected to be carbon.
3. The method of claim 1 wherein the second dopant type is selected to be boron.
4. The method of claim 1 wherein the second compound semiconductor film is selected to have a high concentration of germanium.
5. The method of claim 1 wherein the first and second dopant types are each selected to be carbon.
6. The method of claim 1 further comprising:
forming a silicon seed layer over the first surface of the semiconductor substrate; and
forming a silicon cap layer over the third compound semiconductor film.
7. The method of claim 1 wherein each of the compound semiconductor films is selected to be silicon-germanium.
8. The method of claim 1 wherein the semiconductor substrate is selected to be silicon.
9. The method of claim 1 further comprising:
forming a fourth compound semiconductor film over the second compound semiconductor prior to forming the third compound semiconductor film;
doping the fourth compound semiconductor film with boron; and
forming a fifth compound semiconductor film over the fourth compound semiconductor film prior to forming the third compound semiconductor film.
10. The method of claim 9 wherein the fourth and fifth compound semiconductor films is each selected to be silicon-germanium.
11. The method of claim 10 wherein the fifth compound semiconductor film is selected to have a high germanium concentration.
12. The method of claim 1 further comprising:
forming a fourth compound semiconductor film over the third compound semiconductor film; and
doping the fourth compound semiconductor film with carbon.
13. The method of claim 12 wherein the fourth compound semiconductor films is selected to be silicon-germanium.
14. The method of claim 1 further comprising:
forming a fourth and a fifth compound semiconductor film prior to and subsequent to forming the second compound semiconductor film; and
doping each of the fourth and fifth compound semiconductor films with boron.
15. The method of claim 14 further comprising forming a sixth compound semiconductor film between the third and fifth compound semiconductor films.
16. The method of claim 15 wherein the sixth compound semiconductor film is selected to be silicon-germanium with a high germanium concentration.
17. The method of claim 1 further comprising forming an elemental semiconductor cap layer over the third compound semiconductor film.
18. A method of fabricating a heterojunction bipolar transistor, the method comprising:
forming a collector region in a substrate, the substrate being selected to have at least an uppermost portion comprised of an elemental semiconductor;
forming a multi-layer base region, formation of the multi-layer base region including steps of:
forming a first silicon-germanium film over the first surface of the substrate, the first silicon-germanium film being doped with a first dopant type;
forming a second silicon-germanium film over the first silicon-germanium film, the second silicon-germanium film selected to have a high concentration of germanium; and
forming a third silicon-germanium film over the second silicon-germanium film, the third silicon-germanium film being doped with a second dopant type; and
forming an emitter region from an elemental semiconductor layer over the third silicon-germanium film.
19. The method of claim 18 wherein the first dopant type is selected to be carbon.
20. The method of claim 18 wherein the second dopant type is selected to be boron.
21. The method of claim 18 wherein the first and second dopant types are each selected to be carbon.
22. The method of claim 18 further comprising forming a semiconductor seed layer over the substrate.
23. An electronic device comprising:
a substrate having at least an upper portion being comprised of a semiconductor material;
a first doped compound semiconductor film disposed over the upper portion of the substrate;
a second compound semiconductor film disposed over the first compound semiconductor film, the second compound semiconductor film configured to act as a quantum well layer;
a third doped compound semiconductor film disposed over the second compound semiconductor film; and
a cap layer comprised of a semiconductor material.
24. The electronic device of claim 23 wherein each of the compound semiconductor films is substantially comprised of silicon-germanium.
25. The electronic device of claim 24 wherein the second compound semiconductor film has a high concentration of germanium.
26. The electronic device of claim 23 further comprising an elemental semiconductor seed layer disposed between the upper portion of the substrate and the first doped compound semiconductor film.
27. The electronic device of claim 23 wherein the dopant used in each of the first and third compound semiconductor films is carbon.
28. The electronic device of claim 23 wherein the upper portion of the substrate and the cap layer are each comprised of silicon.
29. A heterojunction bipolar transistor comprising:
a collector layer made substantially of an elemental semiconductor, the collector layer being contained in at least an upper portion of a substrate;
an emitter layer made substantially of an elemental semiconductor; and
a base multi-layer located between the emitter layer and the collector layer and comprised substantially of:
a first doped silicon-germanium layer disposed over the upper portion of the substrate;
a second silicon-germanium layer disposed over the first silicon-germanium layer, the second silicon-germanium layer configured to act as a quantum well layer; and
a third doped silicon-germanium layer disposed over the second silicon-germanium layer.
30. The electronic device of claim 29 wherein the second silicon-germanium layer has a high concentration of germanium.
31. The electronic device of claim 29 further comprising an elemental semiconductor seed layer disposed between the upper portion of the substrate and the first doped silicon-germanium layer.
32. The electronic device of claim 29 wherein the dopant used in each of the first and third silicon-germanium layers is carbon.
33. The electronic device of claim 29 wherein the upper portion of the substrate and the emitter layer are each substantially comprised of silicon.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A system for receiving messages in a parallel computing device having a plurality of nodes, each node having multiple processor units and an associated memory operatively connected therewith via an interconnect device, said messaging system comprising at each node:
a plurality of receiver devices for receiving message packets from a network,
a network reception queue associated with a receiver device, each network reception queue adapted to buffer said received packet,
a reception control unit for receiving information from a processor at a node for handling of packets received over a network; and,
a plurality of DMA engine units, each unit operatively connected with the reception control unit and configured to operate in parallel, one DMA engine unit for transferring a current packet received at a network reception queue to a memory location in a reception memory FIFO (rmFIFO) of the associated memory based on said information,
said control unit implementing logic to determine whether any prior received packet for that reception memory FIFO is still in a process of being stored in said associated memory by another DMA engine unit of said plurality, and prevent said one DMA engine unit to indicate completion of storing said current packet until all prior received packets associated with that reception memory FIFO are completely stored by said other DMA engine units,
wherein multiple packets destined to a single rmFIFO are transferred and stored in parallel to predetermined locations in said associated memory.
2. The system as claimed in claim 1, wherein said information specified by said control uni includes address pointers to locations in the associated memory where data received from a current packet is to be stored, said pointers including a first pointer specifying a location starting address of a next packet in the reception memory FIFO and, a second pointer that indicates complete storing of that packet, wherein, said one DMA engine unit accessing said control unit to request update of a corresponding second pointer when storage of said current received packet is completed by that DMA engine,
said control unit logic configured to track using said first and second pointers whether any prior received packet associated with that reception memory FIFO is still in a process of being stored in said memory, and preventing said one DMA engine unit to update said second pointer until all prior received packets for that reception memory FIFO are completely stored by a DMA engine.
3. The system as claimed in claim 1, further comprising:
an interconnect device having one or more ports for coupling each said at least one DMA engine with said interconnect device, said interconnect device configured to arbitrate requests from each said at least one DMA engine to assign access to a switch port; and,
writing packet data from said network reception queues to memory locations for said rmFIFO via at least one switch port, in parallel.
4. The system as claimed in claim 2, wherein said control unit further specifies: a first counter value corresponding to said first pointer, wherein upon receiving a packet, said one DMA engine accessing said control unit to further record a local copy of a current first pointer and a corresponding local copy of a current first counter value.
5. The system as claimed in claim 4, wherein in response to each DMA request to store a packet associated with said reception memory FIFO, said control unit configured to update said current first pointer to include said the number of bytes in the current packet being stored in memory; and, incrementing said current first counter value.
6. The system as claimed in claim 5, wherein said control unit further specifies a second counter value corresponding to said second pointer, wherein upon completion of a current packet store by a DMA engine, said DMA engine requests said control unit to update said second pointer to point to said locally recorded first pointer plus a size of the stored packet, and increment said second counter.
7. The system as claimed in claim 6, wherein after all received packets are stored by one or more of said DMA engines, said control unit updating said second pointer and second counter values to equal said first pointer and corresponding first counter value.
8. The system as claimed in claim 6, wherein said DMA engine request to said control unit includes an indication of the locally recorded first counter value, and, in response to a DMA engine request, said control lira determining whether any prior received packet associated with that reception memory FIFO is still in a process of being stored.
9. The system as claimed in claim 8, wherein said determining includes comparing, by said control unit, the current second counter value with the locally recorded current first counter value obtained from said DMA engine; and, if the second counter value does not match the requestor DMA engine’s locally recorded first counter value, then a pending DMA engine request has been received before the requestor DMA engine.
10. The system as claimed in claim 8, wherein, in response to determining that a pending DMA engine request has been received before the requestor DMA, said control unit forcing said requestor DMA engine to wait until said second counter value matches the requestor DMA engine’s locally recorded first counter value.
11. The system as claimed in claim 8, wherein a received packet type specifies storage at a location in main memory, said reception messaging unit further calculating a destination address in a main memory and moving data of the received packet from a network reception queue to said destination address in the main memory.
12. A method for receiving messages in a parallel computing system having a plurality of nodes, each node having multiple processor units and an associated memory operatively connected therewith via an interconnect device, said method comprising:
receiving, at a network receiver device of a plurality of network receiver devices, a current packet associated with a message and storing said packet at a network reception queue;
accessing, by at least one parallel operating DMA engine unit of a plurality of DMA engine units, a reception control unit providing information from a processor at a node for handling of packets received over a network; and,
transferring, via one of said at least one parallel operating DMA engine unit, the current received packet from the network reception queue to a memory location in a reception memory FIFO (rmFIFO) of the associated processor memory based on said information;
implementing logic, at said control unit, to determine whether any prior received packet associated with that rmFIFO is still in a process of being stored in said associated memory by another DMA engine unit of said at least one DMA engine units; and,
preventing the one of said at least one parallel operating DMA engine unit to indicate completion of storing said current packet until all prior received packets associated with that rmFIFO are completely stored by said other DMA engine units,
wherein multiple packets belonging to a single rmFIFO are transferred and stored in parallel to predetermined locations in said associated memory.
13. The method as claimed in claim 12, wherein said information specified by said control unit includes address pointers to locations in the associated memory where data received from a current packet is to be stored, said pointers including a first pointer specifying a location starting address of a next packet in the reception memory FIFO and, a second pointer that indicates complete storing of that packet, said method further comprising:
accessing, by said one of said at least one parallel operating DMA engine unit, said control unit to request updating of a corresponding second pointer when storage of said current received packet is completed by that DMA engine unit,
determining, by said control unit logic, using said first and second pointers whether any prior received packet associated with that rmFIFO is still in a process of being stored in said memory, and
preventing said one DMA engine unit to update said second pointer until all prior received packets for that reception memory FIFO are completely stored by a DMA engine.
14. The method as claimed in claim 12, wherein each associated DMA engine is coupled with said interconnect device having switch ports that provide a connection to said interconnect device, said method comprising:
arbitrating requests from each said at least one DMA engine to assign access to at least one port; and,
writing packet data from said network reception queues to said memory location for said rmFIFO via at least one port, in parallel,
wherein at least two packets may be received and processed simultaneously for the same rmFIFO.
15. The method as claimed in claim 13, wherein said control unit further comprises: a first counter value corresponding to said first pointer, wherein upon receiving a packet, said DMA engine accessing said control unit to further record a local copy of a current first pointer and a corresponding local copy of a current first counter value.
16. The method as claimed in claim 15, further comprising:
receiving, at said control unit, a request by a DMA engine to store said packet associated with said rmFIFO, wherein in response to each DMA request to store a packet, said control unit updating said current first pointer to include said the number of bytes in the current packet being stored in memory; and, incrementing said current first counter value.
17. The method as claimed in claim 16, wherein said control unit further comprises a second counter value corresponding to said second pointer, wherein upon completion of a current packet store by a DMA engine, requesting, by said DMA engine, said control unit to update said second pointer to point to said locally recorded first pointer plus a size of the stored packet, and request increment said second counter.
18. The method as claimed in claim 17, wherein after all prior received packets are stored by one or more of said DMA engines, said control unit updating said second pointer and second counter values to equal said first pointer and corresponding first counter value.
19. The method as claimed in claim 17, further comprising, indicating by said DMA engine, to said control unit the locally recorded current first counter value, and, in response to a DMA engine request, said control unit determining whether any prior received packet associated with that reception memory FIFO is still in a process of being stored.
20. The method as claimed in claim 19, wherein said determining includes: comparing, by said control unit, the current second counter value with the locally recorded current first counter value obtained from said DMA engine; and, if the second counter value does not match the requestor DMA engine’s locally recorded first counter value, then a pending DMA engine request has been received before the current requestor DMA engine.
21. The method as claimed in claim 19, wherein, in response to determining that a pending DMA engine request has been received before the current requestor DMA, said control unit forcing said requestor DMA engine to wait until said second counter value matches the requestor DMA engine’s first counter value.
22. A computer program product for receiving messages in a parallel computing system having a plurality of nodes, each node having multiple processor units and an associated memory operatively connected therewith via an interconnect device, said computer program product comprising:
a storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
receiving, at a network receiver device of a plurality of network receiver devices, a current packet associated with a message and storing said packet at a network reception queue;
accessing, by at least one parallel operating DMA engine unit of a plurality of DMA engine units, a reception control unit providing information from a processor at a node for handling of packets received over a network; and,
transferring, via one of said at least one parallel operating DMA engine unit, the current received packet from the network reception queue to a memory location in a reception memory FIFO (rmFIFO) of the associated processor memory based on said information;
implementing logic, at said control unit, to determine whether any prior received packet destined for that rmFIFO is still in a process of being stored in said associated memory by another DMA engine unit of said at least one DMA engine units; and,
preventing the one of said at least one parallel operating DMA engine unit to indicate completion of storing said current received packet until all prior received packets destined for that rmFIFO are completely stored by said other DMA engine units,
wherein multiple packets destined for that rmFIFO are transferred and stored in parallel to predetermined locations in said associated memory.