Author: claimsbot

1-10. (canceled)
11. A lithium ion secondary battery comprising:
a cathode material;
an anode material;
a separator; and
an electrolyte solution, wherein
the cathode material includes lithium oxo acid salt, and the electrolyte solution includes an electrolyte solvent which contains an ammonium ion including two or more alkoxyalkyl groups as substituent groups.
12. The lithium ion secondary battery according to claim 11, wherein the lithium oxo acid salt is one kind of LiFePO4, LiMnPO4, Li2FeSiO4, and Li2MnSiO4.
13. The lithium ion secondary battery according to claim 11, wherein the ammonium ion is represented by the following general formula (1).
(wherein: substituent group R1 represents an alkyl group including one or more and five or less carbons, or an alkoxyalkyl group including two or more and four or less carbons; substituent group R2 represents an alkyl group including one or more and five or less carbons, or an alkoxyalkyl group including two or more and four or less carbons; substituent group R3 represents an alkoxyalkyl group including two or more and four or less carbons; and substituent group R4 is an alkoxyalkyl group including two or more and four or less carbons.)
14. The lithium ion secondary battery according to claim 11, wherein the ammonium ion is represented by the following general formula (2).
(wherein: substituent group R3 represents an alkoxyalkyl group including two or more and four or less carbons; and substituent group R4 represents an alkoxyalkyl group including two or more and four or less carbons.)
15. The lithium ion secondary battery according to claim 11, wherein the ammonium ion is represented by the following general formula (3).
(wherein: substituent group R3 represents an alkoxyalkyl group including two or more and four or less carbons; and substituent group R4 represents an alkoxyalkyl group including two or more and four or less carbons.)
16. The lithium ion secondary battery according to claim 11, wherein the ammonium ion is represented by the following general formula (4).
(wherein: substituent group R3 represents an alkoxyalkyl group including two or more and four or less carbons; and substituent group R4 represents an alkoxyalkyl group including two or more and four or less carbons.)
17. The lithium ion secondary battery according to claim 13, wherein substituent group R2 is an alkoxyalkyl group including three or four carbons.
18. The lithium ion secondary battery according to claim 17, wherein
substituent group R1 is a methoxyethyl group, a methoxypropyl group, an ethoxyethyl group, or an alkyl group including two or more and five or less carbons,
substituent group R2 is a methoxyethyl group or an ethoxyethyl group, and
each of substituent groups R3 and R4 is a methoxyethyl group.
19. The lithium ion secondary battery according to claim 13, wherein
substituent group R1 is a methyl group or an ethyl group,
substituent group R2 is an ethyl group or a butyl group,
substituent group R3 is a methoxyethyl group, and
substituent group R4 is a methoxyethyl group or an ethoxyethyl group.
20. The lithium ion secondary battery according to claim 11, wherein the alkoxyalkyl group includes a terminal alkyl group which contains one or two carbons, and an alkyl group which contains two carbons and is combined with N.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A self-contained, discrete programmable hearing aid module for attachment to a hearing aid faceplate and for accepting a plurality of programming leads retained within a cable element, the self-contained, discrete programmable hearing aid module comprising:
a housing including a first and a second wall, wherein the first and second walls define a slot, and wherein the second wall includes at least one shoulder extending therefrom into the slot; and
a plurality of electrical leads extending into the slot and retained by the first wall and positioned with respect to at least one shoulder such that the electrical leads are disposed in conductive contact with the programming leads of the cable element when the cable element is inserted within the slot.
2. The self-contained, discrete programmable hearing aid module of claim 1 and further including a plurality of shoulders extending from the second wall and spaced apart from each other approximately a width of the programming leads to accept the programming leads between the shoulders when the cable element is inserted into the slot.
3. The self-contained, discrete programmable hearing aid module of claim 2 wherein the electrical leads are made of a spring metal and extend into the slot such that the electrical leads act against the programming leads of the cable element when the cable element is within the slot.
4. The self-contained, discrete programmable hearing aid module of claim 1 wherein the housing is made of a polymeric material sufficient to withstand soldering temperatures such that the electrical leads retain alignment during soldering.
5. The self-contained, discrete programmable hearing aid module of claim 4 wherein the polymeric material is nylon 66.
6. The programmable hearing aid module of claim 1 wherein the programmable cable has a first thickness, the cable slot has a second thickness, the first thickness being larger than the second thickness.
7. A faceplate and programmable hearing aid module combination, the faceplate and programmable hearing aid combination comprising:
a battery opening disposed within the faceplate, wherein the battery opening is defined by opposed side walls and opposed end walls, and wherein the battery opening is located at a first position on the faceplate;
a module opening disposed within the faceplate, the module opening defined by opposed side edges and opposed end edges, wherein the module opening is located at a second position on the faceplate, and wherein the first position is distinct from the second position on the faceplate;
a self-contained programmable hearing aid module disposed within the module opening, the self-contained programmable hearing aid module comprising:
a housing including a first and a second wall, wherein the first and second walls define a slot, and wherein the second wall includes at least one shoulder extending therefrom into the slot; and
a plurality of electrical leads extending into the slot and retained by the first wall and positioned with respect to at least one shoulder such that the electrical leads are disposed in conductive contact with the programming leads of the cable element when the cable element is inserted within the slot.
8. The faceplate and programmable hearing aid module combination of claim 7 wherein the programmable hearing aid module is detachably attached to the faceplate.
9. The faceplate and programmable hearing aid module combination of claim 7 wherein the programmable hearing aid module is made of a polymer having a melt temperature sufficient to withstand soldering temperatures such that the electrical leads retain alignment during soldering.
10. The faceplate and programmable hearing aid module combination of claim 9 wherein the polymeric material is nylon 66.
11. The faceplate and programmable hearing aid module combination of claim 7 and further including a plurality of shoulders extending from the second wall and spaced apart from each other approximately a width of the programming leads to accept the programming leads between the shoulders when the cable element is inserted into the slot.
12. The faceplate and programmable hearing aid module combination of claim 9 wherein the electrical leads are made of a spring medal and extend into the slot such that the electrical lead act against the programming leads of the cable element when the cable element is within a slot.
13. A programmable hearing aid faceplate, the programmable hearing aid faceplate comprising:
a battery opening disposed within the faceplate, wherein the battery opening is defined by opposed side walls and opposed end walls, and wherein the battery opening is located at a first position on the faceplate;
a module opening positioned within the faceplate, the module opening defined by opposed side edges and opposed end edges, the module opening located at a second position on the faceplate,
a programmable module attached to the faceplate in cooperation with the module opening; and
wherein the first position is distinct from the second position on the faceplate.
14. The programmable hearing aid faceplate of claim 13 wherein the programmable module further includes a plurality of electrical leads embedded within a wall of the module and wherein the wall is made of a polymeric material sufficient to withstand soldering temperatures such that the electrical leads retain alignment during soldering.
15. The programmable hearing aid faceplate of claim 14 wherein the polymeric material is nylon 66.

1. An N bit Digital-to-Analog Converter (DAC) comprising independently sized first and second current source transistors coupled to respective pluralities of first and second current provider transistors in current mirror configurations, wherein the first and second current provider transistors are sized proportionally to the first and second current source transistors respectively.
2. An N bit Digital-to-Analog Converter (DAC) comprising:
a first current provider circuit configured to provide a plurality of first current signals responsive to a plurality of first bits of an N bit data word weighted differently based on a first reference current; and
a second current provider circuit configured to provide a plurality of second current signals responsive to a plurality of second bits of the N bit data word weighted equally based on a second reference current that is different than the first reference current.
3. An N bit DAC according to claim 2 wherein the first current provider circuit comprises a plurality of transistors of different sizes based on the first reference current.
4. An N bit DAC according to claim 3 wherein the different sizes of the plurality of transistors are further based on respective orders of data bits of the N bit data word to which each of the respective transistors is coupled.
5. An N bit DAC according to claim 3 wherein the first current signals have associated respective magnitudes determined based on the different sizes of the plurality of transistors.
6. An N bit DAC according to claim 3 wherein respective sourcedrain terminals of the plurality of transistors are coupled to the plurality of first bits.
7. An N bit DAC according to claim 3 wherein the plurality of transistors comprises a plurality of first transistors, wherein the second current provider circuit comprises a plurality of second transistors of about equal sizes based on the second reference current.
8. An N bit DAC according to claim 7 further comprising:
a first current source transistor coupled to the plurality of first transistors that is configured to provide the first reference current, wherein the first current source transistor has a size about equal to a lowest order one of the plurality of first transistors; and
a second current source transistor coupled to the plurality of second transistors that is configured to provide the second reference current, wherein the second current source transistor has a size about equal to all of the plurality of second transistors.
9. An N bit DAC according to claim 8 wherein the first and second current source transistors are sized independently of one another.
10. An N bit DAC according to claim 7 wherein sourcedrain terminals of the pluralities of first and second transistors are not coupled to separate resistor components.
11. An N bit DAC according to claim 7 wherein sourcedrain terminals of the pluralities of first and second transistors are each coupled to respective switches configured to switch respective bits of the N bit data word to the ones of the pluralities of first and second transistors.
12. An N bit DAC according to claim 2 wherein the plurality of first bits comprise lower order bits of the N bit data word and the plurality of second bits comprise high order bits of the N bit data word that are higher order than the plurality of first bits, wherein the second reference current is about 2m times as large as the first reference current, wherein m equals a lowest order one of the high order bits.
13. An N bit DAC according to claim 2 wherein the first current provider circuit comprises a plurality of first transistors having different respective sizes relative to one another and the second current provider circuit comprises a plurality of second transistors having about equal sizes relative to one another.
14. An N bit DAC according to claim 2 further comprising:
first and second current source transistors coupled to the first and second current provider circuits respectively; and
a current correction circuit coupled to the first and second current provider circuits and coupled to at least one of the first and second current source transistors and configured to change at least one of the first and second reference currents based on a difference between voltage levels provided by the first and second current provider circuits.
15. An N bit DAC according to claim 14 wherein the current correction circuit is coupled to the first and second current source transistors and is configured to change the first and second reference currents based on the difference.
16. An N bit DAC according to claim 14 wherein the current correction circuit comprises an analog-to-digital converter circuit to convert the voltage levels provided by the first and second current provider circuits to decoded digital signals representing a correction to the first or second reference current.
17. An N bit DAC according to claim 16 further comprises:
a plurality of current correction transistors coupled to the analog-to-digital converter circuit and at least one of the first and second current source transistors and responsive to the decoded digital signals to change the first and second reference currents.
18. An N bit Digital-to-Analog Converter (DAC) comprising:
a current correction circuit configured to change at least one of first and second reference currents provided in proportion to respective sizes of transistors included in associated first and second current provider circuits based on a difference between voltage levels provided by the first and second current provider circuits.
19. An N bit DAC according to claim 18 further comprising:
first and second current source transistors coupled to the first and second current provider circuits respectively, wherein the current correction circuit is coupled to the first and second current source transistors and is configured to change the first and second reference currents based on the difference.
20. An N bit DAC according to claim 18 wherein the current correction circuit comprises an analog-to-digital converter circuit to convert the voltage levels provided by the first and second current provider circuits to decoded digital signals representing a correction to the first or second reference current.
21. An N bit DAC according to claim 20 further comprises:
a plurality of current correction transistors coupled to the analog-to-digital converter circuit and at least one of the first and second current source transistors and responsive to the decoded digital signals to change the first and second reference currents.
22. A method of operating an N bit Digital-to-Analog Converter (DAC) comprising:
providing a plurality of first current signals responsive to a plurality of first bits of an N bit data word weighted differently based on a first reference current; and
providing a plurality of second current signals responsive to a plurality of second bits of the N bit data word weighted equally based on a second reference current that is different than the first reference current.
23. A method according to claim 22 wherein the plurality of first current signals are provided by a plurality of transistors of different sizes based on the first reference current.
24. A method according to claim 23 wherein the different sizes of the plurality of transistors are further based respective orders of data bits of the N bit data word to which each of the respective transistors is coupled.
25. A method according to claim 23 wherein the first current signals have associated respective magnitudes determined based on the different sizes of the plurality of transistors.
26. A method according to claim 23 wherein respective sourcedrain terminals of the plurality of transistors are coupled to the plurality of first bits.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for manufacturing a surface machined infrared sensor package, comprising the steps of:
providing a semiconductor substrate having a front side surface and a back side surface;
defining a transistor on the substrate front side surface;
implanting a reflector on the substrate front side surface;
forming a sensor on the substrate front side surface adjacent to the reflector; and
depositing a thin-film absorber upon the sensor,
wherein the thin-film absorber is substantially parallel to the reflector with the sensor disposed there between.
2. The method of claim 1, wherein the transistor is a CMOS transistor.
3. The method of claim 1, wherein a distance between the thin-film absorber and the reflector comprises approximately one quarter of a radiation wavelength detected by the sensor.
4. The method of claim 1, wherein the infrared sensor further comprises one of the group of a thermopile infrared sensor, a diode-bolometer, and a resistive microbolometer.
5. The method of claim 4, wherein the diode-bolometer is a lateral diode-bolometer.
6. The method of claim 4, wherein the diode-bolometer is a vertical diode-bolometer.
7. The method of claim 1, wherein the substrate does not include a substrate recess behind the sensor.
8. The method of claim 1, further comprising the step of releasing the front side surface of the infrared sensor.
9. The method of claim 8, wherein the step of releasing the front side surface of the infrared sensor further comprises forming a cavity by etching a spacer between the reflector and the absorber.
10. The method of claim 9, wherein said etching is a front side surface etching.
11. The method of claim 1, further comprising the step of vacuum packaging for further miniaturization of the surface machined infrared sensor package.
12. A surface machined infrared sensor configured to detect a radiation wavelength, comprising:
a silicon wafer having a front side and a back side;
a highly doped silicon reflector implanted in the wafer front side;
an IR sensor having thin-film interferometric absorber disposed parallel to the reflector; and
a front side infrared sensor disposed between the reflector and the absorber.
13. The sensor of claim 12, wherein the infrared sensor further comprises one of the group of a thermopile IR sensor, diode-bolometer, and a resistive microbolometer.
14. The sensor of claim 13, wherein the diode-bolometer is a lateral diode-bolometer.
15. The sensor of claim 13, wherein the diode-bolometer is a vertical diode-bolometer.
16. The sensor of claim 12, wherein the thin-film absorber is impedance matched to atmosphere.
17. The sensor of claim 16, wherein the thin-film absorber impedance is on the order of 377 \u03a9sq.
18. The sensor of claim 12, wherein the wafer back side does not include a recess behind the sensor.
19. The sensor of claim 12, wherein the interferometric absorber is disposed a quarter wavelength distance from the reflector, wherein the wavelength comprises a radiation wavelength detected by the sensor.
20. The sensor of claim 12, wherein the front side infrared sensor further comprises a thin silicon layer for optimized thermoelectric properties.
21. The sensor of claim 20, wherein the thin silicon layer is less than 200 nm thick.
22. The sensor of claim 12, further comprising a CMOS read-out circuit integrated on the wafer.
23. The sensor of claim 12, further comprising vacuum packaging of the sensor.
24. A two dimensional array of surface machined infrared sensors according to claim 12.
25. A two dimensional array of surface machined infrared sensors according to claim 24.
26. The sensor of claim 12, wherein the front side infrared sensor further comprises sensing silicon andor a suspension arm thinner than 200 nm.