Author: claimsbot

1. A method of forming an NVM cell and a logic transistor using a semiconductor substrate, comprising:
in a non-volatile memory (NVM) region, forming over the semiconductor substrate a first thermally-grown oxygen-containing layer, a select gate of a first material, and a first dielectric layer, wherein the select gate is on the first thermally-grown oxygen-containing layer, a top surface of the first dielectric layer is substantially aligned with a top surface of the select gate, and the first dielectric layer has a first opening in which the select gate is present in the first opening;
in a logic region, after forming the first thermally-grown oxygen-containing layer, forming over the semiconductor substrate a high-k dielectric layer, a work-function-setting layer over the high-k dielectric layer, a dummy gate on the work-function-setting layer, sourcedrains in the semiconductor substrate, a sidewall spacer around the dummy gate, and a second dielectric layer, wherein a top surface of the second dielectric layer is substantially aligned with a top surface of the dummy gate, and the second dielectric layer has a second opening in which the dummy gate is present in the second opening;
replacing the dummy gate with a metal gate;
removing the first dielectric layer in the NVM region while leaving the second dielectric layer in the logic region;
forming a charge storage layer over the NVM region including over the select gate;
forming a conductive layer over the charge storage layer;
etching the conductive layer to form a control gate; and
etching the charge storage layer to leave a remaining portion of the charge storage layer aligned to the control gate.
2. The method of claim 1, wherein:
the forming the charge storage layer is further characterized by forming nanocrystals over the second dielectric layer and the metal gate; and
the etching the charge storage layer is further characterized by removing the charge storage layer over the second dielectric layer and the metal gate.
3. The method of claim 2, wherein:
the step of forming the conductive layer is further characterized by forming the conductive layer over the logic region; and
the step of patterning the conductive layer is further characterized by removing the conductive layer over the logic region.
4. The method of claim 3, wherein the forming the first dielectric layer and forming the second dielectric layer are further characterized as forming the first dielectric and the second dielectric layers simultaneously of a same material.
5. The method of claim 1, further comprising forming a first silicide region on the source and a second silicide region on the drain of the logic transistor prior to the forming of the second dielectric layer.
6. The method of claim 5, further comprising:
forming a first sourcedrain adjacent the control gate, a second sourcedrain (66) adjacent the select gate, and siliciding the first and second sourcedrains.
7. The method of claim 1, further comprising:
forming a liner around the dummy gate prior to the forming the sidewall spacer.
8. The method of claim 7, further comprising:
forming a hard mask over the NVM region and the logic region prior to the removing the first dielectric layer.
9. The method of claim 8, further comprising removing the hard mask from over the NVM region while leaving the hard mask over the logic region prior to removing the first dielectric layer.
10. The method of claim 1, wherein the first material comprises polysilicon.
11. The method of claim 1, wherein:
the forming the metal gate comprises removing the dummy gate to form an opening, filling the opening with metal, and performing chemical mechanical polishing.
12. The method of claim 1, wherein the forming the charge storage layer comprises forming a layer of silicon nitride.
13. The method of claim 1, wherein the forming the charge storage layer comprises:
forming a base dielectric layer;
forming nanocrystals on the base dielectric layer; and
forming a fill dielectric layer around and over the nanocrystals.
14. The method of claim 1, wherein the forming the charge storage layer comprises forming a layer of silicon nitride.
15. A method of forming a non-volatile memory (NVM) cell and a logic transistor using a semiconductor substrate, comprising:
forming a polysilicon select gate over a first thermally-grown oxygen-containing layer, a work-function-setting layer over a high-k dielectric, and a dummy gate over the work-function-setting layer;
after forming the first thermally-grown oxygen-containing layer, forming a sidewall spacer around the dummy gate;
forming sourcedrains in the semiconductor substrate adjacent to the dummy gate;
forming a dielectric layer around the polysilicon select gate and the dummy gate wherein a top surface of the dielectric layer is substantially aligned with a top surface of the polysilicon select gate and a top surface of the dummy gate;
removing the dummy gate;
replacing the dummy gate with a metal gate to form a logic gate comprising the work-function-setting material and the metal gate;
forming a hard mask over the logic gate;
removing the dielectric layer from around the polysilicon select gate while leaving the dielectric layer around the logic gate;
forming a charge storage layer over the semiconductor substrate;
forming a conductive layer over the charge storage layer;
etching the conductive layer to form a control gate over a portion of the charge storage layer and removing the conductive layer from over the hard mask;
etching the charge storage layer to leave a portion of the charge storage layer under the control gate and removing the charge storage layer from over the hard mask; and
forming second sourcedrains in the substrate adjacent to the select gate and control gate.
16. The method of claim 15, further comprising removing the hard mask.
17. The method of claim 16 further comprising siliciding the second sourcedrains prior to the removing the hard mask.
18. The method of claim 17 further comprising siliciding the first sourcedrains prior to the forming the dielectric layer.
19. The method of claim 15, wherein the forming a charge storage layer comprises forming a nanocrystal-containing charge storage layer.
20. A method, comprising:
in an NVM region of the semiconductor substrate, forming a polysilicon select gate of a non-volatile memory (NVM) cell on a first thermally-grown oxygen-containing layer, and in a logic region of a semiconductor substrate, forming a work-function-setting material on a high-k gate dielectric and a polysilicon dummy gate on the work-function-setting material;
forming a sidewall spacer around the polysilicon dummy gate and silicided sourcedrains adjacent the sidewall spacer;
forming a dielectric having a top surface that is substantially aligned to a top surface of the polysilicon select gate and a top surface of the polysilicon dummy gate;
replacing the polysilicon dummy gate with a metal gate;
removing the dielectric from around the polysilicon select gate;
forming a charge storage layer over the logic region and the NVM region;
forming a conductive layer over the logic region and the NVM region;
etching the conductive layer over the NVM region to form a control gate over the charge storage layer and removing the conductive layer from the logic region;
etching the charge storage layer to leave the charge storage layer under and aligned with the control gate and to remove the charge storage layer over the logic region; and
forming sourcedrain regions in the substrate in the NVM region adjacent to the control gate and to the polysilicon select gate.
21. The method of claim 20 further comprising:
forming a hard mask over the logic region prior to the removing the dielectric from around the polysilicon select gate;
siliciding the sourcedrain regions in the substrate in the NVM region; and
removing the hard mask after the siliciding the sourcedrain regions in the substrate in the NVM region.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An intraocular lens for insertion into the capsular bag of an eye, comprising:
an optic having a periphery and centered about an optical axis;
an outer periphery configured to engage an equatorial region of the capsular bag of an eye;
an outer support structure disposed along the outer periphery of the intraocular lens and spaced from the optic with voids therebetween;
a first intermediate member operably coupled to the optic and the outer support structure; and
first and second weakened regions disposed along the outer periphery, each of the weakened regions disposed between the outer support structure and the first intermediate member, the weakened regions configured to allow relative motion between the outer support structure and the first intermediate member in response to the ciliary muscle of the eye.
2. The intraocular lens of claim 1, wherein the outer periphery is circular.
3. The intraocular lens of claim 1, wherein the outer periphery is elliptical.
4. The intraocular lens of claim 1, further comprising a second intermediate member extending between and operably coupling the optic and the outer support structure.
5. The intraocular lens of claim 4, further comprising a third intermediate member extending between and connecting the optic and the outer support structure.
6. The intraocular lens of claim 1, wherein the outer support structure further comprises at least one intermediate weakened region circumferentially disposed between first intermediate member and the second intermediate member.
7. The intraocular lens of claim 6, wherein the at least one intermediate weakened region is circumferentially disposed equidistant between first intermediate member and the second intermediate member.
8. The intraocular lens of claim 1, wherein at least one of the weakened regions comprises a hinge.
9. The intraocular lens of claim 1, wherein at least one of the weakened regions has a radial thickness that is less than a radial thickness of the outer support structure in a region proximal the at least one weakened region.
10. The intraocular lens of claim 1, wherein at least one of the weakened regions has a thickness along the optical axis that is less than a thickness along the optical axis of the outer support structure in a region proximal the at least one weakened region.
11. The intraocular lens of claim 1, wherein the outer support structure is made of a first material and at least one of the weakened regions is made of a second material that is more bendable than the first material.
12. The intraocular lens of claim 1, wherein the outer support structure comprises a first arm and the second arm with a void therebetween.
13. The intraocular lens of claim 12, wherein at least a portion of the first arm is slidably disposed to at least a portion of the second arm.
14. An intraocular lens for insertion into the capsular bag of an eye, comprising:
an optic having a periphery and centered about an optical axis;
an outer support structure having an outer periphery, the outer support structure entirely and continuously surrounding the optic and spaced therefrom with voids therebetween, the outer support structure configured to engage an equatorial region of the capsular bag of an eye; and
a first intermediate member extending between and operably coupled to the optic and the outer support structure;
a weakened region disposed proximal to the first intermediate member along the outer periphery, the weakened region configured to allow relative motion between the outer support structure and the first intermediate member in response to the ciliary muscle of the eye.
15. The intraocular lens of claim 14, wherein the outer support periphery is elliptical.
16. The intraocular lens of claim 14, further comprising a second intermediate member extending between and operably coupling the optic and the outer support structure.
17. The intraocular lens of claim 16, further comprising first weakened regions disposed along the outer periphery proximal the intermediate members, and also comprising second weakened regions disposed along the outer periphery proximal the intermediate members, the first weakened regions and the second weakened regions configured to allow angular motion between the outer support structure and the intermediate members in response to the ciliary muscle of the eye.
18. The intraocular lens of claim 17, wherein the outer support structure further comprises at least one intermediate weakened region circumferentially disposed between first intermediate member and the second intermediate member.
19. The intraocular lens of claim 18, wherein the at least one intermediate weakened region is circumferentially disposed equidistant between first intermediate member and the second intermediate member.
20. The intraocular lens of claim 17, wherein at least one of the weakened regions comprises a hinge.
21. The intraocular lens of claim 17, wherein at least one of the weakened regions has a radial thickness that is less than a radial thickness of the outer support structure in a region proximal the at least one weakened region.
22. The intraocular lens of claim 17, wherein the outer support structure is made of a first material and at least one of the weakened regions is made of a second material that is more bendable than the first material.

1. An electronic device comprising:
a fingerprint detector; and
circuitry configured to execute a first function when a detected fingerprint substantially coincides with a first fingerprint from a plurality of registered fingerprints of a user, and to execute a second function different from the first function when a detected fingerprint substantially coincides with a second fingerprint different from the first fingerprint from a plurality of registered fingerprints of the user.
2. The electronic device according to claim 1, wherein
the circuitry is further configured to execute authentication based on a detected fingerprint, wherein the circuitry is further configured to execute:
the first function when a detected fingerprint substantially coincides with the first fingerprint and the authentication of the user succeeds;
the second function when a detected fingerprint substantially coincides with the second fingerprint and the authentication succeeds; and
restriction of at least one of the first function and the second function when the authentication fails or is not executed.
3. The electronic device according to claim 2, wherein the circuitry is further configured to execute a third function, prior to the execution of the first function or the second function respectively when the authentication succeeds.
4. The electronic device according to claims 1, wherein the circuitry is further configured to preset a distinct function to each of the plurality of registered functions corresponding to the plurality of registered fingerprints.
5. The electronic device according to claims 1, wherein the circuitry is further configured to execute a preset function when a detected fingerprint does not coincide with any of the plurality of registered fingerprints.
6. A method executed in an electronic device comprising:
detecting a fingerprint by a detector,
executing a first function when a detected fingerprint substantially coincides with a first fingerprint from a plurality of registered fingerprints of a user; and
executing a second function different from the first function when a detected fingerprint substantially coincides with a second fingerprint different from the first fingerprint from a plurality of registered fingerprints of the user.
7. The method according to claim 6, further comprising:
executing authentication based on a detected fingerprint;
executing the first function when a detected fingerprint substantially coincides with the first fingerprint and the authentication of the user succeeds;
executing the second function when a detected fingerprint substantially coincides with the second fingerprint and the authentication succeeds; and
restricting execution of at least one of the first function and the second function when the authentication failed or is not executed.
8. The method according to claim 7, further executing a third function, prior to the execution of the first function or the second function respectively when the authentication succeeds.
9. The method according to claims 6, wherein presetting a distinct function to each of the plurality of registered functions corresponding to the plurality of registered fingerprints.
10. The method according to claims 6, further executing a preset function when a detected fingerprint does not coincide with any of the plurality of registered fingerprints.
11. A computer program product having a non-transitory computer readable medium including programmed instructions for controlling an electronic device capable to detect a fingerprint, wherein the instructions, when executed by a computer, cause the computer to execute:
a first function when a detected fingerprint substantially coincides with a first fingerprint from a plurality of registered fingerprints of a user; and
a second function different from the first function when a detected fingerprint substantially coincides with a second fingerprint different from the first fingerprint from a plurality of registered fingerprints of the user.
12. The computer program product according to claim 11, wherein the instructions further cause the computer to execute:
authentication based on a detected fingerprint;
the first function when a detected fingerprint substantially coincides with the first fingerprints and the authentication of the user succeeds;
the second function when a detected fingerprint substantially coincides with the second fingerprint and the authentication succeeds; and
restriction of at least one of the first function and the second function when the authentication fails or is not executed.
13. The computer program product according to claim 12, wherein the instructions further cause the computer to execute a third function, prior to the execution of the first function or the second function respectively when the authentication succeeds.
14. The computer program product according to claims 11, wherein the instructions further cause the computer to execute to preset a distinct function to each of the plurality of registered functions corresponding to the plurality of registered fingerprints.
15. The computer program product according to claims 11, wherein the instructions further cause the computer to execute a preset function when a detected fingerprint does not coincide with any of the plurality of registered fingerprints.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. Process for the preparation of 2-(diphenylmethyl)thioacetamide a compound of formula (I) comprising reacting 2-(diphenylmethyl)thioacetic acid, a compound of formula (III) with alcohols, in presence of catalytic amount of inorganic acid or organic acid at reflux temperature of alcohol to obtain ester of formula (V) which is reacted with ammonia to give 2-(diphenylmethyl)thioacetamide
2. Process according to claim 1, wherein R is an alkyl group with 1 to 6 carbon atoms and if desired 2-(diphenylmethyl)thioacetamide thus produced is reacted with hydrogen peroxide to produce Modafinil, a compound of formula (II).
3. Process according to claim 1, wherein said ammonia is added to said ester in-situ.
4. Process according to claim 1, wherein said ammonia is added to ester after isolating the said ester from the reaction mixture.
5. Process according to claim 1, wherein the said alcohol is selected from alcohols with alkyl groups with one to six carbon atoms.
6. Process according to claim 4, wherein the said alcohol is selected from methanol, ethanol, n-propanol or n-butanol.
7. Process according to claim 5, wherein the said alcohol is selected preferably from methanol and ethanol.
8. Process according to claim 1, wherein the said inorganic acid is selected from mineral acids.
9. Process according to claim 7, wherein the said mineral acid is selected from conc. H2SO4 and HCl.
10. Process according to claim 1, wherein the said organic acids are selected from alkyl and aryl sulphonic acids and their derivatives.
11. Process according to claim 9, wherein the said sulphonic acids are selected from p-toluenesulphonic acid and methanesulphonic acid.
12. Process according to claim 1, wherein the said ammonia is purged into the solution of ester (V) in alcohol.
13. Process according to claim 1, wherein said ammonia is alcoholic ammonia.
14. Process according to claim 12, wherein the said alcoholic ammonia is prepared by passing ammonia through alcohols, preferably through methanol and ethanol before reaction.
15. Process according to claim 1, wherein the pressure of said ammonia is maintained at 0 to 6 kg , preferably 1.5-2 kg.
16. Process according to claim 1 wherein, the temperature for preparing 2-(diphenylmethyl)thioacetamide is maintained at 20-80\xb0 C. preferably 25-35\xb0 C.
17. (canceled)