Author: claimsbot

1. A flicker detection method for detecting a flicker from an image signal, comprising the steps of:
(a) calculating a luminance difference between neighboring pixels;
(b) summing up the luminance difference in a predetermined direction if the difference is greater than a threshold value;
(c) performing a motion estimation by using a sum calculated through step (b) to thereby calculate a motion displacement;
(d) performing a motion compensation to a current frame data by using the motion displacement;
(e) calculating a difference between a previous frame data and the compensated current frame data; and
(f) detecting the flicker by using the difference calculated in step (e).
2. The flicker detection method as recited in claim 1, wherein step (b) excludes the luminance difference from a summation if the luminance difference is less than the threshold value.
3. The flicker detection method as recited in claim 2, wherein the flicker is partially removed by steps (a) and (b).
4. The flicker detection method as recited in claim 3, wherein steps (a) and (b) use one line memory.
5. The flicker detection method as recited in claim 4, wherein step (a) calculates the luminance difference between the neighboring pixels in one line.
6. The flicker detection method as recited in claim 5, wherein the predetermined direction is one of a row direction and a column direction.
7. The flicker detection method as recited in claim 6, wherein step (c), an initial position of the motion estimation is decided depending on a search range.
8. The flicker detection method as recited in claim 7, wherein step (c) includes the steps of:
calculating a sum of absolute difference (SAD) from the initial position to a block size of a search window; and
selecting the least SAD as the motion displacement.
9. The flicker detection method as recited in claim 8, wherein step (d) includes a step of moving the previous frame data as much as the motion displacement of the compensated current frame data.
10. The flicker detection method as recited in claim 9, wherein step (e) uses a sum of a plurality of pixels in the specific direction.
11. The flicker detection method as recited in claim 10, wherein the specific direction is one of a row direction and a column direction.
12. The flicker detection method as recited in claim 11, wherein step (f) includes the steps of:
filtering the difference between the previous frame data and the compensated current frame data to thereby detect a plurality of local minima; and
detecting a flicker period by using the local minima.
13. The flicker detection method as recited in claim 12, wherein the flicker period is used for determining whether the flicker is occurred or not.
14. The flicker detection method as recited in claim 11, wherein step (f) includes the steps of:
filtering the difference between the previous frame data and the compensated current frame data to thereby detect a plurality of local maxima; and
detecting a flicker period by using the local maxima.
15. The flicker detection method as recited in claim 14, wherein the flicker period is used for determining whether the flicker is occurred or not.
16. The flicker detection method as recited in claim 4, wherein step (a) calculates the luminance difference between the neighboring pixels, wherein each of the neighboring pixels are placed in neighboring two lines, respectively.
17. The flicker detection method as recited in claim 16, wherein the predetermined direction is one of a row direction and a column direction.
18. The flicker detection method as recited in claim 17, wherein step (c), an initial position of the motion estimation is decided depending on a search range.
19. The flicker detection method as recited in claim 18, wherein step (c) includes the steps of:
calculating a sum of absolute difference (SAD) from the initial position to a block size of a search window; and
selecting the least SAD as the motion displacement.
20. The flicker detection method as recited in claim 19, wherein step (d) includes a step of moving the previous frame data as much as the motion displacement of the compensated current frame data.
21. The flicker detection method as recited in claim 20, wherein step (e) uses a sum of a plurality of pixels in the specific direction.
22. The flicker detection method as recited in claim 21, wherein the specific direction is one of a row direction and a column direction.
23. The flicker detection method as recited in claim 22, wherein step (f) includes the steps of:
filtering the difference between the previous frame data and the compensated current frame data to thereby detect a plurality of local minima; and
detecting a flicker period by using the local minima.
24. The flicker detection method as recited in claim 23, wherein the flicker period is used for determining whether the flicker is occurred or not.
25. The flicker detection method as recited in claim 24, wherein step (f) includes the steps of:
filtering the difference between the previous frame data and the compensated current frame data to thereby detect a plurality of local maxima; and
detecting a flicker period by using the local maxima.
26. The flicker detection method as recited in claim 25, wherein the flicker period is used for determining whether the flicker is occurred or not.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

In the claims:

1. A card with information thereon, comprising:
a first portion having a telephone number thereon capable of being used to connect a computer device to an internet service provider via a telephone connection and a global computer network;
a second portion having a code thereon, wherein said code can be used as a password for enabling said computer device to be connected to said global computer network, and have access to an account associated with said code; and
a third portion indicating the amount of time that has been allocated to said account.
2. The card of claim 1, wherein said card has a fourth portion with information regarding the internet service provider, and a fifth portion with connective identification.
3. The card of claim 2, wherein said connective identification is a website or email address of the internet service provider.
4. The card of claim 1, wherein a removable protective cover is provided to conceal the information on said second portion.
5. The card of claim 4, wherein said protective cover is comprised of scratch-off paint or other scratch-off material.
6. The card of claim 4, wherein said protective cover is comprised of a peel-off strip.
7. The card of claim 1, wherein one or more removable protective covers are provided to conceal the information on said first and second portions.
8. The card of claim 1, wherein said telephone number is a toll-free number.
9. The card of claim 1, wherein said code comprises alpha-numeric symbols.
10. The card of claim 1, wherein said code is assigned to an account, wherein the time allocated to the account determines how long the computer can remain connected to said global computer network.
11. A card comprising:
a first portion having a telephone number thereon capable of being used to connect a computer device to an internet service provider via a telephone connection and a global computer network;
a second portion having a code thereon, wherein said code can be used as a password for enabling said computer device to be connected to said global computer network, and have access to an account associated with said code; and
wherein one or more removable protective covers are provided to conceal the information on said first andor second portions.
12. The card of claim 11, wherein said one or more protective covers are comprised of scratch-off paint or other scratch-off material.
13. The card of claim 11, wherein said one or more protective covers are comprised of a peel-off strip.
14. The card of claim 11, wherein a predetermined amount of time has been allocated to said account, and wherein the time allocated to said account determines how long the computer can remain connected to said global computer network.
15. A method of providing a card to connect to a global computer network, comprising:
providing a card with a telephone number and code thereon;
enabling a computer to be used to enter the telephone number and code to connect to said global computer network and access an account associated with said code;
allocating a predetermined amount of time on said account; and
enabling said computer to be connected to said global computer network for said predetermined amount of time, wherein said connection is terminated at the expiration of said amount of time.
16. The method of claim 15, wherein multiple cards are provided, and a different code is provided on each card, and each code is assigned to a different account.
17. The method of claim 16, wherein a first portion of said multiple cards is provided with codes that are assigned to accounts having a first predetermined amount of time allocated thereto, and a second portion of said multiple cards is provided with codes that are assigned to accounts having a second predetermined amount of time allocated thereto.
18. The method of claim 15, wherein a notification that the amount of time is about to expire is given.
19. The method of claim 15, wherein said predetermined amount of time allocated to said account can be adjusted.

1. A method for forming a flash memory, comprising:
providing a substrate having at least a doped region therein;
forming a plurality of trenches within the doped region in the substrate to define remained doped regions;
forming charge-trapping spacers on sidewalls of the trenches;
forming a gate oxide layer on bottom surfaces of the trenches and on top surfaces of the remained doped regions;
forming a polysilicon layer over the substrate, filling up the trenches and covering the charge-trapping spacers and the gate oxide layer; and
patterning the polysilicon layer.
2. The method of claim 1, wherein each of the charge-trapping spacers consists of a composite ONO (silicon oxidesilicon nitridesilicon oxide) structure.
3. The method of claim 2, wherein the step of forming the charge-trapping spacers further comprises:
sequentially depositing an oxide layer, a silicon nitride layer and a top oxide layer over the substrate and covering the trenches; and
etching back the tunnel oxide layer, the silicon nitride layer and the top oxide layer until the bottom surfaces of the trenches are exposed, so as to form the charge-trapping spacers on the sidewalls of the trenches.
4. The method of claim 2, wherein the step of forming the charge-trapping spacers further comprises:
sequentially depositing an oxide layer and a silicon nitride layer over the substrate and covering the trenches;
etching back the tunnel oxide layer and the silicon nitride layer to form first spacers on the sidewalls of the trenches;
depositing a top oxide layer over the substrate and covering the first spacers; and
etching back the top oxide layer to form second spacers resting on the first spacers, wherein the charge-trapping spacer consists of the first spacer and the second spacer.
5. The method of claim 1, wherein a depth of the trenches is about 500-1000 angstroms.
6. The method of claim 1, wherein the gate oxide layer is formed after forming the charge-trapping spacers.
7. A structure of a flash memory, comprising:
a substrate;
a plurality of raised sourcedrain regions on the substrate;
a plurality of charge-trapping spacers on sidewalls of the raised sourcedrain regions;
a plurality of gate structures covering the charge-trapping spacers and the raised sourcedrain regions; and
an oxide layer located between the gate structure and the raised sourcedrain regions and between the gate structure and the substrate, wherein the gate structures are strip structures in parallel that function as word lines and run across above the raised sourcedrain regions that function as bit lines.
8. The structure of claim 7, wherein each of the charge-trapping spacers consists of a composite oxidenitrideoxide (ONO) structure.
9. The structure of claim 8, wherein the composite oxidenitrideoxide (ONO) structure comprises a tunnel oxide layer of about 40-60 angstroms, a silicon nitride layer of about 40-60 angstroms and a top oxide layer of about 40-60 angstroms.
10. The structure of claim 7, wherein portions of the raised sourcedrain regions are overlapped with the gate structures and the charge-trapping spacers are disposed beneath the gate structures and right on the sidewalls of the overlapped portions of the raised sourcedrain regions.
11. The structure of claim 10, wherein the word lines are perpendicular to the bit lines.
12. The structure of claim 7, wherein the raised sourcedrain regions are strip structures arranged in parallel and with trenches in-between, and portions of the word lines are disposed within the trenches between the raised sourcedrain regions and covering the dielectric spacers.
13. The structure of claim 12, wherein the word lines are perpendicular to the bit lines.
14. The structure of claim 12, wherein a height of the raised sourcedrain regions is about 500-1000 angstroms and a depth of the trenches is about the same as the height of the raised sourcedrain regions.
15. A flash memory cell, comprising:
a substrate;
a first raised sourcedrain region on the substrate;
a second raised sourcedrain region on the substrate, wherein the first and second raised sourcedrain regions are separated by a trench in-between;
a first spacer on a sidewall of the first raised sourcedrain region;
a second spacer on a sidewall of the second raised sourcedrain region, wherein the first and second spacers are disposed on the opposite sidewalls of the trench;
a gate structure covering the first and second spacers, the trench and the first and second raised sourcedrain regions; and
a gate oxide layer located between the gate structure and the first and second raised sourcedrain regions and between the gate structure and the substrate.
16. The structure of claim 15, wherein the first spacer consists of a composite oxidenitrideoxide (ONO) structure.
17. The structure of claim 16, wherein the composite oxidenitrideoxide (ONO) structure comprises a tunnel oxide layer of about 40-60 angstroms, a silicon nitride layer of about 40-60 angstroms and a top oxide layer of about 40-60 angstroms.
18. The structure of claim 15, wherein the second spacer consists of a composite oxidenitrideoxide (ONO) structure.
19. The structure of claim 18, wherein the composite oxidenitrideoxide (ONO) structure comprises a tunnel oxide layer of about 40-60 angstroms, a silicon nitride layer of about 40-60 angstroms and a top oxide layer of about 40-60 angstroms.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A flat panel display comprising:
an insulating substrate;
a data line formed on the insulating substrate;
an interlayer insulating film formed on the data line having a first contact opening exposing the data line;
a connecting member formed in a part of the first contact opening;
a gate insulating film formed on the connecting member having a second contact opening exposing the connecting member; and
an organic semiconductor layer formed on the gate insulating film,
wherein the second contact opening does not overlap the first contact opening.
2. The flat panel display according to claim 1, wherein the data line comprises a data line and a data pad.
3. The flat panel display according to claim 2, further comprising a transparent electrode layer formed on the gate insulating film, wherein the transparent electrode layer comprises a source electrode connected with the connecting member through the second contact opening and contacted to at least a part of the organic semiconductor layer, a drain electrode separated from the source electrode by the organic semiconductor layer, and a pixel electrode connected to the drain electrode.
4. The flat panel display according to claim 3, wherein the transparent electrode layer further comprises a data pad contact member connected to the data pad.
5. The flat panel display according to claim 1, wherein the gate insulating film is composed of organic material.
6. The flat panel display according to claim 1, wherein a height of the connecting member exposed by the second contact opening is greater than that of the connecting member formed on the first contact opening.
7. The flat panel display according to claim 1, further comprising a gate electrode formed on the same layer with the connecting member, wherein the gate electrode is located in a lower part of the organic semiconductor layer.
8. The flat panel display according to claim 3, further comprising a gate line formed to intersect with the data line to define a pixel area, and a gate pad which is provided in the end of the gate line, wherein the gate line and the gate pad are formed on the same layer with the connecting member.
9. The flat panel display according to claim 8, wherein a third contact opening to expose the gate pad is formed on the gate insulating film provided on the gate pad.
10. The flat panel display according to claim 9, wherein the transparent electrode layer further comprises a gate pad contact part connected to the gate pad through the third contact opening.
11. The flat panel display according to claim 3, wherein the transparent electrode layer is composed of one of ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide).
12. The flat panel display according to claim 1, further comprising a passivation layer formed on the organic semiconductor layer.
13. The flat panel display according to claim 9, wherein a thickness of the gate insulating film on which the second contact opening is formed is substantially the same as the thickness of the gate insulating film on which the third contact opening is formed.