Author: claimsbot

1. A switching voltage regulator, comprising:
a comparison module configured to receive a reference voltage and a feedback voltage and to generate a comparison signal corresponding to a difference between the reference voltage and the feedback voltage;
an offset module configured to generate an offset signal based on a number of active phases of the voltage regulator;
an adder configured to generate a control signal based on the comparison signal and the offset signal;
a plurality of pulse-width-modulated (PWM) power stages; and
a control module configured to control the plurality of PWM power stages based at least in part on the control signal generated by the adder.
2. The switching voltage regulator of claim 1 wherein the comparison signal is a comparison voltage and the comparison module comprises an error amplifier configured to receive the reference voltage and the feedback voltage and to generate the comparison voltage.
3. The switching voltage regulator of claim 2 wherein the control signal is a control voltage, the offset signal is an offset voltage and the adder is configured to generate the control voltage as a sum of said comparison voltage and the offset voltage, wherein the control module comprises:
a voltage controlled oscillator configured to generate a train of pulses at a frequency based on said control voltage; and
a state machine configured to receive the train of pulses generated by said voltage controlled oscillator and to generate for each of active phase of the regulator a respective train of pulses obtained by frequency division of the received train of pulses.
4. The switching voltage regulator of claim 3 wherein the plurality of PWM power stages comprises:
a plurality of generators of PWM pulses, each connected such to drive a respective PWM power stage to supply a respective phase winding of the regulator.
5. The switching voltage regulator of claim 2, comprising a feedback impedance connected between an output terminal of the regulator and a feedback terminal of the error amplifier, and an integrating network connected between said feedback terminal and an output terminal of the error amplifier.
6. The switching voltage regulator of claim 5 wherein the offset signal is an offset voltage and the offset module is configured to receive an output voltage of the switching voltage regulator and to generate the offset voltage.
7. The switching voltage regulator of claim 1 wherein,
the comparison module comprises:
an analog-to-digital converter configured to receive the reference voltage and the feedback voltage; and
a proportional-integral-derivative (PID) controller configured to receive an output of the analog-to-digital converter and to generate the comparison signal; and

the control module comprises:
an accumulator configured to generate a train of pulses at a frequency based on said control signal; and
an interleaving oscillator configured to generate a plurality of pulse trains based on the train of pulses generated by the accumulator.
8. The switching voltage regulator of claim 7 wherein the offset module is configured to generate the offset signal based on the number of active phases of the voltage regulator, a gain of the accumulator and a switching frequency of the voltage regulator.
9. A method, comprising:
generating a regulated voltage which tracks a reference voltage using a constant-on-time switching voltage regulator by:
generating an offset signal based on a number N of active phases of the voltage regulator;
generating a comparison signal based on the reference voltage and a feedback voltage;
generating a control signal based on the offset signal and the comparison signal.
10. The method of claim 9 wherein the offset signal is based on the regulated voltage output by the voltage regulator and the constant-on-time switching voltage regulator comprises:
an error amplifier configured to receive on an input terminal said reference voltage and on another input terminal the feedback voltage available on a feedback terminal of the regulator, and to generate on a comparison terminal a comparison voltage corresponding to a difference between the reference voltage and the feedback voltage;
an adder configured to generate a control voltage as sum of said comparison voltage and an offset voltage;
a voltage controlled oscillator controlled by said adder, configured to generate a train of pulses at a frequency determined by said control voltage;
a state machine configured to receive the train of pulses generated by said voltage controlled oscillator, and to generate for each of active phase of the regulator a respective train of pulses obtained by frequency division by N of the received train of pulses;
a plurality of generators of PWM pulses, each configured to drive a respective PWM power stage;
a feedback impedance connected between an output terminal and a feedback terminal of the error amplifier; and
an integrating network connected between said feedback terminal and an output of the error amplifier.
11. The method of claim 9 wherein the offset signal is an offset voltage proportionally to said regulated voltage with a proportionality factor based on the number of active phases of the regulator.
12. The method of claim 11 wherein the proportionality factor is determined such to keep substantially constant a voltage drop on said integrating network when at least a phase of the regulator is turned on or off.
13. The method of claim 11, comprising updating the value of said proportionality factor each time that at least a phase of the voltage regulator is turned on or off.
14. The method of claim 9 wherein the offset signal is a product of the regulated voltage and the number of active phases of the voltage regulator.
15. The method of claim 9, comprising turning off a phase in an instant in which current flowing through a respective winding nullifies.
16. The method of claim 9 wherein the voltage regulator comprises:
an analog-to-digital converter configured to receive the reference voltage and the feedback voltage;
a proportional-integral-derivative (PID) controller configured to receive an output of the analog-to-digital converter and to generate the comparison signal;
an adder configured to generate the control signal based on the comparison signal and the offset signal;
an accumulator configured to generate a train of pulses at a frequency based on said control signal; and
an interleaving oscillator configured to generate a plurality of pulse trains based on the train of pulses generated by the accumulator.
17. The method of claim 16 wherein the offset signal is inversely proportional to a gain of the accumulator and directly proportional to a switching frequency and the number of active phases of the voltage regulator.
18. A system, comprising:
a processor; and
a switching voltage regulator configured to provide power to the processor and including:
a comparison module configured to receive a reference voltage and a feedback voltage and to generate a comparison signal corresponding to a difference between the reference voltage and the feedback voltage;
an offset module configured to generate an offset signal based on a number of active phases of the voltage regulator;
an adder configured to generate a control signal based on the comparison signal and the offset signal;
a plurality of pulse-width-modulated (PWM) power stages; and
a control module configured to control the plurality of PWM power stages based at least in part on the control signal generated by the adder.
19. The system of claim 18 wherein the comparison signal is a comparison voltage and the comparison module comprises an error amplifier configured to receive the reference voltage and the feedback voltage and to generate the comparison voltage.
20. The system of claim 19 wherein the control signal is a control voltage, the offset signal is an offset voltage, the adder is configured to generate the control voltage as a sum of said comparison voltage and the offset voltage, and the control module comprises:
a voltage controlled oscillator configured to generate a train of pulses at a frequency based on said control voltage; and
a state machine configured to receive the train of pulses generated by said voltage controlled oscillator and to generate for each of active phase of the regulator a respective train of pulses obtained by frequency division of the received train of pulses.
21. The system of claim 19, comprising a feedback impedance connected between an output terminal of the regulator and a feedback terminal of the error amplifier, and an integrating network connected between said feedback terminal and an output terminal of the error amplifier.
22. The system of claim 21 wherein the offset module is configured to generate the offset signal by multiplying an output voltage of the switching voltage regulator by the number of active phases of the voltage regulator.
23. The system of claim 18 wherein the comparison module comprises:
an analog-to-digital converter configured to receive the reference voltage and the feedback voltage; and
a proportional-integral-derivative (PID) controller configured to receive an output of the analog-to-digital converter and to generate the comparison signal.
24. The system of claim 23 wherein the control module comprises:
an accumulator configured to generate a train of pulses at a frequency based on said control signal; and
an interleaving oscillator configured to generate a plurality of pulse trains based on the train of pulses generated by the accumulator.
25. The system of claim 24 wherein the offset signal is inversely proportional to a gain of the accumulator and directly proportional to a switching frequency and number of active phases of the voltage regulator.
26. A system, comprising:
means for generating an offset signal based on a number of active phases of a voltage regulator;
means for generating a comparison signal based on a reference voltage and a feedback voltage; and
means for generating a voltage regulator control signal based on the offset signal and the comparison signal.
27. The system of claim 26, further comprising a voltage controlled oscillator, wherein the means for generating the offset signal comprises a multiplier configured to multiply a voltage regulator output by the number of active phases.
28. The system of claim 26, further comprising an accumulator, wherein the means for generating the offset signal is configured to generate the offset signal based on a gain of the accumulator and a switching frequency of the voltage regulator.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A character animation system comprising:
a data generating unit for generating a character skin mesh and an internal reference mesh, a character bone value, and a character solid-body value;
a skin distortion representing unit for representing skin distortion using the generated character skin mesh and the internal reference mesh when an external shock is applied to a character; and
a solid-body simulation engine for applying the generated character bone value and the character solid-body value to a real-time physical simulation library and representing character solid-body simulation.
2. The system of claim 1, further comprising a skin distortion and solid-body simulation processing unit for processing to return to a key frame to be newly applied after the skin distortion and the solid-body simulation are represented.
3. The system of claim 2, wherein the skin distortion and solid-body simulation processing unit represents weighted blending between the character solid-body simulation and the key frame for real time representation by an equation:
Ani(Character, t)=W(t)*Ani(solid-body simulation, t) +(1\u2212W(t))*Ani(key frame, t),
where W(t) is a weight of the character solid-body simulation at a time t, and (1\u2212W(t)) is a weight of the key frame animation at a time t, and upon weighted blending, the skin distortion and solid-body simulation processing unit blends rotation values of respective joints using Spherical Linear interpolation (SLERP) with a weight, and blends location values through linear interpolation of the weight.
4. The system of claim 1, wherein the skin distortion representing unit has a spring structure in which edges between a vertex of the internal reference mesh and a vertex of the character skin mesh and between vertexes of the character skin mesh are spring, and represents laterally shoved skin, sunken skin, and stretched skin through animation.
5. The system of claim 4, wherein the edges have a predetermined spring constant and an initial mesh shape is regarded as a stable state.
6. The system of claim 1, wherein the skin distortion representing unit operates in proportion to a distance between a vertex of the character skin mesh and a corresponding vertex of the internal reference mesh, and represents the skin distortion by much accepting a skin distortion force and decreasing the size of force applied to solid-body simulation when the distance is long and by less accepting the skin distortion force and increasing the size of the force applied to the solid-body simulation when the distance is short.
7. The system of claim 1, wherein the internal reference mesh is generated by matching the character with a skeleton, a size of a muscle mesh, and a posture, discovering a point at which a distance between the skeleton and the muscle mesh at each skin vertex of the character is smallest, forming a virtual sphere around each skin vertex of the character, gradually increasing a radius of the sphere, stopping increasing the radius when a collision with the triangles of the skeleton and the muscle mesh occurs, taking the radius at this time as a thickness, storing a collision point to calculate a thickness between the skeleton and the muscle mesh at each skin vertex of the character, correcting the calculated thickness value using a painting unit, and using the corrected thickness value.
8. The system of claim 1, wherein the internal reference mesh is an internal threshold surface on which the skin is no longer sunken in representing the distortion of the character skin model.
9. The system of claim 1, wherein the internal reference mesh is invisible on a screen during actual rendering and used for controlling a motion in animation.
10. The system of claim 1, wherein the character solid-body simulation includes the solid body of the character and imposes limiting points to joint rotation.
11. The system of claim 1, wherein the character solid-body simulation takes a location, strength, and direction of force, as inputs.
12. A character animation method, comprising:
generating a character skin mesh for each vertex of the character;
generating an internal reference mesh of a character;
generating a bone value of the character;
generating a solid body value of the character;
representing skin distortion using the generated character skin mesh and the generated internal reference mesh;
applying the generated character bone value and the generated character solid-body value to a real-time physical simulation library to represent character solid-body simulation; and
processing to return to a key frame to be newly applied after representing the skin distortion and the solid-body simulation.
13. The method of claim 12, wherein the internal reference mesh is generated by matching the character with a skeleton, a size of a muscle mesh, and a posture, discovering a point at which a distance between the skeleton and the muscle mesh at each skin vertex of the character is smallest, forming a virtual sphere around each skin vertex of the character, gradually increasing a radius of the sphere, stopping increasing the radius when a collision with the triangles of the skeleton and the muscle mesh occurs, taking the radius at this time as a thickness, storing a collision point to calculate a thickness between the skeleton and the muscle mesh at each skin vertex of the character, correcting the calculated thickness value using a painting unit, and using the corrected thickness value.
14. The method of claim 12, wherein the internal reference mesh is an internal threshold surface on which the skin is no longer sunken in representing the distortion of the character skin model.
15. The method of claim 12, wherein the internal reference mesh is invisible on a screen upon actual rendering and used for controlling a motion in animation.

1. A computer system, comprising:
a computer chassis housing a processor and having an airflow pathway through the computer chassis;
a dust filter disposed in the airflow pathway;
a plurality of electrodes disposed across an area of the dust filter;
a voltage source having a negative terminal and a positive terminal; and
a controller for selectively coupling a first subset of the plurality of electrodes to the negative terminal and selectively coupling a second subset of the plurality of electrodes to the positive terminal, wherein a voltage differential between the first subset of electrodes and the second subset of electrodes is sufficient to cause electrostatic movement of dust from an area of the dust filter near the first subset of electrodes to an area of the dust filter near the second subset of electrodes.
2. The computer system of claim 1, wherein the first subset of electrodes is disposed above the second subset of electrodes to move the dust in a generally downward direction.
3. The computer system of claim 2, further comprising:
a damper disposed below the dust filter, wherein the damper opens into communication with a duct through the computer chassis to the rear of the computer chassis.
4. The computer system of claim 3, wherein the duct does not contain heat-generating components.
5. The computer system of claim 4, further comprising:
a fan that draws air through the duct to the rear of the computer chassis when the damper is open.
6. The computer system of claim 3, further comprising:
a fan that draws air through the airflow pathway.
7. The computer system of claim 6, wherein the fan draws air through the duct wherein the damper is open.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A semiconductor device comprising a transistor, the transistor comprising:
an oxide semiconductor over a substrate, the oxide semiconductor including a bottom surface, a top surface and side surfaces, the side surfaces extending in a channel length direction of the transistor, wherein a height of the oxide semiconductor is greater than a length of the oxide semiconductor at the bottom surface along a direction perpendicular to the channel length direction; and
a gate electrode along the top surface and the side surfaces with a gate insulating film between the gate electrode and the oxide semiconductor,
wherein the oxide semiconductor comprises a first region including crystals, and
wherein c-axes of the crystals in the first region are substantially perpendicular to a surface of the oxide semiconductor.
2. The semiconductor device according to claim 1, wherein the oxide semiconductor comprises any one of indium oxide, zinc oxide, tin oxide, an In\u2014Zn-based oxide, a Sn\u2014Zn-based oxide, an Al\u2014Zn-based oxide, a Zn\u2014Mg-based oxide, a Sn\u2014Mg-based oxide, an In\u2014Mg-based oxide, an In\u2014Sn-based oxide, an In\u2014Ga-based oxide, an In\u2014Ga\u2014Zn-based oxide, an In\u2014Sn\u2014Zn-based oxide, an In\u2014Al\u2014Zn-based oxide, a Sn\u2014Ga\u2014Zn-based oxide, an Al\u2014Ga\u2014Zn-based oxide, a Sn\u2014Al\u2014Zn-based oxide, and an In\u2014Sn\u2014Ga\u2014Zn-based oxide.
3. A random access memory comprising the transistor according to claim 1 as a cell transistor.
4. A memory comprising the transistor according to claim 1 as a writing transistor.
5. The semiconductor device according to claim 1, wherein a corner portion of the oxide semiconductor has a curved shape.
6. The semiconductor device according to claim 1, wherein part of the oxide semiconductor comprises an N-type region comprising nitrogen, boron, or phosphorus.
7. A semiconductor device comprising a transistor, the transistor comprising:
an oxide semiconductor over a substrate, the oxide semiconductor including a bottom surface, a top surface and side surfaces, the side surfaces extending in a channel length direction of the transistor, wherein a height of the oxide semiconductor is greater than a length of the oxide semiconductor at the bottom surface along a direction perpendicular to the channel length direction; and
a gate electrode along the top surface and the side surfaces with a gate insulating film between the gate electrode and the oxide semiconductor,
wherein the oxide semiconductor comprises a first region including crystals,
wherein c-axes of the crystals in the first region are substantially perpendicular to a surface of the oxide semiconductor,
wherein the first region is in contact with the top surface of the oxide semiconductor,
wherein the oxide semiconductor comprises a second region being in contact with one of the side surfaces of the oxide semiconductor,
wherein the second region includes crystals, and
wherein c-axes of the crystals in the second region are substantially perpendicular to the one of the side surfaces of the oxide semiconductor.
8. The semiconductor device according to claim 7, wherein the oxide semiconductor comprises any one of indium oxide, zinc oxide, tin oxide, an In\u2014Zn-based oxide, a Sn\u2014Zn-based oxide, an Al\u2014Zn-based oxide, a Zn\u2014Mg-based oxide, a Sn\u2014Mg-based oxide, an In\u2014Mg-based oxide, an In\u2014Sn-based oxide, an In\u2014Ga-based oxide, an In\u2014Ga\u2014Zn-based oxide, an In\u2014Sn\u2014Zn-based oxide, an In\u2014Al\u2014Zn-based oxide, a Sn\u2014Ga\u2014Zn-based oxide, an Al\u2014Ga\u2014Zn-based oxide, a Sn\u2014Al\u2014Zn-based oxide, and an In\u2014Sn\u2014Ga\u2014Zn-based oxide.
9. A random access memory comprising the transistor according to claim 7 as a cell transistor.
10. A memory comprising the transistor according to claim 7 as a writing transistor.
11. The semiconductor device according to claim 7, wherein a corner portion of the oxide semiconductor has a curved shape.
12. The semiconductor device according to claim 7, wherein part of the oxide semiconductor comprises an N\u2014type region comprising nitrogen, boron, or phosphorus.