Author: claimsbot

1. A liquid crystal display device comprising:
a first substrate on which a thin film transistor and a first alignment film are formed;
a second substrate, opposed to the first substrate, on which a second alignment film is formed; and
a liquid crystal layer sandwiched between the first substrate and the second substrate, wherein
the first substrate and the second substrate are bonded to each other with a seal member,
a frame is arranged inside the seal member around the first alignment film to surround the first alignment film, and
a material forming the frame is a highly water repellent organic material having low solubility in an application liquid for forming the first alignment film.
2. The liquid crystal display device according to claim 1, wherein the application liquid for forming the first alignment film is a GBL (\u03b3-butyrolactone) rich liquid.
3. The liquid crystal display device according to claim 1, wherein, a width of the frame is a value in a range from 50 \u03bcm to 300 \u03bcm.
4. The liquid crystal display device according to claim 1, wherein a height of the frame is a value in a range from 0.3 \u03bcm to 1.0 \u03bcm.
5. The liquid crystal display device according to claim 1, wherein the frame is formed on an organic insulation film arranged on the first substrate.
6. The liquid crystal display device according to claim 5, wherein the frame is formed on a groove provided in a frame configuration in the organic insulation film.
7. The liquid crystal display device according to claim 5, wherein the organic insulation film has a slit filled with the seal member.
8. The liquid crystal display device according to claim 1, wherein a surface region of the first substrate on which the first alignment film is formed is more uneven than a surface region of the second substrate on which the second alignment film is formed.
9. A liquid crystal display device comprising:
a first substrate having a display region on which a first alignment film is formed;
a second substrate, opposed to the first substrate, on which a second alignment film is formed; and
a liquid crystal layer sandwiched between the first substrate and the second substrate, wherein
the first substrate and the second substrate are bonded to each other with a seal member,
a driving circuit portion is provided on the first substrate, and a frame is arranged between the driving circuit portion and the display region,
the first alignment film is arranged to extend from the frame to the display region, and
a material for forming the frame is a highly water repellent organic material having low solubility in an application liquid for forming the first alignment film.
10. The liquid crystal display device according to claim 9, wherein a width of the frame is a value in a range from 50 \u03bcm to 300 \u03bcm.
11. The liquid crystal display device according to claim 9, wherein a height of the frame is a value in a range from 0.3 \u03bcm to 1.0 \u03bcm.
12. The liquid crystal display device according to claim 9, wherein the frame is formed on an organic insulation film arranged on the first substrate.
13. A manufacturing method of a liquid crystal display device comprising:
a first step of preparing a first substrate on which thin film transistors are formed;
a second step of forming a frame on the first substrate by ink jet application;
a third step of applying an application liquid for forming a first alignment film on one of two regions sectioned by the frame by ink jet application;
a fourth step of forming the first alignment film;
a fifth step of preparing a second substrate on which a second alignment film is formed; and
a sixth step of arranging a liquid crystal layer between the first substrate and the second substrate that are arranged such that the first alignment film and the second alignment film are opposed to each other, in a region surrounded by a seal member,
wherein a material forming the frame is a highly water repellent organic material having a low solubility in the application liquid for forming the first alignment film.
14. The manufacturing method of the liquid crystal display device according to claim 13, wherein the first substrate is heated when the frame is formed in the second step.
15. The manufacturing method of the liquid crystal display device according to claim 13, wherein the first alignment film is formed by irradiating the applied application liquid with light.
16. The manufacturing method of the liquid crystal display device according to claim 13, wherein the second step includes a step of applying an application liquid for forming the frame and a step of drying it, while the first substrate is heated.
17. The manufacturing method of the liquid crystal display device according to claim 13, wherein a temperature of the first substrate in the third step is lower than a temperature of the first substrate in the fourth step.
18. The manufacturing method of the liquid crystal display device according to claim 13, wherein a temperature of the first substrate in the fourth step is lower than a temperature of the first substrate in the second step.
19. The manufacturing method of the liquid crystal display device according to claim 13, wherein the application liquid for forming the first alignment film in the third step has a lower viscosity than an application liquid for forming the second alignment film.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A microprocessor, comprising:
a branch unit to process branch instructions and provide a fetch unit with a next instruction address;
a loadstore unit (LSU) to retrieve data from and stored data to a data memory of the microprocessor;
an arithmetic logic unit (ALU) to performing arithmetic operations on scalar, integer data; and
a vector unit to execute a vector instruction to perform a first operation on a first set of data operands and a second operation on a second set of operands, wherein the first and second operations differ.
2. The microprocessor of claim 1, wherein the vector unit comprises a primary register file and a secondary register, wherein an operand field in the vector instruction specifies a register within the primary register file and a corresponding register within the secondary register file.
3. The microprocessor of claim 2, wherein the vector instruction comprises fields for first, second, and third operand field, wherein the first, second, and third operand fields specify as many as three operands on which the first operation is to be performed and as many as three operands on which the second operation is to be performed.
4. The microprocessor of claim 3, wherein the vector unit includes a 3-input primary floating point unit and a 3-input secondary floating point unit, wherein the 3-input primary floating point unit is configured to perform a floating point operation on the first set of operands and the 3-input secondary floating point unit is configured to perform a floating point operation on the second set of operands.
5. The microprocessor of claim 4, wherein the 3-input primary floating point unit is configured to multiply first and third operands and further configured to add the second operand to or subtract the second operand from the resulting product.
6. The microprocessor of claim 4, where the vector unit is configured to permit either the primary register file or the secondary register file to provide the operands for the first, second, and third inputs to the primary floating point unit and the first, second, and third inputs to the secondary floating point unit.
7. The microprocessor of claim 2, wherein the vector unit is further characterized as being enabled to perform a cross instruction in which the first and second operations both use at least one operand from the primary register file and at least one operand from the secondary register file.
8. The microprocessor of claim 2, wherein the vector unit is further characterized as being enabled to perform a cross-replicate vector instruction in which the first and second operations are both performed using at least one common operand.
9. The microprocessor of claim 2, wherein the vector unit is configured to store a real portion of a complex number in the primary register file and an imaginary portion of the complex number in the secondary register file.
10. The microprocessor of claim 9, wherein the vector unit is configured to perform a complex operation in which the imaginary portion of a first operand is multiplied by an imaginary portion of a second operand in the first operation and in which the imaginary portion of the first operand is multiplied by a real portion of the second operand in the second operation.
11. A vector unit within a microprocessor, comprising:
means for receiving an instruction specifying first operand and second operands;
means for performing a first operation on a first set of data indicated by the first and second operands and a second operation on data indicated by the first and second operands, wherein the first and second operations differ.
12. The vector unit of claim 11, wherein the first operation is selected from an addition operation and an addition and negate operation and wherein the second operation is selected from a subtract operation and a subtract and negate operation.
13. The vector unit of claim 11, wherein the instruction is further characterized as specifying a third operand and wherein the first and second operations both include multiplying data specified by a pair of the operands.
14. The vector unit of claim 11, wherein each operand indicates a primary register of a primary register file and a corresponding secondary register of a secondary register file.
15. The vector unit of claim 11, wherein the primary register is configured to store a real portion of a complex number and the corresponding secondary register is configured to store an imaginary portion of the complex number.
16. A microprocessor including:
an execution unit enabled to execute an asymmetric instruction, wherein the asymmetric instruction includes a set of operand fields and an operation code (opcode);
wherein the execution unit is configured to interpret the opcode to perform a first operation on a first set of data indicated by the set of operand fields and to perform a second operation on a second set of data indicated by the set of operand fields, wherein the set of operand fields indicate different sets of data with respect to the first and second operations and further wherein the first and second operations are mathematically different.
17. The microprocessor of claim 16, further comprising a vector register file for use in executing the asymmetric instruction, wherein the register file includes a primary register file and a secondary register file, and wherein each operand in the set of operand fields indicates a register in the primary register and a corresponding register in the secondary register file.
18. The microprocessor of claim 16, wherein the instruction includes indicates first, second, and third operand fields indicating first and second sets of data on which the first and second operations are performed.
19. The microprocessor of claim 16, wherein each operand indicates a primary register in a primary register file and a corresponding secondary register in a secondary register file.
20. The microprocessor of claim 19, wherein the primary register file is configured to store a real portion of a complex number and wherein the secondary register file is configured to store an imaginary portion of a complex number.

1. A digitally encoded switch system for operating a plurality of vehicle lamps comprising:
a plurality of vehicle lamps;
a multi-position switch circuit having a plurality of selectable switch positions, the multi-position switch circuit being connected to a voltage source and including a plurality of switch contacts for selectively connecting given ones of the switch contacts to the voltage source for creating different open and closed circuit conditions for corresponding positions of the multi-position switch circuit;
a control module including a microprocessor connected to the multi-position switch circuit and to the plurality of vehicle lamps for illuminating selected ones of the vehicle lamps in accordance with the open and closed circuit conditions created by the multi-position switch circuit.
2. The digitally encoded switch system of claim 1 in which the switch contacts of the multi-position switch circuit provide digitally coded signals wherein an open circuit condition manifests a first binary state and a closed circuit condition manifests a second binary state, and wherein the control module microprocessor is responsive to the digitally coded signals manifested by the circuit conditions of the multi-position switch circuit to illuminate selected ones of the vehicle lamps in accordance with the digital code; and
wherein the digitally encoded switch system includes failure mode robustness via decode software that that interprets circuit state failure modes when a line is permanently shorted or open and provides a best lighting function alternative that most closely resembles a lighting function selected by the user.
3. The digitally encoded switch system of claim 2, wherein the plurality of vehicle lamps include a left low beam headlamp and a left high beam headlamp, a right low beam headlamp and a right high beam headlamp, a left front fog lamp, a right front fog lamp, a left rear fog lamp, a right rear fog lamp, a left park lamp, and a right park lamp.
4. The digitally encoded switch system of claim 2, wherein a relay driver circuit, a multifunction switch and a relay are connected between the microprocessor and left and right high beam headlamp to selectively illuminate the headlamps in accordance with output signals from the microprocessor.
5. The digitally encoded switch system of claim 4, wherein the multi function switch can selectively illuminate the headlamps independent high beams or flash to pass (ftp) independent of a microprocessor failure.
6. The digitally encoded switch system of claim 2, wherein a left low beam high side driver circuit and a right low beam high side driver circuit are connected between the microprocessor and the left low beam headlamp and right low beam headlamp respectively to selectively illuminate the headlamps in accordance with output signals from the microprocessor.
7. The digitally encoded switch system of claim 2, wherein a front fog lamp relay and a rear fog lamp relay are connected between the multi-position switch circuit and the left front, right front, and left rear, right rear fog lamps respectively to selectively illuminate the fog lamps in accordance with output signals from the microprocessor.
8. The digitally encoded switch system of claim 2, further comprising:
an autolamp sensor device connected to the control module to provide ambient light information to the control module.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An axial flux electric motor, comprising:
a housing;
a stator having a solitary ferrous core and fixedly secured to said housing and defining an inner periphery and an outer periphery therefore;
a solitary rotor rotatably secured to said housing, the rotor including a ferrite magnet, the magnet defining at least one an outer periphery extending beyond said stator in a direction normal to the rotation of said rotor and an inner periphery extending beyond said stator in a direction normal to the rotation of said rotor, at least one of said stator or said rotor adapted for use in a fluid moving application.
2. The motor as in claim 1, wherein the ferrite magnet is generally ring shaped
3. The motor as in claim 1, wherein the ferrite magnet has a plurality of magnet segments
4. The motor as in claim 1, wherein a skewed magnetic field is induced into the magnet.
5. The motor as in claim 1, wherein the outer periphery of said ferrite magnet extends outwardly beyond said stator in a direction normal to the rotation of said ring.
6. The motor as in claim 1, wherein the inner periphery of said ferrite magnet extends inwardly beyond said stator in a direction normal to the rotation of said ring.
7. The motor as in claim 1:
wherein the outer periphery of said magnet extends beyond said stator in a direction normal to the rotation of said rotor a first extension distance;
wherein the inner periphery of said magnet extends beyond said stator in a direction normal to the rotation of said rotor a second extension distance;
wherein the ferrous core is generally ring shaped defining a ferrous core radial distance; and
wherein the first extension distance and the second extension distance may be as large as the ferrous core radial distance.
8. The motor as in claim 1:
wherein the outer periphery of said magnet extends beyond said stator in a direction normal to the rotation of said rotor, the outer periphery of said magnet defining a magnet diameter;
wherein the ferrous core of said stator defines a stator core diameter; and
wherein the magnet diameter may be as much as 50 percent larger than stator core diameter.
9. The motor as in claim 1:
wherein the rotor further includes a rotor core, the rotor core being generally ring shaped, said rotor core defining a rotor core inner periphery, a rotor core outer periphery and a rotor core radial distance between the rotor core inner periphery and the rotor core outer periphery;
wherein the outer periphery of said magnet extends beyond said rotor core in a direction normal to the rotation of said rotor a first extension distance;
wherein the inner periphery of said magnet extends beyond said rotor core in a direction normal to the rotation of said rotor a second extension distance; and
wherein the first extension distance and the second extension distance may be as large as the rotor core radial distance.
10. The motor as in claim 1:
wherein the rotor farther includes a rotor core, the rotor core being generally ring shaped, said rotor core defining a rotor core inner periphery, a rotor core outer periphery and a rotor core radial distance between the rotor core inner periphery and the rotor core outer periphery;
wherein the outer periphery of said magnet extends beyond said rotor core in a direction no mal to the rotation of said rotor, the outer periphery of said magnet defining a magnet diameter;
wherein the rotor core of said rotor defines a rotor core diameter; and
wherein the magnet diameter may be as much as 50 percent larger than rotor core diameter.
11. The motor as in claim 1:
wherein said ferrite magnet includes one of a protrusion and a recess;
wherein said rotor includes one of a protrusion and a recess; and
wherein the one of a protrusion and a recess of said ferrite magnet cooperates with the one of a protrusion and a recess of said rotor to secure said ferrite magnet to said rotor.
12. The motor as in claim 1, wherein the fluid moving application is one of an air flowing application, a liquid pumping application, a HVAC application and a blower premix application.
13. A rotor assembly or rotatable placement in a housing and for use with a stator to provide a axial flux electric motor, said rotor comprising:
a rotor rotatably secured to the housing, the rotor including:
a ferrite magnet, the magnet defining at least one an outer periphery extending beyond said stator in a direction normal to the rotation of said rotor and an inner periphery extending beyond said stator in a direction normal to the rotation of said rotor, at least one of said stator or said rotor adapted for use in a fluid moving application.
14. The rotor as in claim 13, wherein the ferrite magnet is generally ring shaped
15. The rotor as in claim 13, wherein the ferrite magnet has a plurality of magnet segments
16. The rotor as in claim 13, wherein a skewed magnetic field is induced into the magnet.
17. The rotor as in claim 13, wherein the outer periphery of said ferrite magnet extends beyond said stator in a direction normal to the rotation of said ring.
18. The rotor as in claim 13, wherein the inner periphery of said ferrite magnet extends beyond said stator in a direction normal to the rotation of said ring.
19. The rotor as in claim 13, wherein the fluid moving application is one of an air flowing application, a HVAC application and a blower premix application.
20. A method for fabricating a motor, said method comprising the steps of:
fabricating a first set of motor parts including a first rotor using neo magnets and a first stator for use in a neo motor;
fabricating a second set of motor parts including a second rotor using ferrite magnets for use in a
ferrite motor;
ascertaining the motor magnet type, ferrite or neo;
selecting one of the first rotor and the second rotor in accordance with desired motor magnet type; and
assembling a motor with one of first rotor and the second rotor and first stator such that the desired motor magnet type is substantially provided.