Author: claimsbot

1. A vehicle front portion structure comprising:
a front side member comprising
a linear portion that extends along the vehicle front and rear direction on the vehicle width direction outside of the vehicle front portion and is disposed on the vehicle front side of a dash panel, and
a slanted portion that extends obliquely downward along an undersurface of the dash panel from a rear end portion of the linear portion; and

a side portion weak portion disposed in a vehicle width direction outside surface or a vehicle width direction inside surface of the linear portion along a joint between the linear portion and the slanted portion.
2. The vehicle front portion structure of claim 1, wherein the side portion weak portion is slanted toward the vehicle front side heading from the vehicle upper side toward the vehicle lower side along the joint.
3. The vehicle front portion structure of claim 1, wherein the side portion weak portion is a recessed bead formed by making the vehicle width direction outside surface of the linear portion inwardly recessed.
4. The vehicle front portion structure of claim 1, wherein an upper portion weak portion is disposed in an upper portion of the linear portion in the region where the side portion weak portion is disposed.
5. The vehicle front portion structure of claim 4, wherein:
the linear portion comprises
a flat plate-shaped front side member outer and
a cross-sectionally hat-shaped front side member inner having an upper side flange portion and a lower side flange portion that are joined to the front side member outer, and

the upper portion weak portion comprises
an indented portion formed by indenting the upper side flange portion of the front side member inner inwardly in the vehicle width direction, and
a hole portion formed in an upper surface of the linear portion.
6. A vehicle front portion structure comprising:
a front side member, in which are integrally formed:
a linear portion that extends along the vehicle front and rear direction on the vehicle width direction outside of the vehicle front portion and is disposed on the vehicle front side of a dash panel and
a slanted portion that extends obliquely downward along an undersurface of the dash panel from a rear end portion of the linear portion; and

a side portion weak portion disposed in a vehicle width direction outside surface or a vehicle width direction inside surface of the linear portion along a rigidity changing portion set in a connecting section between the linear portion and the slanted portion.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A semiconductor device comprising:
a field effect transistor;
a schottky-barrier diode mounted in a same semiconductor substrate as said field effect transistor; and
buried doped layers spaced at a predetermined interval and buried at a predetermined depth in a drift layer of a first conductivity type in a schottky-barrier diode region, said buried doped layers having a second conductivity type.
2. A semiconductor device as set forth in claim 1, wherein said buried doped layers are spaced at a same interval as gate electrodes in said drift layer in a field effect transistor region, such that said buried doped layers contact a bottom face of a gate insulating film covering said gate electrodes.
3. A semiconductor device as set forth in claim 1, wherein said field effect transistor is of a trench gate type.
4. A semiconductor device comprising:
a semiconductor substrate of a first conductivity type;
a semiconductor layer of the first conductivity type and forming a drift layer on said semiconductor substrate;
a first base layer of a second conductivity type, which is formed in the vicinity of a surface in a field effect transistor region of said semiconductor layer;
a source layer of the first conductivity type and formed on a surface of said first base layer;
a gate insulating film formed on said source layer;
a gate electrode formed on said gate insulating film;
a first metal film formed as source and anode electrodes on said field effect transistor region and a schottky-barrier diode region, respectively;
a second metal film formed as drain and cathode electrodes on the reverse of said semiconductor substrate; and
buried doped layers of the second conductivity type spaced at a predetermined interval and buried at a predetermined depth in said semiconductor layer in said schottky-barrier diode region.
5. A semiconductor device as set forth in claim 4, wherein said buried doped layers are dot-shaped.
6. A semiconductor device as set forth in claim 4, wherein said buried doped layers are stripe-shaped.
7. A semiconductor device as set forth in claim 4, wherein said gate insulating film is formed on an inner surface of a trench which is dug from the surface of said source layer to an upper layer of said semiconductor layer, and
said gate electrode being formed on said gate insulating film in the trench.
8. A semiconductor device as set forth in claim 4, further comprising:
a second base layer of the second conductivity type, which is formed as a guard ring in the surface portion of said semiconductor layer along a peripheral edge portion of said semiconductor layer; and
an insulating film formed so as to cover a junction of said semiconductor layer to said second base layer on the side of a peripheral edge portion of said semiconductor substrate.
9. A semiconductor device as set forth in claim 4, further comprising a barrier metal formed as a bedding metal film of said first metal film.
10. A semiconductor device comprising:
a semiconductor substrate of a first conductivity type;
a semiconductor layer of the first conductivity type, which is a drift layer formed on said semiconductor substrate;
a first base layer of a second conductivity type, which is formed in the vicinity of a surface in a field effect transistor region of said semiconductor layer;
a source layer of the first conductivity type, which is formed on a surface portion of said first base layer;
a plurality of trench gates each formed in a trench which is dug from the surface of said source layer to an upper layer portion of said semiconductor layer, said plurality of trench gates each comprising a gate insulating film formed on an inner surface of the trench and a gate electrode formed on said gate insulating film in the trench;
a first metal film formed as source and anode electrodes on said field effect transistor region and a schottky-barrier diode region, respectively;
a second metal film formed as drain and cathode electrodes on the reverse of said semiconductor substrate; and
buried doped layers of the second conductivity type, which are buried at a predetermined interval in said semiconductor layer in said schottky-barrier diode region at a predetermined depth and which are buried at the same interval as said gate electrode in said semiconductor layer in said field effect transistor region so as to have such a depth that said buried doped layers contact bottom faces of said trench gates.
11. A semiconductor device as set forth in claim 10, wherein said buried doped layers are dot-shaped.
12. A semiconductor device as set forth in claim 11, wherein said buried doped layers are connected to each other in the form of a lattice via connecting stripe-shaped buried doped layers of the second conductivity type.
13. A semiconductor device as set forth in claim 12, wherein said connecting stripe-shaped buried doped layers have a lower impurity concentration than that of said buried doped layers.
14. A semiconductor device as set forth in claim 11, wherein said buried doped layers are connected to each other in the form of a frame and stripes via connecting stripe-shaped buried doped layers of the second conductivity type.
15. A semiconductor device as set forth in claim 14, wherein said connecting stripe-shaped buried doped layers have a lower impurity concentration than that of said buried doped layers.
16. A semiconductor device as set forth in claim 10, wherein said buried doped layers are stripe-shaped.
17. A semiconductor device as set forth in claim 16, wherein said buried doped layers are connected to each other in the form of a lattice via connecting stripe-shaped buried doped layers of the second conductivity type.
18. A semiconductor device as set forth in claim 17, wherein said connecting stripe-shaped buried doped layers have a lower impurity concentration than that of said buried doped layers.
19. A semiconductor device as set forth in claim 16, wherein said buried doped layers are connected to each other in the form of a frame via connecting stripe-shaped buried doped layers of the second conductivity type.
20. A semiconductor device as set forth in claim 19, wherein said connecting stripe-shaped buried doped layers have a lower impurity concentration than that of said buried doped layers.
21. A semiconductor device as set forth in claim 10, wherein said buried doped layers are dot-shaped in said schottky-barrier diode region and stripe-shaped in said field effect transistor region.
22. A semiconductor device as set forth in claim 21, wherein said buried doped layers are connected to each other in the form of a lattice via connecting stripe-shaped buried doped layers of the second conductivity type.
23. A semiconductor device as set forth in claim 22, wherein said connecting stripe-shaped buried doped layers have a lower impurity concentration than that of said buried doped layers.
24. A semiconductor device as set forth in claim 21, wherein said buried doped layers are connected to each other in the form of a frame and stripes via connecting stripe-shaped buried doped layers of the second conductivity type.
25. A semiconductor device as set forth in claim 24, wherein said connecting stripe-shaped buried doped layers have a lower impurity concentration than that of said buried doped layers.
26. A semiconductor device as set forth in claim 10, wherein said buried doped layers are stripe-shaped in said schottky-barrier diode region and dot-shaped in said field effect transistor region.
27. A semiconductor device as set forth in claim 26, wherein said buried doped layers are connected to each other in the form of a lattice via connecting stripe-shaped buried doped layers of the second conductivity type.
28. A semiconductor device as set forth in claim 27, wherein said connecting stripe-shaped buried doped layers have a lower impurity concentration than that of said buried doped layers.
29. A semiconductor device as set forth in claim 26, wherein said buried doped layers are connected to each other in the form of a frame and stripes via connecting stripe-shaped buried doped layers of the second conductivity type.
30. A semiconductor device as set forth in claim 29, wherein said connecting stripe-shaped buried doped layers have a lower impurity concentration than that of said buried doped layers.
31. A semiconductor device as set forth in claim 10, further comprising:
a second base layer of the second conductivity type, which is formed as a guard ring in the surface portion of said semiconductor layer along a peripheral edge portion of said semiconductor layer; and
an insulating film formed so as to cover a junction portion of said semiconductor layer to said second base layer on the side of a peripheral edge portion of said semiconductor substrate.
32. A semiconductor device as set forth in claim 10, further comprising a barrier metal formed as a bedding metal film of said first metal film.

1. A communication card, comprising:
a card substrate;
a power interface adapted to receive power from a power source and distribute it to elements mounted on the card substrate;
a ground start detection circuit on the card substrate; and
an active current regulating circuit adapted to receive electrical power through the power interface, regulate a provided current responsive to the received electrical power and provide the regulated current to the ground start detection circuit.
2. A communication card according to claim 1, wherein the active current regulating circuit requires at least 10% of the size of the area of the substrate required by the ground start detection circuit.
3. A communication card according to claim 2, wherein the active current regulating circuit requires at least 20% of the size of the area of the substrate required by the ground start detection circuit.
4. A communication card according to claim 1, wherein the active current regulating circuit requires at least 1% of the area of the substrate utilized for electronic elements.
5. A communication card according to claim 1, wherein the active current regulating circuit comprises at least two transistors.
6. A communication card according to claim 1, wherein the active current regulating circuit provides a fixed current level with a variation error of less than 20%.
7. A communication card according to claim 1, wherein the active current regulating circuit provides a fixed current level with a variation error of less than 10%.
8. A communication card according to claim 1, wherein the elements of the card are adapted to operate with a voltage level of less than 25 volts.
9. A communication card according to claim 1, wherein the active current regulating circuit is adapted to receive electrical power with a voltage level of less than 20 volts.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A latch mechanism, comprising:
a rack, having a restricting structure; and
a linkage assembly, connected to an electronic device in the rack, wherein the linkage assembly includes:
a fixed frame, connected to the electronic device;
a sliding frame, movable along a first direction relative to the fixed frame;
a handle, connected to the sliding frame;
a trigger, movably disposed between the handle and the sliding frame; and
a latch member, connected to the fixed frame and the restricting structure to restrict the electronic device in the rack;
wherein when an external force is exerted on the trigger and the handle to move the sliding frame along the first direction relative the fixed frame, the trigger pushes the latch member to separate from the restricting structure along a second direction perpendicular to the first direction, such that the electronic device can be drawn out of the rack.
2. The latch mechanism as claimed in claim 1, wherein the linkage assembly further includes a locking member disposed on the sliding frame and engaged with the fixed frame to restrict the sliding frame moving relative to the fixed frame.
3. The latch mechanism as claimed in claim 2, wherein the trigger is movably connected to the sliding frame, and when the trigger moves along the first direction relative to the sliding frame, the trigger pushes the locking member to deform and separate from the fixed frame.
4. The latch mechanism as claimed in claim 3, wherein when the trigger moves along the first direction relative to the sliding frame, the trigger pushes the locking member to deform along a third direction, perpendicular to the first direction and the second direction.
5. The latch mechanism as claimed in claim 3, wherein the trigger includes a rod body, a first contact portion, and a second contact portion, wherein the rod body is extended along the first direction, and the first and second contact portions protrude from the rod body toward the second direction.
6. The latch mechanism as claimed in claim 5, wherein when the trigger moves along the first direction relative to the sliding frame, the first contact portion pushes the locking member to deform and separate from the fixed frame.
7. The latch mechanism as claimed in claim 5, wherein when the trigger moves along the first direction relative to the sliding frame and pushes the latch member, the second contact portion pushes the latch member to separate from the restricting structure along the second direction.
8. The latch mechanism as claimed in claim 1, wherein the latch member includes an inclined surface, and when the trigger pushes the latch member, the trigger pushes the inclined surface to separate the latch member from the restricting structure along the second direction.
9. The latch mechanism as claimed in claim 1, wherein the linkage assembly further includes a first spring connected to the sliding frame and the trigger.
10. The latch mechanism as claimed in claim 1, wherein the linkage assembly further includes a second spring connected to the fixed frame and the latch member.