1. A brake actuation unit for a brake-by-wire motor vehicle brake system for a motor vehicle comprising:
a brake-pedal actuatable master brake cylinder having at least one master brake cylinder pressure space to which hydraulically actuatable wheel brakes of the motor vehicle can be connected, a pressure medium reservoir vessel which is assigned to the master brake cylinder,
an electrically controllable pressure supply device which is formed by a hydraulic cylinder-piston arrangement having a piston actuated by an electric motor having a rotor and a stator, wherein the piston bounds a pressure space which is sealed with respect to the atmosphere by a first sealing element and which has a pressure medium connection for connecting to the wheel brakes, a first group of electrically actuatable valves for setting wheel-specific brake pressures,
a second group of electrically actuatable valves for disconnecting or connecting the wheel brakes from or to the master brake cylinder or from or to the pressure supply device,
an electronic control unit for activating the pressure supply device, the first group of valves, and the second group of valves, and
the hydraulic cylinder-piston arrangement configured such that after a predefined actuation displacement of the piston the pressure space is sealed by a second sealing element, in that the electric motor has at least a first and a second drive unit which can be operated independently of one another and each have at least one winding for driving the rotor of the electric motor, and in that the electronic control unit comprises a first microcontroller and a second microcontroller, wherein the first microcontroller is designed to activate the first drive unit of the electric motor, and the second microcontroller is designed to activate the second drive unit of the electric motor, and wherein the first and second the microcontrollers are designed to activate the second group of valves.
2. The brake actuation unit as claimed in claim 1, wherein the brake actuation unit further comprises a pedal travel simulator which gives a vehicle driver a pleasant brake pedal sensation in a brake-by-wire operating mode and which is embodied so as to be capable of being switched on and off by a simulator enabling valve, wherein the simulator enabling valve can also be activated by the first and the second microcontrollers.
3. The brake actuation unit as claimed in claim 1, wherein the pressure supply device further comprises a stepped bore arranged in the housing, and the piston is embodied as a stepped piston whose piston step with a smaller diameter fits into a smaller diameter portion of the stepped bore after the predefined actuation displacement of the stepped piston, with the result that the pressure space is divided into a first pressure space area at which the pressure medium connection is arranged, and a second pressure space area in the form of the an annular chamber.
4. The brake actuation unit as claimed in claim 3, further comprising in that in a state of the piston displaced beyond the predetermined actuation displacement the piston step the first pressure space area and the second pressure space area are sealed with respect to one another by the additional sealing element.
5. The brake actuation unit as claimed in claim 1 further comprising in that the first group of valves can be activated only by the first microcontroller, wherein the first group of valves comprises one inlet valve and one outlet valve for each of the wheel brakes.
6. The brake actuation unit as claimed in claim 5, further comprising in that only the valves of the first group, assigned to the rear wheel brakes, can be additionally activated by the second microcontroller.
7. The brake actuation unit as claimed in claim 1 wherein the brake actuation unit further comprises an electrically actuatable diagnostic valve which is arranged in a hydraulic connection between the master brake cylinder pressure space and the pressure medium reservoir vessel, wherein the diagnostic valve can be activated by at least the first microcontroller.
8. The brake actuation unit as claimed in claim 1 further comprising in that an electrically actuatable parking brake actuator on at least one of the wheel brakes which are arranged on the wheel brakes of the rear axle of the motor vehicle can be activated only by the second microcontroller.
9. The brake actuation unit as claimed in claim 1 further comprising in that the wheel brakes are arranged in first and second brake circuits, and in that the second group of valves which can be activated by the first and the second microcontrollers comprises at least one isolating valve for each of the brake circuits for disconnecting the master brake cylinder from the wheel brakes of the first and second brake circuits, and a sequence valve for each of the brake circuits for disconnecting the pressure supply device from the wheel brakes of the brake circuit.
10. The brake actuation unit as claimed in claim 1 further comprising in that the control unit is an open-loop and closed-loop control unit comprises a first and a second electrical connecting element, wherein the open-loop and closed-loop control unit can be supplied with electrical energy from at least a first electrical energy supply device via the first connecting element, and from at least a second electrical energy supply device via the second connecting element.
11. The brake actuation unit as claimed in claim 1 further comprising in that said brake actuation unit has a first pressure sensor, for detecting a pressure of the master brake cylinder, and a second pressure sensor, for detecting a pressure of the pressure supply device, wherein signals of the first pressure sensor are fed only to the first microcontroller, and signals of the second pressure sensor are fed only to the second microcontroller.
12. The brake actuation unit as claimed in claim 1 wherein the brake actuation unit further comprises a redundantly embodied travel sensor or two travel sensors for detecting a position of a brake pedal or of a master brake cylinder piston, wherein at least one signal of the travel sensor or the travel sensors is fed to the first and the second microcontrollers.
13. The brake actuation unit as claimed in claim 1 further comprising in that a first bus connection for a first databus and a second bus connection for a second databus are provided, wherein the first bus connection is connected only to the first microcontroller, and the second bus connection is connected only to the second microcontroller, and in that the first and the second microcontrollers are connected to one another via a third databus.
14. The brake actuation unit as claimed in claim 13, further comprising in that the first bus connection and the second bus connection are arranged on different electrical connecting elements.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A memory system comprising:
a memory access device;
a memory device coupled to the memory access device, the memory device comprising:
a memory cell array; and
a memory interface coupled to the memory cell array and configured for switchably operating in either an asynchronous mode or a synchronous mode,
wherein three or fewer additional memory interface control signals include a bidirectional data strobe signal and are utilized in the synchronous mode in addition to memory interface control signals utilized in the asynchronous mode, and
wherein the memory interface is configured to utilize a signal on a first contact of the memory interface as a write enable signal in an asynchronous mode and as a clock signal in a synchronous mode, and the memory interface is configured to utilize a signal on a second contact of the memory interface as a read enable signal in the asynchronous mode and as a writeread signal in the synchronous mode.
2. The memory system of claim 1, wherein the three or fewer additional memory interface signals at least includes two signals complementary to memory interface control signals utilized in the synchronous mode.
3. The memory system of claim 1, wherein the three or fewer additional memory interface control signals include a signal complementary to a memory interface control signal utilized in the synchronous mode.
4. The memory system of claim 1, wherein the three or fewer additional memory interface control signals include at least one of a complementary clock signal and a complementary bidirectional data strobe signal.
5. A memory system comprising:
a memory access device;
a memory device coupled to the memory access device, the memory device comprising:
a memory cell array; and
a memory interface coupled to the memory cell array and configured for switchably operating in either an asynchronous mode or a synchronous mode,
wherein the memory interface, utilized in the synchronous mode, includes three or fewer additional memory interface contacts in addition to memory interface contacts utilized in the asynchronous mode.
6. The memory system of claim 5, wherein the three or fewer additional memory interface contacts includes only one additional memory interface contact in addition to the memory interface contacts utilized in the asynchronous mode.
7. The memory system of claim 6, wherein the memory interface is configured to utilize a signal on the one additional memory interface contact as a bidirectional data strobe signal in the synchronous mode.
8. The memory system of claim 5, wherein the memory interface is configured to utilize a signal on the three or fewer additional memory interface contacts as a bidirectional data strobe signal, a complimentary bidirectional data strobe signal, andor a complimentary clock signal.
9. The memory system of claim 8, wherein the memory interface is configured to utilize a signal on a first memory interface contact as a write enable signal in the asynchronous mode and as a clock signal in the synchronous mode, and to utilize a signal on a second memory interface contact of the memory interface contacts as a read enable signal in the asynchronous mode and as a writeread signal in the synchronous mode.
10. A memory system comprising:
a memory access device;
a memory device coupled to the memory access device, the memory device comprising:
a memory cell array; and
a memory interface configured for:
switchably operating in either an asynchronous mode or a synchronous mode,
wherein the memory interface is configured to utilize a signal on a first memory interface contact of the memory interface contacts as a write enable signal in the asynchronous mode and as a clock signal in the synchronous mode, and to utilize a signal on a second memory interface contact of the memory interface contacts as a read enable signal in the asynchronous mode and as a writeread signal in the synchronous mode, and
wherein an additional memory interface contact for a bi-directional data strobe signal is utilized in the synchronous mode in addition to memory interface contacts utilized in the asynchronous mode.
11. The memory system of claim 10, wherein the memory interface is configured to power-up in the asynchronous mode, and switch to the synchronous mode responsive to detecting a clock signal.
12. The memory system of claim 10, wherein the memory interface is configured to power-up in the asynchronous mode, and switch to the synchronous mode responsive to detecting a free-running clock signal on one of the memory interface contacts utilized in the asynchronous mode.
13. The memory system of claim 10, wherein the memory interface is configured to switch operation of the memory interface to the synchronous mode responsive to receiving a SET Feature command while operating in the asynchronous mode.
14. The memory system of claim 10, wherein the memory interface is configured to switch operation of the memory interface to the asynchronous mode responsive to receiving a SET Feature command while operating in the synchronous mode.
15. The memory system of claim 10, wherein the asynchronous mode or the synchronous mode is selected using programmable elements of the memory device.
16. The memory system of claim 10, wherein the memory interface is configured to switch between the asynchronous mode and the synchronous mode using a Get Feature command.
17. The memory system of claim 10, wherein the additional memory interface contact for the bidirectional data strobe signal is the only additional memory interface contact that is utilized in the synchronous mode in addition to the memory interface contacts utilized in the asynchronous mode.
18. A memory system comprising:
a memory access device;
a memory device coupled to the memory access device, the memory device comprising:
a memory cell array; and
a memory interface configured for:
switchably operating in either a asynchronous mode or a synchronous mode; and
switching between the asynchronous mode and the synchronous mode using a Get Feature command,
wherein an additional memory interface contact for a bi-directional data strobe signal is utilized in the synchronous mode in addition to memory interface contacts utilized in the asynchronous mode.