Author: claimsbot

1. A method of producing a toothbrush from a blank, said blank comprising a handle portion, a neck portion and two diverging arm portions, each arm portion having a head portion with bristles, both head portions being located in a plane through a center line of said blank, and said bristles extending rectilinearly outwards from said center line, said method comprising the steps of:
placing said blank in a shaping device;
arranging a bottom side of said arm and head portions at a blank support body, wherein the support body has two mutually parallel pins have oppositely directed side faces having contact lines of the support body;
bending said arm and head portions via torsion twisting around said blank support body to a desired angle position along a respective one of two axes formed by contact lines of said blank support body, said two axes extending approximately parallel to said center line of said blank and approximately level with the bottom side of said neck portion;
wherein said step of bending causes said head portions to extend in downwards diverging directions with respect to said handle and neck portions, with a top side of said head portion extending downwards from a level of the center line of said blank and with the bottom side of said head portions extending downwards from a level of the bottom side of the neck portion.
2. The method according to claim 1, further comprising arranging a rigid support structure in a spacing between said two diverging arm and head portions, said rigid support structure having a shape approximately corresponding to a shape of said spacing.
3. The method according to claim 2, wherein said rigid support structure is wedge-shaped.
4. The method according to claim 1, wherein during said step of bending, the blank support body has two opposed side edges running parallel to said blank center line.
5. A device for producing a toothbrush having a handle portion, a neck portion, two arm portions and a bristle carrying head portion at the outer end of each arm portion, including twisting and deforming said two arm portions to form an angle of about 90\xb0 between the head portion of each arm portion, comprising:
a support body for supporting the toothbrush blank, said support body supporting at least said arm portions during a torsion twist bending of said arm portions along contact lines provided by said support body, wherein the support body forms two contact lines to support the arm portions to maintain their level during bending, and wherein the support body comprises two mutually parallel pins supporting the arm portions by means for mutually opposite side lines extending along the bottom side of the blank; and
means for softening relevant blank portions.
6. The device according to claim 5, further comprising a rigid structure located in a spacing between said two arm portions and said two head portions, said structure having a shape which approximately corresponds to said spacing.
7. The device according to claim 6, wherein the rigid structure is of a shape selected from the group consisting of V-shaped and wedge-shaped.
8. The device according to claim 5, wherein said support body has two edges extending parallel to the center line of the blank.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A tendon repair implant for repair of a partial thickness tear of a tendon, the tendon repair implant comprising:
a sheet-like structure configured to have an initial tensile modulus of about 1 MPa to 100 MPa in the range of 1% to 3% strain and comprising a plurality of pores for tissue in-growth, and wherein the sheet-like structure conforms to the surface of the tendon and is configured to have an initial load share representing between 1% to about 50% of the load of the tendon when affixed to the tendon.
2. The tendon repair implant of claim 1, wherein between 1% and 50% of the load of the tendon comprises between 0.5 N and 50 N.
3. The tendon repair implant of claim 1, wherein between 1% and 50% of the load of the tendon comprises between 0.5 N and 25 N.
4. The tendon repair implant of claim 1, wherein the initial tensile modulus is about 20 MPa to 50 MPa.
5. The tendon repair implant of claim 1, wherein the sheet-like structure is configured to degrade in tensile strength from an initial tensile strength thereby sharing less of the load of the tendon over time but retain at least about 50% of the initial load share of the sheet-like implant three months after being affixed to the tendon.
6. The tendon repair implant of claim 5, wherein to retain at least about 50% of the initial load share of the sheet-like implant at three months, the sheet-like structure is configured to retain at least about 70% of the initial tensile strength three months after being affixed to the tendon and to retain at least about 50% of the initial tensile strength and about 50% of an initial compressive modulus three months after being affixed to the tendon.
7. The tendon repair implant of claim 1, wherein the sheet-like structure comprises a bioresorbable material.
8. The tendon repair implant of claim 1, wherein the sheet-like structure comprises a polymer material.
9. The tendon repair implant of claim 1, wherein the sheet-like structure is further configured to be attached to the surface of the tendon without significant pre-loading or significant pre-stretching.
10. The tendon repair implant of claim 1, wherein the sheet-like structure has one or more agents affixed thereto which promote tissue in-growth.
11. The tendon repair implant of claim 1, wherein the pores have sizes between about 20 microns and 400 microns.
12. The tendon repair implant of claim 1, wherein the sheet-like structure is defined by a longitudinal dimension, a lateral dimension, and a thickness dimension, wherein the longitudinal dimension is greater than the lateral dimension and the thickness dimension, and wherein the sheet-like structure further comprises one or more longitudinal pathways extending along the longitudinal dimension of the sheet-like structure.
13. The tendon repair implant of claim 1, wherein the sheet-like structure has a maximum of about 0.5% creep over three months.
14. A tendon repair implant for repair of a partial thickness tear of a supraspinatus tendon having a load bearing direction, the tendon repair implant comprising:
a sheet-like structure having a longitudinal dimension, a lateral dimension, and a thickness dimension and configured to be affixed to a surface of the supraspinatus tendon such that the longitudinal dimension of the sheet-like structure extends generally parallel to the load bearing direction of the supraspinatus tendon, wherein when affixed to the surface of the supraspinatus tendon, the sheet-like structure is configured to initially share between 1% and 50% of a load applied to the supraspinatus tendon;
the sheet-like structure comprising a plurality of longitudinal pathways that encourage tissue in-growth therein, wherein the longitudinal pathways extend along the longitudinal dimension of the sheet-like structure and have cross sections of about 150 microns to 200 microns; and
the sheet-like structure having a compressive modulus greater than the supraspinatus tendon to allow for cyclic straining of the sheet-like implant and any tissue in-growth.
15. The tendon repair implant of claim 14, wherein the longitudinal pathways comprise lumens.
16. The tendon repair implant of claim 14, wherein the longitudinal pathways are maintained when the sheet-like implant is subjected to longitudinal loads.
17. The tendon repair implant of claim 14, wherein the sheet-like implant further comprises a plurality of pores, wherein the pores range in size from about 20 to 400 microns.
18. The tendon repair implant of claim 14, wherein the sheet-like structure has a porosity of at least about 50% to about 80%.
19. A tendon repair implant for repair of a partial thickness tear of a tendon, the tendon repair implant comprising:
a sheet-like structure configured to have an initial tensile modulus of about 1 MPa to 100 MPa in the range of 1% to 3% strain and comprises a plurality of pores for tissue in-growth, wherein the sheet-like structure is flexible such that when the sheet-like structure is affixed to a surface of the tendon the sheet-like structure conforms to the surface of the tendon;
the sheet-like structure being configured to initially have an initial load share representing between 1% and 50% of a load applied to the tendon; and
the sheet-like structure being configured to degrade in tensile strength from an initial tensile strength thereby sharing less of the load of the tendon over time but retain at least 50% of the initial load share of the sheet-like implant three months after being affixed to the tendon.
20. The tendon repair implant of claim 19, wherein the sheet-like implant is configured to initially share between 5% and 33% of the load of the tendon.
21. The tendon repair implant of claim 19, wherein, between 1% and 50% of the load of the tendon comprises between 0.5 N and 50 N.
22. The tendon repair implant of claim 19, wherein, between 1% and 50% of the load of the tendon comprises between 0.5 N and 25 N.
23. The tendon repair implant of claim 19, wherein the initial tensile modulus is 20 MPa to 50 MPa.
24. The tendon repair implant of claim 19, wherein to retain at least 50% of the initial load share of the sheet-like implant at three months, the sheet-like structure is configured to retain at least 70% of the initial tensile strength three months after being affixed to the tendon and to retain at least 50% of the initial tensile strength and at least 50% of an initial compressive modulus three months after being affixed to the tendon.
25. The tendon repair implant of claim 19, wherein the sheet-like structure comprises a bioresorbable material.
26. The tendon repair implant of claim 19, wherein the sheet-like structure comprises a polymer material.
27. The tendon repair implant of claim 19, wherein the sheet-like structure is further configured to be attached to the surface of the tendon without significant pre-loading or significant pre-stretching.
28. The tendon repair implant of claim 19, wherein the sheet-like structure has one or more agents affixed thereto which encourage tissue in-growth.
29. The tendon repair implant of claim 19, wherein the pores have sizes between 20 microns and 400 microns.
30. The tendon repair implant of claim 19, wherein the sheet-like structure is defined by a longitudinal dimension, a lateral dimension, and a thickness dimension, wherein the longitudinal dimension is greater than the lateral dimension and the thickness dimension, and wherein the sheet-like structure further comprises one or more longitudinal pathways extending along the longitudinal dimension of the sheet-like structure.

1. A semiconductor device, comprising:
a clock input unit configured to receive a system clock and a data clock externally;
a phase dividing unit configured to generate a plurality of multi-system clocks in response to the system clock, wherein each of the multi-system clocks has an individual phase difference;
a phase detecting unit configured to detect phase differences between one of the plurality of multi-system clocks and the data clock to generate a training information signal in response to the detection result; and
a signal transmitting unit configured to transmit the training information signal,
wherein the phase detecting unit includes:
a plurality of phase comparing units configured to compare phases between each of the plurality of multi-system clocks and the data clock, respectively, to output a plurality of comparison signals; and
a logic level changing unit configured change a logic level of the training information signal in response to the plurality of comparison signals,
wherein the data clock and the plurality of multi-system clocks have the same frequency.
2. The semiconductor device of claim 1, wherein the phase dividing unit is configured to generate the plurality of multi-system clocks with a phase difference of 45\xb0 from each other, a phase difference of 90\xb0 from each other, or a phase difference of 180\xb0 from each other in response to the system clock.
3. The semiconductor device of claim 1, wherein each of the phase comparing units is configured to determine whether the comparison signals are activated or not according to an activation state of the data clock at times when a logic level of any one clock among the plurality of multi-system clocks is being changed.
4. The semiconductor device of claim 1, wherein the logic level changing unit is configured to activate the training information signal to output the activated training information signal when all the plurality of comparison signals outputted from the plurality of phase comparing units are activated.
5. The semiconductor device of claim 1, wherein the logic level changing unit is configured to inactivate the training information signal to output the inactivated training information signal when all the plurality of comparison signals outputted from the plurality phase comparison units are inactivated.
6. The semiconductor device of claim 1, wherein the logic level changing unit is configured to inactivate the training information signal to output the inactivated training information signal when the number of the comparison signals of inactivated states is greater than the number of the comparison signals of activated states among the comparison signals outputted from the plurality of the phase comparing units.
7. The semiconductor device of claim 1, wherein the logic level changing unit is configured to activate the training information signal to output the activated training information signal when the number of the comparison signals of activated states is greater than the number of the comparison signals of inactivated states among the comparison signals outputted from the plurality of the phase comparing units.
8. A semiconductor device, comprising:
a clock input unit configured to receive a system clock and a data clock externally;
a phase dividing unit configured to generate a plurality of multi-system clocks each having an individual phase difference based on the system clock;
a clock dividing unit configured to generate a data dividing clock with the same frequency as the plurality of multi-system clocks by dividing a frequency of the data clock;
a phase detecting unit configured to detect phase differences between the plurality of multi-system clocks and the data dividing clock to generate a training information signal in response to the detection result; and
a signal transmitting unit configured to transmit the training information signal,
wherein the phase detecting unit includes:
a plurality of phase comparing units configured to compare phases between each of the plurality of multi-system clocks and the data dividing clock, respectively, to output a plurality of comparison signals; and
a logic level changing unit configured to change a logic level of the training information signal in response to the plurality of comparison signals.
9. The semiconductor device of claim 8, wherein the phase dividing unit is configured to generate the plurality of multi-system clocks with a phase difference of 45\xb0 from each other, a phase difference 90\xb0 from each other, or a phase difference 180\xb0 from each other in response to the system clock.
10. The semiconductor device of claim 8, wherein each of the phase comparing units determines whether the comparison signals are activated or not according to an activation state of the data dividing clock at times when a logic level of any one clock among the plurality of multi-system clocks is being changed.
11. The semiconductor device of claim 8, wherein the logic level changing unit is configured to activate the training information signal to output the activated training information signal when all the plurality of comparison signals outputted from the plurality of phase comparing units are activated.
12. The semiconductor device of claim 8, wherein the logic level changing unit is configured to inactivate the training information signal to output the inactivated training information signal when all the plurality of comparison signals outputted from the plurality phase comparison units are inactivated.
13. The semiconductor device of claim 8, wherein the logic level changing unit is configured to inactivate the training information signal to output the inactivated training information signal when the number of the comparison signals of inactivated states is greater than the number of the comparison signals of activated states among the comparison signals outputted from the plurality of the phase comparing units.
14. The semiconductor device of claim 8, wherein the logic level changing unit is configured to activate the training information signal to output the activated training information signal when the number of the comparison signals of activated states is greater than the number of the comparison signals of inactivated states among the comparison signals outputted from the plurality of the phase comparing units.
15. A semiconductor device, comprising:
a clock input unit configured to receive a system clock and a data clock from outside;
a first clock dividing unit configured to divide a frequency of the system clock by a first ratio to output a system dividing clock;
a phase dividing unit configured to generate a plurality of multi-system dividing clocks having a phase difference of a dedicated size respectively in response to the system dividing clock;
a second clock dividing unit configured to divide a frequency of the data clock by a second ratio to generate a data dividing clock;
a phase detecting unit configured to detect phase differences between the plurality of multi-system dividing clocks and the data dividing clock respectively to generate a training information signal in response to the detection result; and
a signal transmitting unit configured to transmit the training information signal,
wherein the phase detecting unit includes:
a plurality of phase comparing units configured to compare phases between the plurality of multi-system dividing clocks and the data dividing clock, respectively, to output a plurality of comparison signals; and
a logic level changing unit configured to change a logic level of the training information signal in response to the comparison signals output from the phase comparing units,
wherein the data dividing clock and the plurality of multi-system dividing clocks have the same frequency.
16. The semiconductor device of claim 15, wherein the phase dividing unit is configured to generate the plurality of multi-system dividing clocks with a phase difference of 45\xb0 from each other, a phase difference 90\xb0 from each other or a phase difference 180\xb0 from each other in response to the system dividing clock.
17. The semiconductor device of claim 15, wherein each of the phase comparing units is configured to determine whether the comparison signals are activated or not according to activation state of the data dividing clock at a time when a logic level of any one clock among the plurality of multi-system dividing clocks is changed.
18. The semiconductor device of claim 15, wherein the logic level changing unit is configured to activate the training information signal to output the activated training information signal when all the plurality of comparison signals outputted from the plurality of phase comparing units are activated.
19. The semiconductor device of claim 15, wherein the logic level changing unit is configured to inactivate the training information signal to output the inactivated training information signal when all the plurality of comparison signals outputted from the plurality phase comparison units are inactivated.
20. The semiconductor device of claim 15, wherein the logic level changing unit is configured to inactivate the training information signal to output the inactivated training information signal when the number of the comparison signals of inactivated states is greater than the number of the comparison signals of activated states among the comparison signals outputted from the plurality of the phase comparing units.
21. The semiconductor device of claim 15, wherein the logic level changing unit is configured to activate the training information signal to output the activated training information signal when the number of the comparison signals of activated states is greater than the number of the comparison signals of inactivated states among the comparison signals outputted from the plurality of the phase comparing units.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A transistor device laid out in a CMOS process, shaped as a rectangle having four edges, comprising:
a first drainsource layer that is employable as a source or a drain connection layer;
a top drainsource layer that is employable as a source or a drain connection layer, wherein said top drainsource layer is above said first drainsource layer, and wherein both of said first drainsource layer and said top drainsource layer covers each of said four edges of said device rectangle, such that both of said drain and said source are accessible from each of said four edges of said device rectangle;
two or more via stripes extending over an entire length in an X direction and evenly distributed over an entire length in a Y direction connecting said first drainsource layer and said top drainsource layer;
a gate layer that is employable as a gate connection layer; and
a bulk layer that is employable as a bulk connection layer, wherein the bulk is independently accessible from the drain, the gate, and the source.
2. The transistor device of claim 1, wherein said first drainsource layer and said top drainsource layer are both metal layers.
3. The transistor device of claim 1, wherein said gate layer is connected to a plurality of polysilicon gates in said X direction underlying said gate layer wherein said polysilicon gates are transistor fingers wherein said transistor fingers extend over an entire length of said rectangle in said Y direction.
4. The transistor device of claim 3 wherein said via stripes are evenly distributed over a length of said transistor fingers in said Y direction.
5. The transistor device of claim 1, wherein said first drainsource layer, said top drainsource layer, said gate layer, and said bulk layer are all metal layers.
6. The transistor device of claim 5, wherein
said bulk layer is a Metal 1 layer that is below said gate layer, said first drainsource layer, and said top drainsource layer;
said gate layer is a Metal 2 layer that is below said first drainsource layer and said top drainsource layer; and
wherein said first drainsource layer is a Metal 3 layer that is below said top drainsource layer.
7. The transistor device of claim 1, wherein
said transistor device is a transistor array including a plurality of transistors;
said first drainsource layer is connected to said drain or said source of each transistor of a plurality of transistors;
said top drainsource layer is connected to said drain or said source of each of said plurality of transistors;
each transistor in said plurality of transistors is shaped as a rectangle having four edges;
each of said transistors in said plurality is structured such that any two transistors having any two edges abutting each other automatically have their gates, drains, sources, edges, and bulks coupled together; and
wherein, for each of said transistors in said plurality, at least one edge of said transistor is abutted to at least one of said edges of at least one of another of said transistors in said plurality of transistors.