Author: claimsbot

1. A housing for use as a vehicle driveline component, comprising:
a sidewall establishing an open end of the housing, the sidewall having a plurality of spaced splines and a strengthening member near the open end that is formed of the sidewall material having a folded over portion that is at least partially aligned with and adjacent the sidewall, an inner surface of the sidewall near the open end extending continuously and uninterrupted once the strengthening member and establishing at least one surface of the strengthening member.
2. The housing of claim 1, including a plurality of the strengthening members.
3. The housing of claim 2, wherein at least some of the plurality of the strengthening members are aligned with the splines.
4. The housing of claim 2, wherein the plurality of strengthening members are spaced about a periphery of the open end.
5. The housing of claim 2, wherein the splines have an exposed surface at a first radial distance from a center of the housing and spaces between the splines have an exposed surface at a second radial distance from the center of the housing and wherein the folded over portion of each of the strengthening members is received at least partially against the exposed surface of the spaces.
6. The housing of claim 5, wherein an exposed surface of the strengthening members is at a radial distance from the center of the housing that is one of the first radial distance or the second radial distance.
7. The housing of claim 5, wherein the folded over portion of each of the strengthening members is nested between the splines.
8. The housing of claim 1, wherein the folded over portion of the strengthening member is adjacent an outer surface of the sidewall.
9. A housing for use as a vehicle driveline component, comprising:
a sidewall establishing an open end of the housing, the sidewall having a first plurality of spaced splines projecting toward an interior of the housing and a second plurality of spaced splines projecting toward an exterior of the housing and a plurality of strengthening members near the open end that are extensions of at least some of one of the pluralities of splines, each strengthening member having a folded over portion that is at least partially aligned with and adjacent the sidewall and at least partially nested between corresponding adjacent ones of the other of the pluralities of splines.
10. The housing of claim 9, wherein an inner surface of the sidewall near the open end extends continuously and uninterrupted onto the strengthening member and establishes at least one surface of the strengthening member.
11. The housing of claim 9, wherein the strengthening members are extensions of the sidewall material forming the first plurality of splines and the folded over portions are at least partially nested between corresponding ones of the second plurality of splines.
12. The housing of claim 9, wherein the strengthening members are spaced about a periphery of the open end.
13. A housing for use as a vehicle driveline component, comprising:
a side wall establishing an open end of the housing, the side wall having a plurality of spaced splines that have an exposed surface at a first radial distance from a center of the housing and spaces between the splines that have an exposed surface at a second radial distance from the center of the housing, and a plurality of strengthening members near the open end that are formed of the side wall material having a folded over portion that is received at least partially against the exposed surface of the spaces and is nested between the splines, and an inner surface of the side wall near the open end extending continuously and uninterrupted onto the strengthening members and establishing at least one surface of the strengthening members.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

I claim:

1. An assembly of shelving units that are interconnected without fasteners to form a free standing piece of furniture, comprising,
a base shelf having a planar upper surface, first and second ends and front and rear edges,
at least one additional shelf having a planar upper surface, first and second ends and front and rear edges,
a first plurality of spaced apart elongated mutually parallel slots disposed transversely in the rear edge of each of said shelves intermediate the first and second ends thereof, each having parallel sides and a lengthwise axis,
at least one brace-receiving slot having parallel sides and disposed in the rear edge of the base shelf, where the sides of the brace-receiving slots are not perpendicular to the planar surface of the base shelf,
a first plurality of support members having parallel planar surfaces and each having front and rear edges,
a plurality of elongated mutually parallel slots disposed in the front edge of each of said support members, whereby the slots in the support members are sized and adapted for interlocking engagement with corresponding slots in the shelves,
at least one brace-receiving slot in the rear edge of each of said support members, said slot having sides that are not perpendicular to the planar surfaces of the support members, and
at least one brace member having ends that are respectively adapted to be disposed in the brace-receiving slot of the base shelf and the support member.
2. The assembly of claim 1 where the lengthwise axes of the slots disposed transversely in the rear edge of each of said shelves are perpendicular to the rear edge thereof.
3. The assembly of claim 1 where at least one of the support members includes at least one pair of spaced apart, parallel, and elongated surface recesses that are substantially aligned with one of said slots in the support member.
4. The assembly of claim 3 where the contour of the sides of the shelf slot that is adapted to interconnect with the slot in the support member that is aligned with the said pair of surface recesses is shaped to match the contour of the recess.
5. The assembly of claim 4, where the contour of each of the recesses is curved.
6. The assembly of claim 1 where the brace member extends through the brace-receiving slot in the support member to engage the at least one additional shelf.
7. An improved interlocking slot-to-slot connection between two planar objects, comprising,
a first planar object having front and rear edges and having an elongated transverse first slot extending from the rear edge thereof, said first slot having parallel sides, at least one of which is contoured,
a second object having at least two opposing planar surfaces and front and rear edges and having a transverse second slot extending from the front edge thereof with parallel sides and a terminal end, said second object also having a contoured recess in at least one of said surfaces that extends from the terminal end of the second slot toward the rear edge of the second object, where the contour of the recess corresponds to the contour of the side of the first slot.
8. A shelving assembly, comprising,
at least one horizontally disposed shelf member having front and rear edges and having an elongated transverse shelf slot extending from the rear edge thereof, said first slot having parallel sides, at least one of which is contoured,
a vertically disposed support member having at least two opposing planar surfaces and front and rear edges and having a transverse support slot extending from the front edge thereof with parallel sides and a terminal end, said support member also having a contoured recess in at least one of said surfaces that extends from the terminal end of the second slot toward the rear edge of the support member, where the contour of the recess corresponds to the contour of the side of the first slot.

1. An integrated circuit comprising:
A. a data source having a data output bus;
B. a data destination having a data input bus; and
C. a serial inputoutput circuit having a serial data input and a serial data output, the serial inputoutput circuit including:
i. a multiplexer having a first input connected to the data output bus, a second input connected to the serial data input, a third input, an output, and a control input, and
ii. a flop-flop having an input connected to the output of the multiplexer, a clock input, and having an output connected to the data input bus, connected to the third input of the multiplexer, and coupled to the serial data output.
2. The integrated circuit of claim 1 in which the control input of the multiplexer is a load lead that is also connected to the data source.
3. The integrated circuit of claim 1 in which the flop-flop is a D-type flip-flop.
4. The integrated circuit of claim 1 in which the serial data input and the serial data output are coupled to a test clock lead, and the integrated circuit includes a test mode select lead, a test data in lead, and test data out lead.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1-47. (canceled)
48. A plasma display panel (PDP), comprising:
a first substrate;
a first electrode and a second electrode arranged respectively in parallel on the first substrate;
a second substrate;
an address electrode arranged on the second substrate; and
a driving circuit that sends a driving signal to the first electrode, the second electrode and the address electrode during a reset period, an address period and a sustain period,
wherein, during the reset period, the driving circuit,
applies a first voltage level to the first electrode, while maintaining the second electrode at a second voltage level;
applies a first voltage waveform to the second electrode, the first voltage waveform increasing with a first slope to a third voltage level, while maintaining the first electrode at a fourth voltage level; and
applies a second voltage waveform to the second electrode, the second voltage waveform decreasing with a second slope to a fifth voltage level, while applying a sixth voltage level to the first electrode,
wherein the fifth voltage level is a negative voltage.
49. The PDP of claim 48, the first voltage level is maintained for a predetermined time.
50. The PDP of claim 48, wherein the first voltage level is a positive voltage and the second voltage level is a negative voltage.
51. The PDP of claim 48, wherein the address electrode is maintained at a seventh voltage level, while the first voltage level is applied to the first electrode, and the first voltage waveform and the second voltage waveform are applied to the second electrode.
52. The PDP of claim 51, wherein the seventh voltage level is a ground level.
53. The PDP of claim 48, wherein the first slope is time-invariant.
54. The PDP of claim 48, wherein the second slope is time-variant.
55. The PDP of claim 48, wherein the second voltage waveform decreases from a seventh voltage level to the fifth voltage level.
56. The PDP of claim 55, wherein the seventh voltage level is less than the third voltage level.
57. The PDP of claim 48, wherein the fifth voltage level is less than the third voltage level.
58. The PDP of claim 48, wherein the first voltage level and the sixth voltage level are different from each other.
59. The PDP of claim 48, wherein the fourth voltage level is a negative voltage level.
60. The PDP of claim 48, wherein, during the sustain period, the driving circuit further
applies a seventh voltage level to the first electrode and applies an eighth voltage level to the second electrode simultaneously in a first subperiod; and
applies the eighth voltage level to the first electrode and applies the seventh voltage level to the second electrode simultaneously in a second subperiod,
wherein the seventh voltage level and the eighth voltage level have opposite polarities.
61. The PDP of claim 60, wherein the seventh voltage level and the eighth voltage level have a same magnitude.
62. The PDP of claim 60, wherein the first subperiod and the second subperiod are alternately repeated in the sustain period.
63. The PDP of claim 60, the fifth voltage level and the seventh voltage level are different from each other.
64. The PDP of claim 60, wherein the fourth voltage level and the seventh voltage level are different from each other.
65. The PDP of claim 60, wherein the driving circuit applies the seventh voltage level to the first electrode in a period between a last sustain discharge in a previous subfield and application of the first voltage level in a following subfield.
66. The PDP of claim 48, wherein, during the sustain period, the driving circuit further
applies a seventh voltage level to the first electrode and applies an eighth voltage level to the second electrode simultaneously in a first subperiod; and
applies the eighth voltage level to the first electrode and applies the seventh voltage level to the second electrode simultaneously in a second subperiod,
wherein the seventh voltage level is a ground level.
67. A plasma display panel (PDP), comprising:
a first substrate;
a first electrode and a second electrode arranged respectively in parallel on the first substrate;
a second substrate;
an address electrode arranged on the second substrate; and
a driving circuit that sends a driving signal to the first electrode, the second electrode and the address electrode during a reset period, an address period and a sustain period,
wherein, during the reset period, the driving circuit,
applies a first voltage waveform to the second electrode, the first voltage waveform decreasing from a first voltage level to a second voltage level, while maintaining the first electrode at a third voltage level;
applies a second voltage waveform to the second electrode, the second voltage waveform increasing to a fourth voltage level, while maintaining the first electrode at a fifth voltage level; and
applies a third voltage waveform to the second electrode, the third voltage waveform decreasing to a sixth voltage level, while applying a seventh voltage level to the first electrode,
wherein the sixth voltage level is a negative voltage.
68. The PDP of claim 67, wherein the first voltage level and the second voltage level have opposite polarities.
69. The PDP of claim 67, wherein the first voltage waveform comprises a ramp voltage waveform.
70. The PDP of claim 67, wherein the third voltage level is a positive voltage.
71. The PDP of claim 67, wherein the second voltage waveform comprises a ramp voltage waveform.
72. The PDP of claim 67, wherein the third voltage waveform comprises a ramp voltage waveform.
73. The PDP of claim 67, wherein the third voltage waveform decreases with a first slope from the fourth voltage level to an eighth voltage level before decreasing with a second slope from the eighth voltage level to the sixth voltage level.
74. The PDP of claim 73, wherein the eighth voltage level is a positive voltage.
75. The PDP of claim 73, wherein a magnitude of the second slope is less than a magnitude of the first slope.
76. The PDP of claim 73, wherein the second slope comprises at least one of ramp waveform.
77. The PDP of claim 67, wherein the first voltage level and the third voltage level are equal to each other.
78. The PDP of claim 73, wherein the second voltage waveform increases from the eighth voltage level to the fourth voltage level.
79. The PDP of claim 67, wherein the address electrode is maintained at an eighth voltage level, while the first voltage waveform and the third voltage waveform are applied to the second electrode.
80. The PDP of claim 79, wherein the eighth voltage level is a ground level.
81. The PDP of claim 67, wherein, during the sustain period, the driving circuit further
applies an eighth voltage level to the first electrode and applies a ninth voltage level to the second electrode simultaneously in a first subperiod; and
applies the ninth voltage level to the first electrode and applies the eighth voltage level to the second electrode simultaneously in a second subperiod,
wherein the eighth voltage level and the ninth voltage level have opposite polarities.
82. The PDP of claim 81, wherein the eighth voltage level and the ninth voltage level have a same magnitude.
83. The PDP of claim 82, wherein the first voltage level and the ninth voltage level are equal to each other.
84. The PDP of claim 81, wherein the sixth voltage level and the eighth voltage level are different from each other.
85. The PDP of claim 81, wherein the fifth voltage level and the eighth voltage level are different from each other.
86. The PDP of claim 67, wherein the fourth voltage level is higher than the sixth voltage level.
87. The PDP of claim 67, wherein the second voltage level and the sixth voltage level are equal to each other.
88. The PDP of claim 67, wherein, during the sustain period, the driving circuit further
applies an eighth voltage level to the first electrode and applies a ninth voltage level to the second electrode simultaneously in a first subperiod; and
applies the ninth voltage level to the first electrode and applies the eighth voltage level to the second electrode simultaneously in a second subperiod,
wherein the eighth voltage level is a ground level.
89. A plasma display panel (PDP), comprising:
a first substrate;
a first electrode and a second electrode arranged respectively in parallel on the first substrate;
a second substrate;
an address electrode arranged on the second substrate; and
a driving circuit that sends a driving signal to the first electrode, the second electrode and the address electrode during a reset period, an address period and a sustain period,
wherein, during the reset period, the driving circuit,
applies a first voltage waveform to the second electrode, the first voltage waveform decreasing from a first voltage level to a second voltage level, while maintaining the first electrode at substantially the first voltage level;
applies a second voltage waveform to the second electrode, the second voltage waveform increasing to a third voltage level, while maintaining the first electrode at a fourth voltage level; and
applies a third voltage waveform to the second electrode, the third voltage waveform decreasing to a fifth voltage level, while applying a sixth voltage level to the first electrode,
wherein the first voltage level is a positive voltage and the fifth voltage level is a negative voltage.
90. The PDP of claim 89, wherein the second voltage level is a negative voltage.
91. The PDP of claim 89, wherein the second voltage level is substantially the same as the fifth voltage level.
92. The PDP of claim 89, wherein the first voltage waveform comprises at least one ramp voltage waveform.
93. The PDP of claim 89, wherein the second voltage waveform comprises a ramp voltage waveform increasing from a seventh voltage level to the third voltage level, the seventh voltage level being a positive voltage.
94. The PDP of claim 89, wherein the third voltage waveform comprises at least one ramp voltage waveform.
95. The PDP of claim 93, wherein the third voltage waveform comprises a first period decreasing from the third voltage level to an eighth voltage level with a first slope and a second period decreasing from the eighth voltage level to the fifth voltage level with a second slope.
96. The PDP of claim 95, wherein the eighth voltage level is a positive voltage.
97. The PDP of claim 95, wherein the second period comprises a ramp waveform.
98. The PDP of claim 95, wherein the seventh voltage level is substantially the same as the eighth voltage level.