Author: claimsbot

1. A memory apparatus comprising:
a nonvolatile memory configured to have data written thereto and read therefrom in units of clusters and to have data deleted therefrom in units of blocks each formed by a plurality of sectors; and
a control circuit configured to control said nonvolatile memory in operation;
wherein said nonvolatile memory includes
a management area in which to record management information,
a user data area in which to record data coming from a user, and a cache area in which to hold temporarily the data to be written to and read from said user data area,
said management area includes
a logical to physical conversion table retaining relations of correspondence between addresses of logical blocks in said user data area on the one hand, and addresses of physical blocks assigned to said logical blocks on the other hand, and
addresses of physical blocks in said cache area, the physical block addresses corresponding to the physical block addresses in said logical to physical conversion table, and
said control circuit includes
first writing means for writing, to a deleted new cache block in said cache area, data in excess of a designated logical boundary which defines a logical space size in units of a plurality of sectors within a user data block of said user data area, and
second writing means for having the data written starting from the beginning of said new cache block upon data write by said first writing means to said new cache block, regardless of the logical address space of said new cache block.
2. The memory apparatus according to claim 1, further comprising third writing means as part of said control circuit, wherein, in case of a continuous data write subsequent to the data write performed by said first writing means to said new cache block, said control circuit causes said third writing means to write the additional data immediately in excess of written sectors within said cache block.
3. The memory apparatus according to claim 2, further comprising fourth writing means as part of said control circuit, wherein, following the data write by said first writing means to said new cache block, if it is found impossible to write data immediately in excess of said written sectors within said new cache block, then said control circuit causes said fourth writing means to copy the data from said user data block up to a write starting sector address, before writing the additional data to said cache block.
4. The memory apparatus according to claim 3, further comprising fifth writing means as part of said control circuit, wherein, if said new cache block is found fully written upon data write by said fourth writing means, then said control circuit causes said fifth writing means to write the data from said new cache block back to said user data block without starting garbage collection as a copy operation preparatory to executing the write-back.
5. A memory apparatus comprising:
a nonvolatile memory configured to have data written thereto and read therefrom in units of clusters and to have data deleted therefrom in units of blocks each formed by a plurality of sectors; and
a control circuit configured to control said nonvolatile memory in operation;
wherein said nonvolatile memory includes
a management area in which to record management information,
a user data area in which to record data coming from a user, and
a cache area in which to hold temporarily the data to be written to and read from said user data area,
said management area includes
a logical to physical conversion table retaining relations of correspondence between addresses of logical blocks in said user data area on the one hand, and addresses of physical blocks assigned to said logical blocks on the other hand, and
addresses of physical blocks in said cache area, the physical block addresses corresponding to the physical block addresses in said logical to physical conversion table, and
said control circuit includes
sixth writing means for writing, to a deleted new cache block in said cache area, data short of a designated logical boundary which defines a logical space size in units of a plurality of sectors within a user data block of said user data area, and
seventh writing means for having data written starting from the beginning of said new cache block upon data write by said sixth writing means to said new cache block, regardless of the logical address space of said new cache block.
6. The memory apparatus according to claim 5, further comprising eighth writing means as part of said control circuit, wherein, in case of a data write to the same logical address space within said new cache block following the data write by said sixth writing means to said new cache block, said control circuit causes said eighth writing means to write the additional data immediately in excess of written sectors within said cache block.
7. The memory apparatus according to claim 6, further comprising ninth writing means as part of said control circuit, wherein, following the data write by said eighth writing means to said new cache block, if the written data is found short of said designated logical boundary, then said control circuit causes said ninth writing means to copy the data from said user data block up to the sector address of said designated logical boundary.
8. The memory apparatus according to claim 7, further comprising tenth writing means as part of said control circuit, wherein, if said new cache block is found fully written upon data write by said ninth writing means, then said control circuit causes said tenth writing means to write the data to another cache block.
9. The memory apparatus according to claim 8, further comprising eleventh writing means as part of said control circuit, wherein, in case of a data write in excess of said designated logical border following the data write by said tenth writing means to said new cache block, said control circuit causes said eleventh writing means to write the data to another cache block.
10. A memory apparatus comprising:
a nonvolatile memory configured to have data written thereto and read therefrom in units of clusters and to have data deleted therefrom in units of blocks each formed by a plurality of sectors; and
a control circuit configured to control said nonvolatile memory in operation;
wherein said nonvolatile memory includes
a management area in which to record management information,
a user data area in which to record data coming from a user, and
a cache area in which to hold temporarily the data to be written to and read from said user data area,
said management area includes
a logical to physical conversion table retaining relations of correspondence between addresses of logical blocks in said user data area on the one hand, and addresses of physical blocks assigned to said logical blocks on the other hand, and
addresses of physical blocks in said cache area, the physical block addresses corresponding to the physical block addresses in said logical to physical conversion table, and
said control circuit includes
twelfth writing means for, if all cache blocks in said cache area are found fully written upon data write to user data blocks in said user data area, then writing the data from said cache blocks back to said user data blocks without starting garbage collection as a copy operation preparatory to executing the write-back, and
first preferential processing means for causing said twelfth writing means to execute said write-back to said cache blocks preferentially in ascending order of data update frequency of said cache blocks.
11. A memory apparatus comprising:
a nonvolatile memory configured to have data written thereto and read therefrom in units of clusters and to have data deleted therefrom in units of blocks each formed by a plurality of sectors; and
a control circuit configured to control said nonvolatile memory in operation;
wherein said nonvolatile memory includes
a management area in which to record management information,
a user data area in which to record data coming from a user, and
a cache area in which to hold temporarily the data to be written to and read from said user data area,
said management area includes
a logical to physical conversion table retaining relations of correspondence between addresses of logical blocks in said user data area on the one hand, and addresses of physical blocks assigned to said logical blocks on the other hand, and
addresses of physical blocks in said cache area, the physical block addresses corresponding to the physical block addresses in said logical to physical conversion table, and
said control circuit includes
thirteenth writing means for, if all cache blocks in said cache area are found fully written upon data write to user data blocks in said user data area, then writing the data to another cache block, and
second preferential processing means for, if said another cache block is found fully written upon data write by said thirteenth writing means, then carrying out garbage collection as a copy operation preparatory to executing a write-back operation preferentially on the fully-written cache blocks.
12. A memory control method for controlling a management area, a user data area, and a cache area in a nonvolatile memory configured to have data written thereto and read therefrom in units of clusters and to have data deleted therefrom in units of blocks each formed by a plurality of sectors, said memory control method comprising:
a storing step of storing a logical to physical conversion table retaining relations of correspondence between addresses of logical blocks in said user data area on the one hand, and addresses of physical blocks assigned to said logical blocks on the other hand, along with addresses of physical blocks in said cache area, the physical block addresses corresponding to the physical block addresses in said logical to physical conversion table;
a first writing step of writing, to a deleted new cache block in said cache area, data in excess of a designated logical boundary which defines a logical space size in units of a plurality of sectors within a user data block of said user data area; and
a second writing step of writing the data starting from the beginning of said new cache block upon data write in said first writing step to said new cache block, regardless of the logical address space of said new cache block.
13. The memory control method according to claim 12, further comprising, in case of a continuous data write subsequent to the data write performed in said first writing step to said new cache block, a third writing step of writing the additional data immediately in excess of written sectors within said cache block.
14. The memory control method according to claim 13, further comprising, subsequent to the data write in said first writing step to said new cache block, if it is found impossible to write data immediately in excess of said written sectors within said new cache block, a fourth writing step of performing a write to copy the data from said user data block up to a write starting sector address, before writing the additional data to said cache block.
15. The memory control method according to claim 14, further comprising, if said new cache block is found fully written upon data write in said fourth writing step, a fifth writing step of writing the data from said new cache block back to said user data block without starting garbage collection as a copy operation preparatory to executing the write-back.
16. A memory control method for controlling a management area, a user data area, and a cache area in a nonvolatile memory configured to have data written thereto and read therefrom in units of clusters and to have data deleted therefrom in units of blocks each formed by a plurality of sectors, said memory control method comprising:
a storing step of storing a logical to physical conversion table retaining relations of correspondence between addresses of logical blocks in said user data area on the one hand, and addresses of physical blocks assigned to said logical blocks on the other hand, along with addresses of physical blocks in said cache area, the physical block addresses corresponding to the physical block addresses in said logical to physical conversion table;
a sixth writing step of writing, to a deleted new cache block in said cache area, data short of a designated logical boundary which defines a logical space size in units of a plurality of sectors within a user data block of said user data area; and
a seventh writing step of writing the data starting from the beginning of said new cache block upon data write in said sixth writing step to said new cache block, regardless of the logical address space of said new cache block.
17. The memory control method according to claim 16, further comprising, in case of a data write to the same logical address space within said new cache block following the data write in said sixth writing step to said new cache block, a eighth writing step of writing the additional data immediately in excess of written sectors within said cache block.
18. The memory control method according to claim 17, further comprising, following the data write in said eighth writing step to said new cache block, if the written data is found short of said designated logical boundary, a ninth writing step of performing a write to copy the data from said user data block up to the sector address of said designated logical boundary.
19. The memory control method according to claim 18, further comprising, if said new cache block is found fully written upon data write in said ninth writing step, a tenth writing step of writing the data to another cache block.
20. The memory control method according to claim 19, further comprising, in case of a data write in excess of said designated logical border following the data write in said tenth writing step to said new cache block, a eleventh writing step of writing the data to another cache block.
21. A memory control method for controlling a management area, a user data area, and a cache area in a nonvolatile memory configured to have data written thereto and read therefrom in units of clusters and to have data deleted therefrom in units of blocks each formed by a plurality of sectors, said memory control method comprising:
a storing step of storing a logical to physical conversion table retaining relations of correspondence between addresses of logical blocks in said user data area on the one hand, and addresses of physical blocks assigned to said logical blocks on the other hand, along with addresses of physical blocks in said cache area, the physical block addresses corresponding to the physical block addresses in said logical to physical conversion table;
a twelfth writing step of, if all cache blocks in said cache area are found fully written upon data write to user data blocks in said user data area, then writing the data from said cache blocks back to said user data blocks without starting garbage collection as a copy operation preparatory to executing the write-back; and
a first preferential processing step of causing said twelfth writing step to execute said write-back to said cache blocks preferentially in ascending order of data update frequency of said cache blocks.
22. A memory control method for controlling a management area, a user data area, and a cache area in a nonvolatile memory configured to have data written thereto and read therefrom in units of clusters and to have data deleted therefrom in units of blocks each formed by a plurality of sectors, said memory control method comprising:
a storing step of storing a logical to physical conversion table retaining relations of correspondence between addresses of logical blocks in said user data area on the one hand, and addresses of physical blocks assigned to said logical blocks on the other hand, along with addresses of physical blocks in said cache area, the physical block addresses corresponding to the physical block addresses in said logical to physical conversion table;
a thirteenth writing step of, if all cache blocks in said cache area are found fully written upon data write to user data blocks in said user data area, then writing the data to another cache block; and
a second preferential processing step of, if said another cache block is found fully written upon data write in said thirteenth writing step, then carrying out garbage collection as a copy operation preparatory to executing a write-back operation preferentially on the fully-written cache blocks.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of predictive directional Web caching, comprising:
detecting a first document accessed by a user;
predicting a subsequent document which, with a highest degree of probability, is likely to be retrieved based on the first document accessed;
caching said predicted subsequent document; and
automatically downloading the subsequent document to the user’s browser before being requested by the user,
wherein the predicting is based on a distance function derived from a Euclidean distance of documents in a N-dimensional space and from a usage pattern of other users, and
wherein the distance function allows the user to move from one page to another without traversing a link.
2. The method of claim 1, further comprising:
estimating a direction in a navigation pattern of spatial data retrieval by said user.
3. The method of claim 1, wherein a plurality of subsequent documents are predicted for retrieval.
4. The method of claim 1, further comprising:
utilizing an N-dimensional space indexing technique to construct an indexed database of documents which are to be retrieved by the user.
5. The method of claim 1, wherein the predicting comprises computing a direction of trajectory based on the user’s traversals and traversals of other users.
6. The method of claim 1, further comprising:
retaining a memory of a sequence in which documents are traversed by any given user.
7. The method of claim 1, wherein, when a user retrieves first and second documents in sequence, the first document comprises an \u201corigin\u201d document of a movement and the second document comprises a \u201cdestination\u201d document,
wherein one of a trail count record entry is created in a search record index of the origin document labeled with a unique resource identifier of the destination document, and a trail count record is incremented, if a trail count record already exists.
8. The method of claim 1, wherein said first and second documents are retrieved in sequence if the user retrieves the first and second documents within a scope of a single search operation, and
wherein a point of origin of a trail comprises a point of insertion of a search and a metadata index block is created corresponding to the point of insertion, which comprises the point of origin of the traversal, thereby allowing a search result and documents for which an index position are closest to the point of origin, to be sent to the user.
9. The method of claim 10, further comprising:
selecting, by the user, one of the documents from the search result; and
one of creating a trail count record at the point of origin labeled with a unique resource identifier of the document selected, and incrementing an existing trail count record, such that the point of origin becomes a position index of a most-recently retrieved document.
10. The method of claim 9, further comprising:
when the user initiates a retrieval of a document, consulting, by a Web caching portal, the index record;
computing which points are closest to the origin, using Euclidean distances; and
computing which documents are most likely to be traversed next based on a previous usage of other users, by consulting trail records of the index.
11. The method of claim 10, further comprising:
returning, to the user, at least one of a document which the user requested, documents for which a positioning index is closest to the requested document, and documents for which the trail count record of the requested document indicates are most likely to be retrieved next.
12. The method of claim 1,
wherein, when a user retrieves a first document, a proximity list is returned to the user, indicating which documents are closest to the first document and the closest documents are returned and cached at a user’s side.
13. The method of claim 12, further comprising:
selecting, by the user, a second document from the proximity list, a hypertext link being devoid between the first and second documents.
14. The method of claim 13, further comprising:
based on said selecting of said second document, making a trail count record in an index of the first document, recording that a user retrieved the second document in sequence to the first document, and incrementing the trail count record each time other users make a same retrieval sequence.
15. The method of claim 16, further comprising:
monitoring that another user retrieves the first document;
estimating that the user is potentially interested in the second document regardless of whether there is a hypertext link from the first document to the second document; and
sending the second document to the user, for future retrieval.
16. The method of claim 1, further comprising:
providing a predictive Web caching portal at a user side, to allow a Web Browser at said user to determine which documents are likely to be retrieved next by the user, said documents being linked by hypertext links and a hypertext link tag being provided for links which contain a counter of a number of times that the user has traversed that link.
17. The method of claim 16, wherein each time that a user traverses a link, the counter is incremented and a Web document associated with the link is modified, to reflect a value of the hypertext link tag.
18. The method of claim 1, further comprising:
using techniques in a server to determine a content which the user would most likely fetch next given that the user has already fetched one document from a portal,
said techniques comprising a trails map and links listed in a proximity list which the user may click on given that the user is viewing a certain page, such that the trails map and the links are displayed in conjunction with the page the user is viewing.
19. The method of claim 18, wherein the server maintains a count attached to a file of how many times any given user has retrieved a page given that the user has retrieved a first page.
20. The method of claim 1, wherein said predicting is based on a sequence of a plurality of documents, including said first document, previously accessed.
21. The method of claim 20, further comprising:
constructing a vector based on said first document and another document of said plurality of documents; and
projecting said vector in space to determine a next document most likely to be requested by said user.
22. The method of claim 1, wherein said predicting predicts said subsequent document which is likely to be retrieved based on the first document accessed, regardless of whether there is a hypertext link from the first document to the subsequent document.
23. The method of claim 1, wherein said predicting is independent from a hypertext link from the first document to the subsequent document.
24. The method of claim 1, wherein said caching comprises automatically caching said predicted subsequent document prior to the user’s request for said predicted subsequent document.
25. A computer-implemented method of predictive directional Web caching, comprising:
detecting a first document accessed by a user; and
predicting a second document for being accessed by said user which, with a highest degree of probability, is likely to be retrieved based on the first document accessed;
caching said predicted subsequent document; and
automatically downloading the subsequent document to the user’s browser before being requested by the user,
wherein the predicting is based on a distance function derived from a Euclidean distance of documents in a N-dimensional space and from a usage pattern of other users, and
wherein the distance function allows the user to move from one pate to another without traversing a link.
26. A signal-bearing medium tangibly embodying a program of recordable machine-readable instructions executable by a digital processing apparatus to perform a method of predictive directional Web caching, said method comprising:
detecting a first document accessed by a user;
predicting a subsequent document which with highest degree of probability is likely to be retrieved based on the first document accessed;
caching said predicted subsequent document, and
automatically downloading the subsequent document to the user’s browser before being requested by the user,
wherein the predicting is based on a distance function derived from a Euclidean distance of documents in a N-dimensional space and from a usage pattern of other users, and
wherein the distance function allows the user to move from one page to another without traversing a link.

What is claimed is:

1. An exercise apparatus, comprising:
a frame having a base that is configured to rest upon a floor surface;
a left crank and a right crank, wherein each said crank is rotatably mounted on the frame;
a left rocker link and a right rocker link, wherein each said rocker link is pivotally mounted on the frame;
a left bar and a right bar, wherein each said bar has a first end rotatably connected to a respective crank;
first and second left intermediate links, wherein each of said left intermediate links is pivotally interconnected between the left rocker link and an opposite, second end of the left bar;
first and second right intermediate links, wherein each of said right intermediate links is pivotally interconnected between the right rocker link and an opposite, second end of the right bar; and
a left foot support and a right foot support, wherein each said foot support is supported by an intermediate portion of a respective bar and constrained to move through a generally elliptical path in response to rotation of each said crank.
2. The exercise apparatus of claim 1, wherein an upper distal end of one of the left intermediate links is sized and configured for grasping, and an upper distal end of one of the right intermediate links is sized and configured for grasping.
3. The exercise apparatus of claim 2, wherein said one of the left intermediate links is pivotally connected to a distal end of the left rocker link, and said one of the right intermediate links is pivotally connected to a distal end of the right rocker link.
4. The exercise apparatus of claim 1, wherein each said rocker link pivots through a range of generally horizontal orientations.
5. The exercise apparatus of claim 4, wherein said intermediate links pivot through a range of generally vertical orientations.
6. The exercise apparatus of claim 1, wherein each said foot support is movably mounted on a respective bar and operatively connected to a respective one of the intermediate links.
7. The exercise apparatus of claim 6, wherein a left connector link has a first end pivotally connected to the respective one of the left intermediate links, and a second end pivotally connected to the left foot support, and a right connector link has a first end pivotally connected to the respective one of the right intermediate links, and a second end pivotally connected to the right foot support.
8. The exercise apparatus of claim 7, wherein the first end of each said connector link is selectively movable along a respective one of the intermediate links to adjust the elliptical path of each said foot support.
9. The exercise apparatus of claim 8, wherein the first end of each said connector link is pivotally connected to a bracket, and each said bracket is slidably mounted on a respective one of the intermediate links.
10. The exercise apparatus of claim 9, wherein each said bracket is threadably mounted on a respective lead screw, and each said lead screw is operatively connected to a respective motor, and each said motor is mounted on a respective one of the intermediate links.
11. An exercise apparatus, comprising:
a frame having a base that is configured to rest upon a floor surface;
a left crank and a right crank, wherein each said crank is rotatably mounted on the frame;
a left bar and a right bar, wherein each said bar has a first end rotatably connected to a respective crank;
a left foot support and a right foot support, wherein each said foot support is supported by an intermediate portion of a respective bar;
a left guiding means for guiding an opposite, second end of the left bar through a closed loop in response to rotation of said left crank; and
a right guiding means for guiding an opposite, second end of the right bar through a closed loop in response to rotation of said right crank, wherein each said guiding means includes a rocker link pivotally mounted on the frame, and at least one intermediate link pivotally interconnected between a respective rocker link and a respective bar.
12. The exercise apparatus of claim 11, wherein on each side of the frame, an upper distal end of one said intermediate link moves through a generally elliptical path and is sized and configured for grasping.
13. The exercise apparatus of claim 11, wherein each said foot support is movably mounted on a respective bar, and on each side of the frame, a drawbar link is pivotally interconnected between one said intermediate link and a respective foot support.
14. The exercise apparatus of claim 13, further comprising a means for adjusting where each said drawbar link is pivotally connected to a respective intermediate link.
15. The exercise apparatus of claim 11, wherein each said guiding means includes first and second intermediate links pivotally interconnected between a respective rocker link and a respective bar.
16. An exercise apparatus, comprising:
a frame having a base that is configured to rest upon a floor surface;
a left crank and a right crank, wherein each said crank is rotatably mounted on the frame;
a left bar and a right bar, wherein each said bar has a first end rotatably connected to a respective crank;
a left foot support and a right foot support, wherein each said foot support is supported by an intermediate portion of a respective bar; and
a left rocker assembly and a right rocker assembly, wherein each said rocker assembly includes three links, and at least one of the links is pivotally connected to the frame, and at least one of the links is pivotally connected to a respective bar, and each of the links is pivotally connected to at least one other of the links, thereby constraining each said foot support to move through a generally elliptical path.
17. The exercise apparatus of claim 16, wherein a first one of the links is pivotally connected to the frame, and a second one of the links is pivotally interconnected between the bar and the first one of the links, and a third one of the links is pivotally interconnected between the bar and the first one of the links.
18. The exercise apparatus of claim 16, wherein a respective handle is provided on an upper end of one of the links in each said rocker assembly.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A high speed digital circuit for use with an N bit digital data signal comprising:
a. a source device for receiving said N bit digital data signal;
b. a sink device coupled to said source device and receiving said N bit digital data signal from said source device, said N bit digital data signal having a skew when received by said sink device;
c. a skew detection circuit in said sink device for detecting said skew in said N bit digital data signal and generating a skew detection signal;
d. a compensation circuit in said source device for receiving said skew detection signal and compensating for said skew in said N bit digital data signal in response thereto.
2. The circuit of claim 1, wherein said source device outputs a reference signal to said sink device, said reference signal having timing information for phase and delay detection of said skew in said N bit digital data signal.
3. The circuit of claim 2, wherein said skew detection circuit includes a circuit for detecting the skew of each of said N bits in said N bit digital data signal, generating N phase detection signals in response thereto, and multiplexing said N phase detection signals as said skew detection signal.
4. The circuit of claim 2, wherein said source device is a high complexity integrated circuit, and said sink device is a low complexity integrated circuit.
5. The circuit of claim 2, and further comprising a line for supplying a synchronization signal between said source device and said sink device.
6. The circuit of claim 5, wherein said source device includes N variable delay units for outputting said N bits, each of said variable delay units associated with and individually controlled by a respective one bit of a phase comparison signal.
7. The circuit of claim 6, wherein said source device includes a counter circuit for supplying said reference signal to said sink device.
8. The circuit of claim 7, wherein said source device includes a delay control circuit for supplying said phase comparison signal as a control signal to said N variable delay units.
9. The circuit of claim 8, wherein said source device includes N low pass filters, each of said low pass filters coupled to one of said N variable delay units, said N low pass filters being disposed between said delay control circuit and said N variable delay units.
10. The circuit of claim 9, wherein said sink device includes N phase detectors for outputting a phase comparison in response to a respective one of said N bits and said reference signal.
11. The circuit of claim 10, wherein said sink device includes a counter circuit for receiving said reference signal from said source device.
12. The circuit of claim 11, wherein said sink device includes a skew signal circuit coupled to said counter circuit and said N phase detectors for supplying said skew detection signal to said source device.
13. The circuit of claim 12, wherein said sink device includes N analog to digital converters coupled to said N phase detectors and said skew signal circuit.
14. The circuit of claim 13, and further comprising a line for supplying said synchronization signal between said counter circuits in said source device and said sink device.
15. The circuit of claim 14, wherein said sink device includes N low pass filters, each of said low pass filters connected between one of said N phase detectors and one of said N analog to digital converters.
16. The circuit of claim 1, wherein said high speed digital circuit operates in an initialization condition in which a digital initialization signal having bits of a first predefined unit length initializes said circuit, and in an operating condition in which said N bits of said N bit digital data signal have a second predefined unit length, wherein said source device includes N AND gates for receiving said N bit digital data signal and said digital initialization signal to produce a gated N bit digital data signal, and variable delay units for receiving said gated N bit digital data signal and outputting an N bit data signal in response thereto, and wherein said first predefined unit length is greater than said second predefined unit length.
17. The circuit of claim 1, and further comprising a line for supplying a reference signal from said source device to said sink device, said reference signal having timing information for phase and delay detection of said skew in said N bit digital data signal, and wherein said sink device includes N correlator units for detecting the delay between each of the N bits of said N bit digital data signal and said reference signal and outputting a phase detection signal.
18. The circuit of claim 1, wherein said sink device inserts a synchronization signal in said skew detection signal supplied to said source device, and wherein said source device includes a sync circuit for receiving said synchronization signal and synchronizing said source device with said sink device in response thereto.
19. A method of correcting the skew in an N bit digital data signal transmitted between a source device and a sink device of an interface, comprising the steps of:
a. measuring said skew in said N bit digital data signal in said sink device;
b. generating a skew detection signal in said sink device;
c. transmitting said skew detection signal from said sink device to said source device; and
d. compensating for said skew in said N bit digital data signal in said source device in response to said skew detection signal.
20. The method of claim 19, and further comprising the step of supplying a reference signal from said source device to said sink device, said reference signal having timing information for phase and delay detection of said skew in said N bit digital data signal.
21. The method of claim 20, and further comprising the steps of:
a. detecting the skew of each of the N bits in said N bit digital data signal;
b. generating N phase detection signals in response thereto; and
c. multiplexing said N phase detection signals as said skew detection signal.
22. The method of claim 20, and further comprising the step of supplying a synchronization signal between said source device and said sink device.
23. The method of claim 22, wherein said interface operates in an initialization condition and in an operating condition, and further comprising the steps of:
a. transmitting, in said operating condition, said N bit digital data signal with bits having a first predefined unit length; and
b. transmitting, in said initialization condition, a digital data signal with bits having a second predefined unit length, said second predefined unit length greater than said first predefined unit length.
24. A high speed digital interface circuit for use with an N bit digital data signal comprising:
a. an N bit bus connecting a source device and a sink device, said N bit digital data signal being received at said sink device with a skew;
b. said source device comprising:
i. N variable delay units, each associated with one of said N bits, and each of said variable delay units individually controlled for each of said N bits;
ii. a compensation circuit in said source device for compensating for said skew, said compensation circuit including:
1. a counter circuit for supplying a reference signal to said sink device;
2. an AND gate coupled to said counter circuit; and
3. N low pass filters, each associated with one of said N bits, and each of said low pass filters coupled to one of said N variable delay units and to said AND gate;
c. said sink device comprising:
i. N phase detectors, each associated with one of said N bits, and each of said phase detectors individually controlled for each of said N bits by said reference signal;
ii. N analog to digital converters, each associated with one of said N bits, coupled to said N phase detectors;
iii. a skew detection circuit in said sink device for detecting said skew in said N bit digital data signal and generating a skew detection signal, said skew detection circuit including:
1. a counter circuit for receiving said reference signal from said source device; and
2. an AND gate coupled to said counter circuit;
d. a line supplying said skew detection signal from said sink device to said source device; and
e. a line supplying said reference signal from said source device to said sink device.
25. The circuit of claim 24, and further comprising a line for supplying a synchronization signal between said counter circuits in said source device and said sink device.
26. The circuit of claim 24, wherein said skew detection circuit detects the skew of each of said N bits in said N bit digital data signal, generates N phase detection signals, each associated with one of said N bits in response thereto, and multiplexes said N phase detection signals as said skew detection signal.
27. The circuit of claim 24, wherein said source device is a high complexity integrated circuit, and said sink device is a low complexity integrated circuit.
28. The circuit of claim 24, wherein said high speed digital interface circuit operates in an initialization condition in which a digital initialization signal having bits of a first predefined unit length initializes said circuit, and in an operating condition in which said N bits of said N bit digital data signal have a second predefined unit length, wherein said source device includes N AND gates, each associated with one of said N bits, for receiving said N bit digital data signal and said digital initialization signal, and wherein said first predefined unit length is greater than said second predefined unit length.
29. The circuit of claim 24, wherein said phase detectors in said sink device are correlator units for detecting the delay between each of the N bits of said N bit digital data signal and said reference signal.
30. The circuit of claim 24, wherein said sink device inserts a synchronization signal in said skew detection signal supplied to said source device, and wherein said source device includes a sync circuit for receiving said synchronization signal and synchronizing said counters in said source device and said sink device.