Author: claimsbot

1. An on-chip noise measurement system that measures noise associated with an on-chip power supply, the system comprising:
an on-chip measurement module comprising:
a first input port for receiving an input signal;
a second input port that is coupled to the on-chip power supply;
circuitry that combines the input signal and a power supply output signal generated by the on-chip power supply; and
an output port that communicates an output signal representative of the combined input signal and the power supply output signal, wherein the output signal indicates characteristics of the noise associated with the on-chip power supply.
2. The system according to claim 1 wherein the circuitry comprises a plurality of inverters in series, wherein the input signal is input into the first of the plurality of inverters, and each of the plurality of inverters is powered by the power supply.
3. The system according to claim 2 wherein the input signal comprises a square wave.
4. The system according to claim 2 wherein the output signal comprises a combination of delayed versions of the input signal.
5. The system according to claim 4 wherein spectrum analysis of the output signal indicates the characteristics of the noise associated with the power supply output signal.
6. The system according to claim 1 wherein the characteristics of the noise associated with the power supply comprise a magnitude and phase of the noise in the frequency domain.
7. The system according to claim 1 wherein the circuitry comprises at least one mixer that mixes the input signal and the power supply.
8. The system according to claim 7 wherein the input signal comprises a sinusoidal signal.
9. The system according to claim 8 wherein the output signal comprises the sinusoidal signal modulated with the noise associated with the power supply.
10. The system according to claim 9 wherein the circuitry demodulates the output signal with the input signal yields the noise associated with the power supply.
11. A method for measuring noise associated with an on-chip power supply, the method comprising:
receiving on chip, an input signal;
combining on chip, the input signal and a power supply output signal generated by the on-chip power supply; and
generating on chip, an output signal comprising the combined input signal and the power supply output signal, wherein the output signal indicates characteristics of the noise associated with the power supply.
12. The method according to claim 11 wherein combining the input signal and the power supply output signal comprises running the input signal through a delay line powered by the power supply.
13. The method according to claim 12 wherein the delay line comprises a plurality of inverters in series, wherein the input signal is input into the first of the plurality of inverters, and each of the plurality of inverters is powered by the power supply.
14. The method according to claim 12 wherein the input signal comprises a square wave.
15. The method according to claim 12 wherein the output signal comprises a combination of delayed versions of the input signal.
16. The method according to claim 15 further comprising analyzing the output signal to determine the characteristics of the noise associated with the power supply.
17. The method according to claim 11 wherein the characteristics of the noise associated with the power supply comprise a magnitude and spectrum of the noise in the frequency domain.
18. The method according to claim 11 wherein combining the input signal and the power supply comprises mixing the input signal and the power supply.
19. The method according to claim 18 wherein the input signal comprises a sinusoidal signal and the output signal comprises the sinusoidal signal modulated with the noise associated with the power supply.
20. The method according to claim 19 further comprising demodulating the output signal with the input signal to extract the noise associated with the power supply.
21. An on-chip noise measurement system that measures noise associated with an on-chip power supply, the system comprising:
an on-chip measurement module comprising:
a first input port and an output port;
a second input port coupled to the on-chip power supply; and
combining circuitry coupled to the first input port, the second input port, and the output port, wherein the combining circuitry comprises a plurality of serially coupled inverters that are coupled between the first input port and the output port and each of the each of the plurality of inverters is coupled to the on-chip power supply and powered therefrom.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A semiconductor device, comprising:
a substrate comprising an inactive region and an active region, wherein the active region comprises: a lateral edge which defines an active width of the active region, and a transverse edge which defines a length of the active region;
a gate electrode structure comprising:
a common portion spaced apart from the active region by a first distance; and
a plurality of gate electrode finger portions integral with the common portion,

wherein a portion of each gate electrode finger portion overlie the active region,
wherein a gate length of the portion of each gate electrode finger portion which overlies the active region is substantially uniform; and
a compressive layer overlying the active region and the gate electrode finger portions; and
a tensile layer overlying the inactive region outside the active region and disposed adjacent the transverse edge of the active region, wherein the tensile layer overlies a portion of the compressive layer that does not overlap with the active region.
2. A semiconductor device according to claim 1, wherein the gate electrode structure further comprises:
a plurality of fillet portions integral with the common portion and the gate electrode finger portions, wherein the fillet portions have a concave-shaped edge and are disposed between the common portion and the gate electrode finger portions, and wherein the fillet portions do not overlie the active region.
3. A semiconductor device according to claim 2, wherein the active width is between 0.1 \u03bcm and 1.0 \u03bcm, and wherein the first distance is between 0.01 \u03bcm and 0.04 \u03bcm so that the fillet portions do not overlie the active region to reduce variations in gate length of the portion of each gate electrode finger portion which overlie the active region due to corner rounding of the fillet portions.
4. A semiconductor device according to claim 2, wherein the tensile layer increases stress in the active region to increase drive current in the active region so that an active width is reduced and the fillet portions are non-overlying the active region without increasing layout area occupied by the semiconductor device.
5. A semiconductor device according to claim 1, wherein the tensile layer disposed adjacent the active region, the gate electrode finger portions, and the compressive layer.
6. A semiconductor device according to claim 5, wherein the tensile layer does not overlie the active region.
7. A semiconductor device according to claim 6, wherein the tensile layer is spaced apart from the compressive layer by a distance of at least 0.02 \u03bcm.
8. A semiconductor device comprising:
a substrate comprising an inactive region and an active region, wherein the active region comprises: a lateral edge which defines an active width of the active region, and a transverse edge which defines a length of the active region;
a gate electrode structure having portions overlying the active region, the gate electrode structure comprising: a common portion, a plurality of gate electrode finger portions integral with the common portion; and a plurality of fillet portions integral with the common portion and the gate electrode finger portions, wherein the fillet portions do not overlie the active region;
a compressive layer overlying the active region; and
a tensile layer overlying the inactive region outside the active region and disposed adjacent the transverse edge of the active region.
9. A semiconductor device according to claim 8, wherein the common portion is spaced apart from the active region by a first distance; wherein a portion of each gate electrode finger portion overlie the active region, wherein a gate length of the portion of each gate electrode finger portion which overlies the active region is substantially uniform; and wherein the fillet portions have a concave-shaped edge and are disposed between the common portion and the gate electrode finger portions.
10. A semiconductor device according to claim 9, wherein the active width is between 0.1 \u03bcm and 1.0 \u03bcm, and wherein the first distance is between 0.01 \u03bcm and 0.04 \u03bcm so that the fillet portions do not overlie the active region to reduce variations in a gate length of the portion of each gate electrode finger portion which overlie the active region.
11. A semiconductor device according to claim 9, wherein the tensile layer is disposed adjacent the active region and does not contact the active region, wherein the tensile layer overlies a portion of the compressive layer that does not overlap with the active region, wherein the tensile layer increases stress in the active region to increase drive current in the active region so that the fillet portions are non-overlying the active region without increasing layout area occupied by the semiconductor device.
12. A semiconductor device according to claim 8, wherein the tensile layer is spaced apart from the compressive layer by a distance of at least 0.02 \u03bcm.
13. A semiconductor device, comprising:
a substrate comprising an inactive region and an active region;
a gate electrode structure having a portion overlying the active region, the gate electrode structure comprising: a common portion; a plurality of gate electrode finger portions integral with the common portion; and a plurality of fillet portions integral with the common portion and the gate electrode finger portions, wherein the fillet portions are non-overlying the active region;
a compressive stress layer overlying the active region and the gate electrode finger portions;
a tensile stress layer overlying a portion of the inactive region that is spaced apart from the active region and in contact with the inactive region,
wherein a portion of the tensile stress layer overlies a portion of the compressive stress layer and is spaced apart from and non-overlapping the active region.
14. A semiconductor device according to claim 13, wherein the common portion is spaced apart from the active region by a first distance.
15. A semiconductor device according to claim 14, wherein the first distance is between 0.01 \u03bcm and 0.04 \u03bcm to reduce variations in a gate length of the portion of each gate electrode finger portion which overlie the active region due to corner rounding of the fillet portions.
16. A semiconductor device according to claim 13, wherein a portion of each gate electrode finger portion overlies the active region, and wherein a gate length of the portion of each gate electrode finger portion which overlies the active region is substantially uniform.
17. A semiconductor device according to claim 13, wherein the fillet portions are located along interior corner portions of the gate electrode structure between side portions of the gate electrode finger portions and the common portion and have a concave-shaped edge and are disposed between the common portion and the gate electrode finger portions.
18. A semiconductor device according to claim 13, wherein the tensile layer is spaced apart from the compressive layer by a distance of at least 0.02 \u03bcm.
19. A semiconductor device according to claim 13, wherein the active region comprises: a lateral edge which defines an active width of the active region, and a transverse edge which defines a length of the active region, and wherein the active width is between 0.1 \u03bcm and 1.0 \u03bcm.
20. A semiconductor device according to claim 13, wherein the remaining portion of the tensile stress layer increases compressive stress of the remaining portion of the compressive stress layer overlying the active region and increases stress in the active region to increase drive current in the active region.

1. A solar tracking apparatus for use with a power driving apparatus, the solar tracking apparatus comprises:
a memory unit for recording a first solar image;
an image capturing unit for capturing a second solar image; and
an processing unit for obtaining a difference between the first solar image and the second solar image;
wherein the processing unit activates the power driving apparatus in response to the difference.
2. The solar tracking apparatus of claim 1, wherein the first solar image is a default reference solar image, and the second solar image is a solar image taken on the spot.
3. The solar tracking apparatus of claim 1, wherein the processing unit further calculates a first solar center from the first solar image and a second solar center from the second solar image, and the difference is obtained by comparing the first solar center with the second solar center.
4. The solar tracking apparatus of claim 1, wherein the difference is recorded in the memory unit to provide the processing unit to activate the power driving apparatus in advance.
5. The solar tracking apparatus of claim 1, further comprising an optical unit for focusing the sun light onto the image capturing unit to form the second solar image.
6. The solar tracking apparatus of claim 5, wherein the optical unit is a lens.
7. The solar tracking apparatus of claim 5, wherein the optical unit is a wide-angle lens.
8. The solar tracking apparatus of claim 1, wherein the image capturing unit is a charge coupled device (CCD) or a complementary metal-oxide semiconductor (CMOS).
9. The solar tracking apparatus of claim 1, wherein the image capturing unit further captures a plurality of second solar images, and each second solar image is taken after a predetermined time interval.
10. A solar power generation system includes:
a solar panel;
a power driving apparatus for adjusting the solar panel; and
a solar tracking apparatus including:
a memory unit for recording a first solar image;
an image capturing unit for capturing a second solar image; and
an processing unit for obtaining difference between the first solar image and the second solar image;
wherein the processing unit activates the power driving apparatus in response to the difference so that the solar panel can be aligned towards the sun to gather sun light.
11. The system of claim 10, wherein the first solar image is a default reference solar image, and the second solar image is a solar image taken on the spot.
12. The system of claim 10, wherein the processing unit further calculates a first solar center from the first solar image and a second solar center from the second solar image, and the difference is obtained by comparing the first solar center with the second solar center.
13. The system of claim 10, wherein the difference is recorded in the memory unit to provide the processing unit to activate the power driving apparatus in advance.
14. The system of claim 10, further comprising an optical unit for focusing the sun light onto the image capturing unit to form the second solar image.
15. The system of claim 14, wherein the optical unit is a lens.
16. The system of claim 14, wherein the optical unit is a wide-angle lens.
17. The system of claim 10, wherein the image capturing unit is a charge coupled device (CCD) or a complementary metal-oxide semiconductor (CMOS).
18. The system of claim 10, wherein the image capturing unit further captures a plurality of second solar images, and each second solar image is taken after a predetermined time interval.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. A method for producing a fertile transgenic plant, comprising the steps of:
(a) introducing one or more genetic component(s) one desires to introduce into the genome of a plant by co-culturing a regenerable plant cell or tissue with Agrobacterium containing said genetic component(s);
(b) co-culturing said Agrobacterium and regenerable plant cells or tissues of step (a) under conditions that decrease the weight of said Arobacterium-inoculated explant;
(c) identifying or selecting a transformed cell line; and
(d) regenerating a fertile transgenic plant therefrom.
2. The method of claim 1 wherein the regenerable cell or tissue is precultured prior to step (a).
3. The method of claim 1 wherein the conditions for co-culture comprise limitation or removal of moisture from the Agrobacterium-inoculated explant wherein the weight of the explant is reduced by not more than 50%.
4. The method of claim 3 wherein the weight of the Agrobacterium-inoculated explant is reduced by up to 40%.
5. The method of claim 3 wherein the weight of the Agrobacterium-inoculated explant is reduced by up to 30%.
6. The method of claim 3 wherein the moisture-limitation or removal period after inoculation with Agrobacterium is greater than one hour.
7. The method of claim 3 wherein the moisture-limitation or removal period after inoculation with Agrobacterium is from one hour to about 6 days.
8. The method of claim 3 wherein the moisture-limitation or removal period after inoculation with Agrobacterium is from about one day to about 4 days.
9. The method of claim 3 wherein the moisture-limitation or removal period after inoculation with Agrobacterium is from about one day to about 3 days.
10. The method of claim 1 wherein the transgenic plant is a monocot.
11. The method of claim 1 wherein the transgenic plant is a dicot.
12. The method of claim 10 wherein the monocot is wheat, corn, or rice.
13. The method of claim 10 wherein the monocot is wheat.
14. The method of claim 10 wherein the monocot is corn.
15. The method of claim 10 wherein the monocot is rice.
16. The method of claim 11 wherein the dicot is soybean.