Author: claimsbot

1. An anti-Chlamydia agent, which comprises containing tea polyphenol.
2. The anti-Chlamydia agent as claimed in claim 1, wherein the tea polyphenol is at least one selected from the group consisting of ()-catechin, ()-catechin, ()-gallocatechin, ()-epigallocatechin, ()-gallocatechin gallate, ()-epigallocatechin gallate, ()-epicatechin, ()-epicatechin gallate, ()-catechin gallate, ()-epigallocatechin, ()-gallocatechin, () -epigallocatechin gallate, () -gallocatechin gallate, teaflavin monogallate A, teaflavin monogallate B, teaflavin digallate, and free teaflavin.
3. The anti-Chlamydia agent as claimed in claim 1, wherein Chlamydia is Chlamydia trachomatis.
4. A preventive or therapeutic method for a Chlamydia infectious disease, characterized by administering a composition containing tea polyphenol in an amount effective for the therapy of a Chlamydia infectious disease on an affected part of a patient.
5. The preventive or therapeutic method as claimed in claim 4, wherein the composition is in the form of cream, paste, gel, ointment, milky lotion, solution or suspension.
6. The preventive or therapeutic method as claimed in claim 4, wherein the tea polyphenol in the composition is in a concentration of 0.2 to 50 mgml when used in the form of liquid, milky lotion, or the like or 0.2 to 200 mgg when used in the form of cream, paste, gel, ointment or the like.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. An interleave type decoding method, comprising steps of:
receiving an interleaved block containing a number, L, of interleaved codewords, wherein the interleaving was done in such a manner that any L consecutive symbols consist of exactly one symbol from each of the L codewords, the interleaved codewords being made up of symbols;
de-interleaving the interleaved block of symbols to obtain estimated codewords for the block of symbols, wherein errors may be present in the symbols;
performing a first decoding of the estimated codewords by using a first error correction code;
marking erasure positions in uncorrectable estimated codewords; and
performing a second decoding of the estimated codewords by using the first error correction code, where the second decoding is at least partially based on the erasure positions marked from correctable estimated codewords.
2. The method of claim 1 wherein marking erasure positions further comprises marking erasure positions according to error positions extracted from correctable estimated codewords.
3. The method of claim 1 wherein performing a second decoding further comprises decoding only the uncorrectable estimated codewords according to the erasure positions marked from correctable estimated codewords.
4. The method of claim 1 further comprising determining a number of uncorrectable estimated codewords, wherein the determining function is done after the second decoding.
5. The method of claim 1 further comprising determining a number of uncorrectable estimated codewords, wherein the determining function is done after the first decoding.
6. The method of claim 1, wherein the single burst error correction capability is enhanced to L(t01)1 symbols, where L is the number of codewords in the de-interleaved block and t0 is the random error correction capability of an individual codeword.
7. The method of claim 1, wherein an encoding procedure used to create the interleaved block comprises a transmission index that is assigned to each symbol according to the order in which the symbols will be transmitted through a communication channel.
8. The method of claim 7, wherein marking erasure positions further comprises:
sorting error positions, obtained in the first decoding, by the transmission index of erroneous symbols; and
examining the intervals between each consecutive error position.
9. The method of claim 8, wherein the examining the intervals further comprises:
determining an interval between consecutive error positions el and el1; comparing the interval to a predefined threshold which is not greater than L;
marking as erasures the symbols that have a transmission index between elL1 and el1L1, if the interval is less than the predefined threshold, where L represents the number of codewords in an interleave block.
10. The method of claim 9, wherein the predefined threshold is the same as L.
11. A decoder for use in a data communication system wherein random and burst errors may be present in the transmitted information code, comprising:
(a) an erasure marker for marking erasure positions in data sequences; and
(b) an error correction circuit for performing error correction on a de-interleaved block that was decoded from an interleaved block, where the interleaved block contained a number, L, of interleaved codewords, wherein the interleaving was done in such a manner that any L consecutive symbols consisted of exactly one symbol from each of the L codewords, operably coupled to the erasure marker, the error correction circuit being designed to perform a first decoding of the estimated codewords and subsequently perform a second decoding of the estimated codewords where the second decoding uses the same error correction circuit as the first decoding and is at least partially based on the erasure positions marked by the erasure marker.
12. The decoder of claim 11 wherein the erasure marker further comprises circuitry for marking erasure positions according to error positions extracted from correctable estimated codewords.
13. The decoder of claim 11 wherein the error correction circuitry further comprises circuitry for performing a second decoding only on the uncorrectable estimated codewords according to the erasure positions extracted from correctable estimated codewords.
14. The decoder of claim 11 wherein the error correction circuitry further comprises a counter for determining a number of uncorrectable estimated codewords.
15. The decoder of claim 11 wherein the error correction circuitry further comprises a counter for determining a number of uncorrectable estimated codewords after the second decoding.
16. The decoder of claim 11 wherein the error correction circuitry further comprises a counter for determining a number of uncorrectable estimated codewords after the first decoding.
17. The decoder of claim 11 wherein the single burst error correction capability is enhanced to L(t01)1 symbols, where L is the number of codewords in an interleaved block and t0 is the random error correction capability of an individual codeword.
18. A disc drive comprising the decoder of claim 11 and further comprising:
at least one disc for storing data;
a transducer for reading and writing data from the disc;
a communication channel, operatively coupled to the transducer for transmitting data, the communication channel comprising the decoder.
19. A data communication system comprising:
(a) an encoder for producing an interleaved block containing a number, L, of interleaved codewords, wherein the interleaving was done in such a manner that any L consecutive symbols consist of exactly one symbol from each of the L codewords, the codewords containing symbols;
(b) a communication channel, operatively coupled to the encoder, that may introduce errors into the transmitted sequences;
(c) a decoder, operatively coupled to the communication channel, comprising:
(i) an erasure marker for marking erasure positions in estimated codewords, and
(ii) an error correction circuit for performing error correction on a de-interleaved block that was decoded from an interleaved block, where the interleaved block contained a number, L, of interleaved codewords, wherein the interleaving was done in such a manner that any L consecutive symbols consisted of exactly one symbol from each of the L codewords, operably coupled to the erasure marker, the error correction circuit being designed to perform a first decoding of the estimated codewords and subsequently perform a second decoding of the estimated codewords where the second decoding uses the same error correction circuit as the first decoding and is at least partially based on the erasure positions marked by the erasure marker.
20. The data communication system of claim 19 wherein the erasure marker further comprises circuitry for marking erasure positions according to error positions extracted from correctable estimated codewords.
21. The data communication system of claim 20 wherein the error correction circuitry further comprises circuitry for performing a second decoding only on the uncorrectable estimated codewords according to the erasure positions extracted from correctable estimated codewords.
22. The data communication system of claim 19 wherein the error correction circuitry further comprises a counter for determining a number of uncorrectable estimated codewords.
23. The data communication system of claim 19 wherein the encoder further comprises a transmission index that is assigned to each symbol according to the order in which the symbols are transmitted through the channel.
24. The data communication system of claim 19 implemented in a communication channel of a storage device such as a disc drive or CD-ROM.
25. A digital communication channel, comprising:
an interleave type encoder; and
means for decoding interleaved codewords using erasure markers.
26. A digital communication channel, comprising:
an interleave type encoder used for obtaining an interleaved block containing a number, L, of interleaved codewords, wherein the interleaving was done in such a manner that any L consecutive symbols consist of exactly one symbol from each of the L codewords; and
means for decoding estimated codewords at least twice while using the same error correction technique.
27. The digital communication channel of claim 26 where the means for decoding further comprises:
means for decoding uncorrectable estimated codewords according to erasure positions extracted from correctable estimated codewords.
28. The digital communication channel of claim 26 further comprising. means for transmitting an index for an arranged sequence of symbols.
29. The digital communication channel of claim 26 further comprising:
means for marking symbols in estimated codewords as erasures.

1. A method of validating a configuration description of an automation device in a power system, wherein said description is encoded in a standardized configuration description language based on an XML schema, and wherein said description is subject to notations, requirements andor conventions which are not incorporated in said XML schema, comprising:
identifying, from Parts 7-2, 7-3 and 7-4 of an International Electrotechnical Committee 61850 standard, notations to be validated;
generating therefrom extended rules in a computer-readable format;
checking said description for conformance to the extended rules; and
issuing, in case a discrepancy is found, a notification to a user,
displaying, via a Human-Machine Interface, the notification to the user.
2. The method according to claim 1, wherein the conformance checking is executed during an engineering phase of a Substation Automation (SA) system.
3. The method according to claim 1, comprising:
checking the description for consistency with a rule generated from notations as defined in Part 7-2, 7-3 and 7-4 of the International Electrotechnical Committee 61850 standard.
4. The method according to claim 1, comprising:
checking the description for consistency with a rule representing application specific, project specific or other user defined requirements.
5. The method according to claim 1, comprising:
checking the description for consistency with power system operation principles.
6. A non-transitory computer readable medium containing a computer program for validating a configuration description of a Substation Automation (SA) system or of an Intelligent Electronic Device (IED), wherein said description is encoded in a Standardized Configuration description Language (SCL) based on an XML schema, and wherein said description is subject to notations, requirements andor conventions from Parts 7-2, 7-3 and 7-4 of an International Electrotechnical Committee 61850 standard, which are not incorporated in said XML schema, to be validated the computer program performing, when executed, the steps of:
checking said description for conformance with extended rules generated in a computer-readable format from the notations, requirements or conventions to be validated; and
issuing, in case a discrepancy is found, a notification to a user.
7. A non-transitory computer readable storage medium containing a computer program for execution by a computer for validating a configuration description of a Substation Automation system or of an Intelligent Electronic Device, wherein said description is encoded in a Standardized Configuration description Language based on an Extensible Markup Language schema, and wherein said description is subject to notations, requirements andor conventions which are not incorporated in said schema, wherein the computer program performs the steps of:
identifying, from Parts 7-2, 7-3 and 7-4 of an International Electrotechnical Committee 61850 standard, notations, to be validated;
generating there from extended rules in a computer-readable format;
checking said description for conformance to the extended rules; and
issuing, in case a discrepancy is found, a notification to a user.
8. The computer readable storage medium according to claim 7, wherein the step of conformance checking is executed during an engineering phase of the Substation Automation system.
9. The computer readable storage medium according to claim 7, wherein the computer program performs the step of:
checking the description for consistency with a rule generated from notations.
10. The computer readable storage medium according to claim 7, wherein the computer program performs the step of:
checking the description for consistency with a rule representing application specific, project specific or other user defined requirements.
11. The computer readable storage medium according to claim 7, wherein the computer program performs the step of:
checking the description for consistency with power system operation principles.
12. The method according to claim 1, wherein the automation devices are Substation Automation systems andor Intelligent Electronic Device components of the Automation systems.
13. The method according to claim 1, wherein the power system includes one or more of wind power, hydropower and Distributed Energy Resources (DER) components.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. A semiconductor integrated circuit having an internal monitoring function, said semiconductor integrated circuit comprising:
an internal power supply circuit for generating a driving voltage which is obtained by shifting the level of a power supply voltage;
a limiter circuit, which is operated by the input of a mode signal, for monitoring said driving voltage which is outputted from said internal power supply circuit, and for outputting an activating signal which has a first logical level until said driving voltage reaches a predetermined value and which has a second logical level after said driving voltage reaches said predetermined value, to activate and control said internal power supply circuit; and
a monitoring circuit for detecting a first change of said activating signal from said first logical level to said second logical level after the operation of said limiter circuit is started, and for outputting a monitoring signal having a constant logical level while said limiter circuit operates after said first change of said activating signal is detected.
2. A semiconductor integrated circuit as set forth in claim 1, wherein said monitoring circuit is activated in a test mode, and said monitoring signal is transferred and outputted to a first external terminal.
3. A semiconductor integrated circuit as set forth in claim 2, wherein said monitoring circuit comprises:
a comparator, to which an external power supply voltage supplied from a second external terminal is given and which is activated in said test mode, for comparing a voltage of a monitoring node which is provided for monitoring said driving voltage of said internal power supply circuit, with a reference voltage which is supplied from a third external terminal, and for outputting said monitoring signal; and
a transfer gate for transferring said monitoring signal, which is outputted from said comparator, to said first external terminal.
4. A semiconductor integrated circuit as set forth in claim 3, wherein said reference voltage supplied from said third external terminal is a voltage, the level of which varies with the elapse of time so as to cross a voltage value which is to be monitored by said monitoring node.
5. A semiconductor integrated circuit as set forth in claim 3, wherein a transfer gate driven by a boosted voltage is provided in a path for supplying said external power supply voltage from said second external terminal to said comparator.
6. A semiconductor integrated circuit as set forth in claim 3, wherein a transfer gate driven by said external power supply voltage or a voltage boosted therein is provided in a path for supplying a reference voltage from said third external terminal to said comparator.
7. A semiconductor integrated circuit as set forth in claim 2, wherein said monitoring circuit comprises:
a comparator, to which an external power supply voltage supplied from a second external terminal is given and which is activated in said test mode, for comparing a voltage of a monitoring node which is provided for monitoring said driving voltage of said internal power supply circuit, with a reference voltage which is obtained by potential-dividing said external power supply voltage, and for outputting said monitoring signal; and
a transfer gate for transferring said monitoring signal, which is outputted from said comparator, to said first external terminal.
8. A semiconductor integrated circuit as set forth in claim 7, wherein said external power supply voltage supplied from said second external terminal is a voltage, the level of which varies with the elapse of time so that said reference voltage crosses a voltage value which is to be monitored by said monitoring node.
9. A semiconductor integrated circuit as set forth in claim 7, wherein a transfer gate driven by a boosted voltage is provided in a path for supplying said external power supply voltage from said second external terminal to said comparator.
10. A semiconductor integrated circuit as set forth in claim 2, wherein said monitoring circuit comprises:
a comparator, activated in said test mode, for comparing a voltage of a monitoring node which is provided for monitoring said driving voltage of said internal power supply circuit, with a reference voltage which is supplied from a third external terminal, and for outputting said monitoring signal; and
a transfer gate for transferring said monitoring signal, which is outputted from said comparator, to said first external terminal.
11. A semiconductor integrated circuit as set forth in claim 10, wherein said reference voltage supplied from said third external terminal is a voltage, the level of which varies with the elapse of time so as to cross a voltage value which is to be monitored by said monitoring node.
12. A semiconductor integrated circuit as set forth in claim 10, wherein a transfer gate driven by an external power supply voltage or a voltage boosted therein is provided in a path for supplying a reference voltage from said third external terminal to said comparator.
13. A semiconductor integrated circuit as set forth in claim 2, wherein said monitoring circuit comprises:
a first latch circuit for detecting and holding a change of said activating signal to said first logical level immediately after an operation starts;
a second latch circuit for detecting and holding a first change of said activating signal to said second logical level after said operation starts; and
a gate circuit for obtaining said monitoring signal by a logical product of data held by said first and second latch circuits.
14. A semiconductor integrated circuit as set forth in claim 1, which further comprises:
a comparing part for comparing a predetermined voltage with a reference voltage;
an internal voltage generating part for generating an internal voltage on the basis of an output of said comparing part; and
a divided resistance part for potential-dividing into said predetermined voltage by dividing an internal voltage node with resistance,
said semiconductor integrated circuit having a test mode for determining an internal resistance value by supplying a desired trimming voltage from the outside to an external terminal connected to a first node which is an node between said internal voltage generating part and said divided resistance part, deactivating a feedback to said internal voltage generating part by the output of said comparing part, and detecting a compared result which is the output of said comparing part, in order to set said internal resistance value so as to be a desired voltage.
15. A semiconductor integrated circuit having a voltage trimming function, said semiconductor integrated circuit comprising:
a comparing part for comparing a predetermined voltage with a reference voltage;
an internal voltage generating part for generating an internal voltage on the basis of an output of said comparing part; and
a divided resistance part for potential-dividing into said predetermined voltage by dividing an internal voltage node with resistance,
said semiconductor integrated circuit having a test mode for determining an internal resistance value by supplying a desired trimming voltage from the outside to an external terminal connected to a first node which is an node between said internal voltage generating part and said divided resistance part, deactivating a feedback to said internal voltage generating part by the output of said comparing part, and detecting a compared result which is the output of said comparing part, in order to set said internal resistance value so as to be a desired voltage.
16. A semiconductor integrated circuit as set forth in claim 15, which further comprises a first reference voltage generating part for generating a reference voltage for the whole chip.
17. A semiconductor integrated circuit as set forth in claim 15, which further comprises a second reference voltage generating circuit for generating a second reference voltage, which is stepped down by level-shifting said first reference voltage, when a first reference voltage, which is a reference voltage for the whole chip, is higher than said trimming voltage which is supplied from said external terminal.
18. A semiconductor integrated circuit as set forth in claim 15, wherein said internal voltage generating part comprises:
an oscillator circuit operated by an activating signal which is outputted when said internal voltage is higher than a power supply voltage;
a booster circuit for outputting a boosted voltage, which is boosted in response to a pulse outputted from said oscillator circuit, to said first node; and
a control part for controlling a change of said oscillator circuit between activation and deactivation by a compared result, which is outputted from said comparing part, by said desired trimming voltage which is supplied from said external terminal in said test mode.
19. A semiconductor integrated circuit as set forth in claim 15, wherein said internal voltage generating part comprises:
an oscillator circuit operated by an activating signal which is outputted when said internal voltage is higher than a power supply voltage;
a booster circuit for outputting a boosted voltage, which is boosted in response to a pulse outputted from said oscillator circuit, to said first node; and
a control part for controlling a change of said booster circuit between activation and deactivation by a compared result, which is outputted from said comparing part, by said desired trimming voltage which is supplied from said external terminal in said test mode.
20. A semiconductor integrated circuit as set forth in claim 15, wherein said divided resistance part includes a variable resistor for varying a resistance value on the basis of said compared result in said test mode, said divided resistance part previously setting a set level of said trimming voltage, which is supplied from said external terminal, to be a predetermined step width, and shifting said step width upwards or downwards by a half step during a trimming test to control said set level with the precise of said half step.
21. A semiconductor integrated circuit having a function capable of generating an internal voltage by comparison with a reference voltage and fine-controlling an internal voltage value by bit data, said semiconductor integrated circuit comprising means for supplying a first voltage from the outside to an output node of an internal voltage generating circuit during a test, detecting bit data wherein a voltage ratio of an internal voltage value to a reference voltage is closest to a voltage ratio of said first voltage to a reference voltage, and fine-controlling an internal voltage in accordance with bit data during an operation other than said test.