All The Claims

1. A method for determining relative clock signal jitter, comprising:
providing a delay circuit;
providing a system clock signal to the delay circuit;
providing a reference clock signal to operate the delay circuit;
outputting a first measurement signal from the delay circuit representing a first time delay of the system clock signal relative to the reference clock signal;
outputting a second measurement signal from the delay circuit representing a second time delay of the system clock signal with respect to the reference clock signal; and
determining a time difference between the first time delay and the second time delay.
2. The method of claim 1, wherein the determining the first time delay comprises:
detecting a system clock edge of the system clock;
detecting a reference clock edge of the reference clock; and
determining the first time delay between the system clock edge detected and the reference clock edge detected.
3. The method of claim 1, wherein the outputting of the first measurement signal comprises encoding the first measurement signal.
4. The method of claim 1, wherein the outputting the second measurement signal comprises encoding the second measurement signal.
5. The method of claim 1, further comprising:
providing another system clock signal to another delay circuit; and
determining a skew between the system clock signal and the other system clock signal.
6. A method for determining jitter of a on-chip clock signal with respect to a reference clock signal, comprising:
delaying the on-chip clock signal relative to the reference clock signal;
providing a signal output indicative of delay of the on-chip clock signal relative to the reference clock signal;
detecting a transition of the on-chip clock signal;
measuring a first time delay initiated from the transition relative to the reference clock signal;
outputting a binary number indicative of the first time delay;
detecting another transition of the on-chip clock signal;
measuring a second time delay initiated from the other transition relative to the reference clock signal;
outputting another binary number indicative of the second time delay; and
determining a time difference between the first time delay and the second time delay.
7. The method of claim 6, wherein the detecting the transition comprises:
providing a delay circuit;
clocking the delay circuit with the reference clock signal; and
detecting at least one edge of the clock signal.
8. The method of claim 6, wherein the outputting the binary number comprises outputting at least two signals representing a transition binary number.
9. The method of claim 8, wherein the outputting the other binary number comprises outputting at least two signals representing a another transition binary number.
10. The method of claim 6, wherein the determining the time difference comprises subtracting the binary number from the other binary number.
11. A method for determining jitter, comprising:
delaying a first clock signal relative to a reference clock signal;
providing a first signal output responsive to delay of the first clock signal relative to the reference clock signal;
detecting a first transition of the first clock signal;
measuring a first time delay associated with the first transition relative to the reference clock signal;
outputting a first binary number for the first time delay;
detecting a second transition of the first clock signal;
measuring a second time delay initiated from the second transition relative to the reference clock signal;
outputting a second binary number for the second time delay; and
determining a time difference between the first time delay and the second time delay.
12. The method of claim 11, further comprising determining skew between the clock signal and another clock signal.
13. The method of claim 12, wherein the determining the skew comprises detecting a transition of the other clock signal.
14. The method of claim 13, further comprising;
outputting a third binary number responsive to a third time delay relative to the reference clock signal for the other clock signal; and
subtracting the first time delay from the third time delay.
15. A method for determining clock signal skew, comprising:
providing a first time delay determination circuit;
providing a first clock signal to the first time delay determination circuit;
providing a second time delay determination circuit;
providing a second clock signal to the second time delay determination circuit;
providing a reference clock signal to operate the first time delay determination circuit and the second time delay determination circuit;
outputting a first measurement signal from the first time delay determination circuit indicative of a first clock signal time delay relative to the reference clock signal;
outputting a second measurement signal from the second time delay determination circuit indicative of a second clock signal time delay relative to the reference clock signal; and
determining a time difference between the first clock signal time delay and the second clock signal time delay.
16. The method of claim 15, wherein the outputting the first measurement signal comprises:
encoding the first measurement signal; and
outputting from the first time delay determination circuit a first binary number indicative of the first clock signal time delay.
17. The method of claim 16, wherein the outputting the signal measurement signal comprises:
encoding the second measurement signal; and
outputting from the second time delay determination circuit a second binary number indicative of second clock signal time delay.
18. The method of claim 17, wherein the step of determining a time difference comprises subtracting the first binary and second binary number.
19. An apparatus to determine clock signal noise, comprising:
a delay circuit coupled to receive a clock signal and a reference signal and configured to provide an output signal indicative of delay between the clock signal and the reference signal;
a measuring circuit configured to receive and process the output signal to provide a measurement value; and
a data processing circuit configured to:
store the measurement value as a reference value;
compare the reference value to one of a plurality of measurement values to determine a first delay value between the clock signal and the reference signal;
compare the reference value to another one of the plurality of measurement values to determine a second delay value between the clock signal and the reference signal; and
compare the first delay value to the second delay value to determine a time difference.
20. The apparatus of claim 19, wherein the apparatus is coupled to a programmable logic device.
21. The apparatus of claim 19, wherein at least some part of the apparatus is implemented within a fabric of a programmable logic device.
22. The apparatus of claim 19, wherein the measuring circuit comprises an encoder configured to receive the output signal to provide at least some of the plurality of measurement values.
23. The apparatus of claim 22, wherein the data processing circuit comprises a subtraction circuit configured to provide a resultant value between the reference value and at least one of the plurality of measurement values.
24. The apparatus of claim 22, wherein the data processing circuit comprises a register configured to store the reference value.
25. The apparatus of claim 19, wherein the output signal represents a plurality of time delay values.
26. The apparatus of claim 25, wherein the plurality of time delay values increment to provide at least a portion of a total time delay.
27. The apparatus of claim 19, further comprising another delay circuit, the other delay circuit coupled to receive another clock signal and the reference clock signal and configured to provide another output signal, the other output signal indicating delay between the other clock signal and the reference clock signal.
28. The apparatus of claim 27, further comprising another measuring circuit configured to receive and process the other output signal to provide another measurement value.
29. The apparatus of claim 27, wherein the data processing circuit is configured to compare delays between the clock signal and the other clock signal with respect to the reference clock signal to determine a skew therebetween.
30. A system for measuring jitter of an input signal, comprising:
a relative phase encoder, the relative phase encoder including a delay chain and flip-flops, the delay chain having a plurality of tap nodes, the plurality of tap nodes respectively connected to flip-flop delay inputs of the flip-flops for sampling the input signal to the delay chain, the relative phase encoder configured to receive a clock signal to first flip-flop clock inputs of the flip-flops, the relative phase encoder having an encoder respectively coupled to flip-flop outputs of the flip-flops and configured to provide encoded phase of the input signal relative to the clock signal responsive to the flip-flop outputs; and
a data compare circuit coupled to receive the encoded phase and configured to compare the encoded phase with a stored reference sample.
31. The system of claim 30, wherein the stored reference sample is obtained from a prior instance of the encoded phase for the input signal.
32. The system of claim 31, wherein the data compare circuit comprises registers for storing the encoded phase and the stored reference sample.
33. The system of claim 32, wherein the data compare circuit comprises a subtractor coupled to receive the stored reference sample and the encoded phase stored to provide a difference output, wherein the difference output represents at least a portion of the jitter.
34. The system of claim 33, further comprising a validity check circuit coupled to the relative phase encoder to check validity of output on the flip-flop outputs.
35. The system of claim 34, further comprising a data interface coupled to the data compare circuit and configured to provide at least one of maximum and minimum period-to-period jitter.
36. The system of claim 34, further comprising a data interface coupled to said data compare circuit and configured to provide at least one of maximum and minimum cycle-to-cycle jitter.
37. The system of claim 34, further comprising a data interface coupled to said data compare circuit and configured to provide cycle-to-cycle jitter for each cycle of said clock signal.
38. A system for measuring skew between a plurality of signals, comprising:
a first and a second relative phase encoder, each said first and said second relative phase encoder including a delay chain and flip-flops, each said delay chain having a plurality of tap nodes respectively connected to flip-flop delay inputs of said flip-flops, each said delay chain for sampling a respective input signal of said plurality of signals, each said first and said second relative phase encoder configured to receive a clock signal to clock said flip-flops, said first and said second relative phase encoder each having an encoder respectively coupled to outputs of said flip-flops, each said encoder configured to respectively provide encoded phase for each of said plurality of signals relative to said clock signal; and
a data compare circuit coupled to receive each said encoded phase and configured to compare each said encoded phase with each other.
39. The system of claim 38, wherein said data compare circuit comprises a subtractor operably coupled to provide a difference representing the skew.
40. The system of claim 38, further comprising a validity check circuit respectively coupled to said first and said second relative phase encoder to check validity of said outputs.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of coating for protecting a product with a nanocomposite coating adapted to protect the product from being corroded and damaged by some exterior chemicals, the method comprising the steps of:
preparing the nanocomposite coating which is formed by mixing a nanometer inorganic oxide gel made by a sol-gel method, an organic solvent and a nanometer powder together;
coating the nanocomposite coating onto surfaces of the product evenly by way of spraying, dipping or roll-to-rolling; and
subjecting the product coated with the nanocomposite coating to a room temperature or a heating environment lower than 170 degrees centigrade to make the nanocomposite coating dry for forming nanometer protective films on the surfaces of the product so as to protect the product from being corroded and damaged by the exterior chemicals;
wherein the weight percentage of the nanometer inorganic oxide gel, the organic solvent and the nanometer powder in the nanocomposite coating is 22.5\u02dc49.5%, 45\u02dc74.25% and 1\u02dc10% respectively.
2. The method as claimed in claim 1, wherein the nanometer powder is any one of or a mixture of a nanometer metal powder and a nanometer metal-oxide powder.
3. The method as claimed in claim 2, wherein the nanometer metal powder is any one of or a mixture of at least two selected from a nanometer platinum powder, a nanometer copper powder and a nanometer nickel powder.
4. The method as claimed in claim 2, wherein the nanometer metal-oxide powder is any one of or a mixture of at least two selected from a nanometer silicon dioxide powder, a nanometer titanium dioxide powder and a nanometer zirconium dioxide powder.
5. The method as claimed in claim 1, wherein the nanometer powder is processed by a surfactant before being mixed with the nanometer inorganic oxide gel and the organic solvent to form the nanocomposite coating.
6. The method as claimed in claim 5, wherein the surfactant is any one of or a mixture of a sodium dodecylsulphonate and a polyvinyl pyrrolidone.
7. The method as claimed in claim 1, wherein the diameter of the nanometer powder is 5\u02dc100 nm.
8. The method as claimed in claim 1, wherein the nanometer inorganic oxide gel is any one of or a mixture of at least two selected from a nanometer silicon dioxide gel, a nanometer titanium dioxide gel and a nanometer zirconium dioxide gel.
9. The method as claimed in claim 1, wherein the organic solvent is any one of or a mixture of an ethanol solvent and an isopropanol solvent.

1. A method for preventing telephony fraud, the method comprising:
maintaining a centralized database resident within a domestic region, the database being configured to store a block call list that includes a terminating number corresponding to an international region, wherein the database is accessible by all telephony switches within a first telephony network; and
receiving a database query initiated by one of the telephony switches in response to a collect call placed to a destination number terminated via a second telephony network within the international region, wherein the collect call is blocked if the database query results in a response indicating the destination number is within the block call list.
2. A method according to claim 1, wherein the first telephony network is maintained by a domestic service provider, and the second telephony network is maintained by an international service provider.
3. A method according to claim 2, wherein the block call list is updated based on call records of the second telephony network.
4. A method according to claim 2, wherein the second telephony network includes a cellular network, and the destination number corresponds to a cellular phone.
5. A method according to claim 1, wherein the terminating number in the block call list includes a wildcard character.
6. A method according to claim 1, the method further comprising:
determining whether the block call list has any entries; and
comparing the destination number with entries within the block call list if the list has at least one entry.
7. A method according to claim 1, wherein the block call list includes entries that exhibit a fraud-to-revenue ratio exceeding a predetermined threshold or that correspond to accounts that have overdue balances.
8. A method according to claim 1, wherein a record within the database includes the block call list, a field specifying a country code of the international region, and a field specifying a category of billing product, the category including collect calls.
9. A system for preventing telephony fraud, the system comprising:
a centralized database resident within a domestic region, the database being configured to store a block call list that includes a terminating number corresponding to an international region, wherein the database is accessible by all telephony switches within a first telephony network,
wherein a database query is initiated by one of the telephony switches in response to a collect call placed to a destination number terminated via a second telephony network within the international region, wherein the collect call is blocked if the database query indicates the destination number is within the block call list.
10. A system according to claim 9, wherein the first telephony network is maintained by a domestic service provider, and the second telephony network is maintained by an international service provider.
11. A system according to claim 10, wherein the block call list is updated based on call records of the second telephony network.
12. A system according to claim 10, wherein the second telephony network includes a cellular network, and the destination number corresponds to a cellular phone.
13. A system according to claim 9, wherein the terminating number in the block call list includes a wildcard character.
14. A system according to claim 9, wherein a determination is made whether the block call list has any entries before comparing the destination number with entries within the block call list.
15. A system according to claim 9, wherein the block call list includes entries that exhibit a fraud-to-revenue ratio exceeding a predetermined threshold or that correspond to accounts that have overdue balances.
16. A system according to claim 9, wherein a record within the database includes the block call list, a field specifying a country code of the international region, and a field specifying a category of billing product, the category including collect calls.
17. A system for preventing telephony fraud, the system comprising:
a bridging switch configured to access a centralized database, the centralized database being resident within a domestic region and being configured to store a block call list that includes a terminating number corresponding to an international region; and
an interexchange switch in communication with the bridging switch and configured to process a collect call placed to a destination number corresponding to a device served by a first service provider, wherein the interexchange switch and the bridging switch are operated by a second service provider, the collect call initiating a database query to the database, wherein the collect call is blocked if the database query results in a response indicating the destination number is within the block call list.
18. A system according to claim 17, wherein the first service provider is an international service provider, and the second service provider is a domestic service provider.
19. A system according to claim 18, wherein the block call list is updated based on call records of the first service provider.
20. A system according to claim 18, wherein the device is a cellular phone.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A polarizing liquid crystal panel comprising:
a first substrate comprising a plastic substrate, a first electrode on the plastic substrate, and a first alignment layer on the first electrode;
a second substrate comprising a base substrate which opposes the first substrate, a second electrode on the base substrate, and a second alignment layer on the second electrode; and
a liquid crystal layer between the first and second substrates, wherein the liquid crystal layer polarizes a light and uses an electric field between the first and second electrodes.
2. The polarizing liquid crystal panel of claim 1, wherein the first substrate further comprises a buffer layer between the plastic substrate and the first electrode, wherein the buffer layer protects the plastic substrate.
3. The polarizing liquid crystal panel of claim 1, wherein one of the first and second electrodes comprises a patterned electrode including a plurality of sub-electrodes.
4. The polarizing liquid crystal panel of claim 1,
wherein the first electrode comprises a patternless electrode on an entire of the plastic substrate, and
wherein the second electrode comprises a patterned electrode including a plurality of sub-electrodes.
5. The polarizing liquid crystal panel of claim 1, wherein the base substrate comprises a plastic substrate.
6. The polarizing liquid crystal panel of claim 5, wherein the second substrate further comprises:
a moisture resistant layer on one of a first surface of the base substrate including the second electrode thereon, and a second surface which opposes the first surface, the moisture resistant layer including an organic material.
7. The polarizing liquid crystal panel of claim 5, wherein the second substrate further comprises a buffer layer between the base substrate and the second electrode, wherein the buffer layer protects the base substrate.
8. The polarizing liquid crystal panel of claim 1, wherein the base substrate comprises a glass substrate.
9. The polarizing liquid crystal panel of claim 1, wherein the plastic substrate comprises one of polycarbonate, triacetiyl cellulose and cyclic olefin copolymer.
10. A display apparatus comprising:
a display panel which displays a stereoscopic image; and
a polarizing liquid crystal panel on the display panel and comprising;
a first substrate comprising a plastic substrate, a first electrode on the plastic substrate, and a first alignment layer on the first electrode;
a second substrate comprising a base substrate which opposes the first substrate, a second electrode on the base substrate, and a second alignment layer; and
a liquid crystal layer between the first and second substrates, wherein the liquid crystal layer polarizes a light which passes through the display panel.
11. The display apparatus of claim 10,
wherein the first substrate is on the display panel, and
wherein the base substrate comprises a plastic substrate.
12. The display apparatus of claim 11, wherein the second substrate further comprises a moisture resistant layer including an organic material.
13. The display apparatus of claim 10,
wherein the first substrate is on the display panel, and
wherein the base substrate comprises a glass substrate.
14. The display apparatus of claim 10,
wherein the second substrate is on the display panel, and
wherein the base substrate comprises a glass substrate.
15. The display apparatus of claim 14, wherein the first substrate further comprises a moisture resistant layer including an organic material.
16. The display apparatus of claim 10, wherein one of the first and second electrodes comprises a patterned electrode, and the other comprises a patternless electrode.
17. The display apparatus of claim 10,
wherein the first electrode comprises a patternless electrode on an entire of the plastic substrate, and
wherein the second electrode comprises a patterned electrode including a plurality of sub-electrodes.
18. The display apparatus of claim 10, further comprising a touch screen member on the polarizing liquid crystal panel.
19. The display apparatus of claim 10, further comprising polarizing glasses which receive an image which passes through the polarizing liquid crystal panel, wherein the polarizing glasses part includes a left eye part and a right eye part having different polarizing properties from each other.
20. A display apparatus comprising:
a display panel which displays a stereoscopic image;
a polarizing member on the display panel and comprising:
a first surface which faces the display panel,
a first electrode on a second surface opposite surface to the first surface, and
a first alignment layer on the first electrode;

an opposite substrate comprising a plastic substrate which faces the polarizing member, a second electrode on the plastic substrate, a second alignment layer on the second electrode, and a moisture resistant layer including an organic material; and
a liquid crystal layer between the polarizing member and the opposite substrate.