1. A circuit comprises:
a clock circuit coupled to produce a digital clock signal;
a processing module coupled to:
determine whether a harmonic component of the digital clock signal having a nominal digital clock rate interferes with operation of at least a portion of the circuit;
when the harmonic component of the digital clock signal interferes with the operation of the at least a portion of the circuit, provide an indication to the clock circuit to adjust rate of the digital clock signal from the nominal digital clock rate to an adjusted digital clock rate, wherein harmonic components of the digital clock signal having the adjusted digital clock rate do not interfere with the operation of the at least a portion of the circuit; and
processing circuitry coupled to:
receive data at the nominal digital clock rate; and
process, at the adjusted digital clock rate, the data to produce processed data having a rate corresponding to the nominal digital clock rate.
2. The circuit of claim 1, wherein the processing module further functions to:
determine that the harmonic component of the digital clock signal interferes with the operation of the at least a portion of the circuit by determining whether the harmonic component of the digital clock signal is within a frequency passband; and
when the harmonic component of the digital clock signal is within the frequency passband, provide the indication to the clock circuit to adjust the rate of the digital clock signal from the nominal digital clock rate to the adjusted digital clock rate, wherein harmonic components of the digital clock signal having the adjusted digital clock rate are outside of the frequency passband.
3. The circuit of claim 1, wherein the processing circuit is further coupled to:
interpolate, at an interpolation rate, the processed data to produce interpolated processed data having a rate corresponding to the interpolation rate.
4. The circuit of claim 3 comprises:
the interpolation rate corresponding to the adjusted digital clock rate.
5. The circuit of claim 3, wherein the processing circuitry comprises:
a digital modulation module coupled to modulate, at the adjusted digital clock rate, the data at the nominal digital clock rate to produce modulated data having a rate corresponding to the nominal digital clock rate;
an interpolation module coupled to interpolate, at the interpolation rate, the modulated data to produce interpolated modulated data having a rate corresponding to the interpolation rate; and
a digital to analog conversion module coupled to convert the interpolated modulated data into analog modulated data, wherein a digital portion of the digital to analog conversion module is clocked in accordance with the interpolation rate.
6. The circuit of claim 5, wherein the digital modulation module comprises:
digital modulation circuitry coupled to modulate, at the adjusted digital clock rate, the data to produce modulated data having a rate corresponding to the adjusted digital clock rate; and
rate adjusting circuitry coupled to convert the modulated data having the rate corresponding to the adjusted digital clock rate into the modulated data having the nominal digital clock rate.
7. The circuit of claim 5 further comprises:
an analog filter module coupled to filter the analog modulated data to produce filtered modulated data;
an up-conversion module coupled to convert the filtered modulated data into an up-converted signal;
a power amplifier module coupled to amplify the up-converted signal to produce a transmit radio frequency (RF) signal having a carrier frequency within the frequency passband; and
an RF filtering module coupled to filter the transmit RF signal to produce an outbound RF signal.
8. The circuit of claim 1 comprises:
the clock circuit coupled to produce a second digital clock signal; and
the processing module coupled to:
determine whether a harmonic component of the second digital clock signal having a second nominal digital clock rate interferes with operation of at least a portion of the circuit; and
when the harmonic component of the second digital clock signal interferes with operation of at least a portion of the circuit, provide an indication to the clock circuit to adjust rate of the second digital clock signal from the second nominal digital clock rate to an interpolation rate, wherein harmonic components of the second digital clock signal having the interpolation rate do not interfere with the operation of the at least a portion of the circuit.
9. The circuit of claim 1 comprises:
the adjusted digital clock rate is at a higher rate than the nominal digital clock rate.
10. The circuit of claim 1 comprises:
an integrated circuit (IC) substrate that supports the clock circuit, the processing module, and the processing circuit.
11. A circuit comprises:
a clock circuit coupled to produce a digital clock signal;
a processing module coupled to:
determine whether a harmonic component of the digital clock signal having a nominal digital clock rate interferes with operation of at least a portion of the circuit;
when the harmonic component of the digital clock signal interferes with the operation of the at least a portion of the circuit, provide an indication to the clock circuit to adjust rate of the digital clock signal from the nominal digital clock rate to an adjusted digital clock rate, wherein harmonic components of the digital clock signal having the adjusted digital clock rate do not interfere with the operation of the at least a portion of the circuit; and
processing circuitry coupled to:
receive data; and
process, in accordance with the adjusted digital clock rate, the data to produce processed data having a rate corresponding to the nominal digital clock rate.
12. The circuit of claim 11, wherein the processing module further functions to:
determine that the harmonic component of the digital clock signal interferes with the operation of the at least a portion of the circuit by determining whether the harmonic component of the digital clock signal is within a frequency passband; and
when the harmonic component of the digital clock signal is within the frequency passband, provide the indication to the clock circuit to adjust the rate of the digital clock signal from the nominal digital clock rate to the adjusted digital clock rate, wherein harmonic components of the digital clock signal having the adjusted digital clock rate are outside of the frequency passband.
13. The circuit of claim 11, wherein the processing circuitry is further coupled to:
receive the data at an interpolation rate;
interpolate, in accordance with the interpolation rate, the data to produce interpolated data having a rate corresponding to the nominal digital clock rate; and
process, in accordance with the adjusted digital clock rate, the interpolated data to produce the processed data having a rate corresponding to the nominal digital clock rate.
14. The circuit of claim 13 comprises:
the interpolation rate corresponding to the adjusted digital clock rate.
15. The circuit of claim 13, wherein the processing circuitry comprises:
an analog to digital conversion module coupled to convert analog modulated data into the data at the interpolation rate, wherein a digital portion of the analog to digital conversion module is clocked in accordance with the interpolation rate;
an interpolation module coupled to interpolate, at the interpolation rate, the data at the interpolation rate to produce interpolated modulated data having a rate corresponding to the nominal digital clock rate; and
a digital demodulation module coupled to demodulate, at the adjusted digital clock rate, the interpolated modulated data at the nominal digital clock rate to produce recovered data having a rate corresponding to the nominal digital clock rate.
16. The circuit of claim 15, wherein the digital demodulation module comprises:
digital demodulation circuitry coupled to demodulate, at the adjusted digital clock rate, the interpolated modulated data to produce demodulated data having a rate corresponding to the adjusted digital clock rate; and
rate adjusting circuitry coupled to convert the demodulated data having the rate corresponding to the adjusted digital clock rate into the recovered data having the nominal digital clock rate.
17. The circuit of claim 15, wherein the interpolation module comprises:
sampling circuitry to sample the data at the interpolation rate to produce sampled data; and
rate adjusting circuitry coupled to convert the sampled data into the interpolated modulated data having the rate corresponding to the nominal digital clock rate.
18. The circuit of claim 15 further comprises:
a radio frequency (RF) filtering module coupled to filter an inbound RF signal to produce a filtered inbound RF signal;
a low noise amplifier module coupled to amplify the filtered inbound RF signal to produce an amplified inbound RF signal having a carrier frequency within the frequency passband;
an down-conversion module coupled to convert the amplified inbound RF signal into modulated data; and
an analog filter module coupled to filter the modulated data to produce the analog modulated data.
19. The circuit of claim 11 comprises:
the clock circuit coupled to produce a second digital clock signal; and
the processing module coupled to:
determine whether a harmonic component of the second digital clock signal having a second nominal digital clock rate interferes with the operation of the at least a portion of the circuit; and
when the harmonic component of the second digital clock signal interferes with the operation of the at least a portion of the circuit, provide an indication to the clock circuit to adjust rate of the second digital clock signal from the second nominal digital clock rate to an interpolation rate, wherein harmonic components of the second digital clock signal having the interpolation rate do not interfere with the operation of the at least a portion of the circuit.
20. The circuit of claim 11 comprises:
an integrated circuit (IC) substrate that supports the clock circuit, the processing module, and the processing circuit.
21. A radio frequency circuit comprises:
a clock circuit coupled to produce a digital clock signal;
a processing module coupled to:
determine whether a harmonic component of the digital clock signal having a nominal digital clock rate is within the frequency passband;
when the harmonic component of the digital clock signal is within the frequency passband, provide an indication to the clock circuit to adjust rate of the digital clock signal from the nominal digital clock rate to an adjusted digital clock rate, wherein harmonic components of the digital clock signal having the adjusted digital clock rate are outside of the frequency passband;
a receiver section coupled to convert an inbound radio frequency (RF) signal into an analog inbound symbol stream;
an analog to digital conversion module coupled to convert the analog inbound symbol stream into an inbound symbol stream at the interpolation rate, wherein a digital portion of the analog to digital conversion module is clocked in accordance with an interpolation rate; and
a baseband processing module coupled to:
interpolate, in accordance with an interpolation rate, the inbound symbol stream to produce interpolated inbound data having a rate corresponding to the nominal digital clock rate; and
demodulate, in accordance with the adjusted digital clock rate, the interpolated inbound data at the nominal digital clock rate to produce inbound data having a rate corresponding to the nominal digital clock rate.
22. The radio frequency circuit of claim 21 comprises:
the interpolation rate corresponding to the adjusted digital clock rate.
23. The radio frequency circuit of claim 21 comprises:
the clock circuit coupled to produce a second digital clock signal; and
the processing module coupled to:
determine whether a harmonic component of the second digital clock signal having a second nominal digital clock rate is within the frequency passband; and
when the harmonic component of the second digital clock signal is within the frequency passband, provide an indication to the clock circuit to adjust rate of the second digital clock signal from the second nominal digital clock rate to the interpolation rate, wherein harmonic components of the second digital clock signal having the interpolation rate are outside of the frequency passband.
24. The radio frequency circuit of claim 21, wherein the baseband processing module further functions to demodulate, at the adjusted digital clock rate, the interpolated inbound data at the nominal digital clock rate by:
demodulating, at the adjusted digital clock rate, the interpolated inbound data to produce demodulated inbound data having a rate corresponding to the adjusted digital clock rate; and
converting the demodulated inbound data having the rate corresponding into the inbound data having a rate corresponding to the nominal digital clock rate.
25. The radio frequency circuit of claim 21 comprises:
the adjusted digital clock rate is at a higher rate than the nominal digital clock rate.
26. A radio frequency circuit comprises:
a clock circuit coupled to produce a digital clock signal;
a processing module coupled to:
determine whether a harmonic component of the digital clock signal having a nominal digital clock rate is within the frequency passband;
when the harmonic component of the digital clock signal is within the frequency passband, provide an indication to the clock circuit to adjust rate of the digital clock signal from the nominal digital clock rate to an adjusted digital clock rate, wherein harmonic components of the digital clock signal having the adjusted digital clock rate are outside of the frequency passband;
a transmitter section coupled to convert an analog outbound symbol stream into an outbound RF signal, wherein at least one of the inbound RF signal and the outbound RF signal having a carrier frequency within the frequency passband;
a digital to analog conversion module coupled to convert an outbound symbol stream into the analog outbound symbol stream, wherein a digital portion of the digital to analog conversion module is clocked in accordance with the interpolation rate; and
a baseband processing module coupled to:
modulate, in accordance with the adjusted digital clock rate, outbound data at the nominal digital clock rate to produce modulated outbound data having a rate corresponding to the nominal digital clock rate;
interpolate, in accordance with the interpolation rate, the modulated outbound data to produce the outbound symbol stream having a rate corresponding to the interpolation rate.
27. The radio frequency circuit of claim 26 comprises:
the interpolation rate corresponding to the adjusted digital clock rate.
28. The radio frequency circuit of claim 26 comprises:
the clock circuit coupled to produce a second digital clock signal; and
the processing module coupled to:
determine whether a harmonic component of the second digital clock signal having a second nominal digital clock rate is within the frequency passband; and
when the harmonic component of the second digital clock signal is within the frequency passband, provide an indication to the clock circuit to adjust rate of the second digital clock signal from the second nominal digital clock rate to the interpolation rate, wherein harmonic components of the second digital clock signal having the interpolation rate are outside of the frequency passband.
29. The radio frequency circuit of claim 26, wherein the baseband processing module further functions to modulate, at the adjusted digital clock rate, the outbound data at the nominal digital clock rate by:
modulating, at the adjusted digital clock rate, the outbound data to produce modulated data having a rate corresponding to the adjusted digital clock rate; and
converting the outbound data having the rate corresponding to the adjusted digital clock rate to the modulated outbound data having a rate corresponding to the nominal digital clock rate.
30. The radio frequency circuit of claim 26 comprises:
the adjusted digital clock rate is at a higher rate than the nominal digital clock rate.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A process for manufacturing an analog transistor comprising:
providing a doped well;
forming a screen layer that contacts and overlies at least a portion of the doped well;
forming an epitaxial undoped channel layer above the screen layer, and the undoped channel not being subjected to contaminating threshold voltage implants or halo implants;
forming a gate dielectric and gate electrode above the undoped channel and positioned between a source and a drain, the source and drain configured to respond to an analog signal; and
maintaining process conditions so that a portion of the undoped channel adjacent to the gate dielectric remains undoped in the final analog transistor.
2. The process of claim 1, further comprising the step of forming a threshold voltage setting layer positioned between the substantially undoped channel and the screen layer.
3. The process of claim 2, further comprising the step of counter doping the threshold voltage setting layer with respect to the screen layer.
4. The process of claim 2, further comprising the step of forming an asymmetric threshold voltage setting layer that extends only partially between the source and the drain.
5. The process of claim 4, wherein the threshold voltage setting layer that extends from the source to a position below the substantially undoped channel short of the drain.
6. The process of claim 2, wherein the threshold voltage setting layer is formed by out diffusion from the screen layer into an epitaxially grown layer.
7. The process of claim 2, wherein the threshold voltage setting layer is formed by growing an epitaxial layer on the screen layer and doping the epitaxial layer through either implantation or in-situ doping.
8. The process of claim 2, wherein the threshold voltage setting layer is formed by delta doping to form an offset doped plane.
9. The process of claim 2, wherein the threshold voltage setting layer is formed as part of a blanket layer underlying a plurality of gate dielectrics and gate electrodes.
10. The process of claim 2, further comprising:
forming a dopant migration resistant layer above the threshold voltage setting layer.
11. The process of claim 2, further comprising:
forming a first dopant migration resistant layer above the threshold voltage setting layer;
forming a second dopant migration resistant layer above the threshold voltage setting layer.
12. The process of claim 1, further comprising the steps of:
forming a first channel LDD extending from the source toward the drain; and
forming a second channel LDD extending from the drain toward the source.
13. The process of claim 12, wherein the first channel LDD extends a different distance than the second channel LDD.
14. The process of claim 12, wherein the first channel LDD has a greater depth than the second channel LDD.
15. The process of claim 12, wherein the first channel LDD has a greater dopant density than the second channel LDD.
16. The process of claim 1, further comprising the step of depositing the gate metal of the gate electrode, wherein the gate metal is selected to have a work function intermediate between band edge and midgap.
17. The process of claim 1, further comprising the step forming an electrical tap to the doped well to permit biasing that adjusts threshold voltage.
18. The process of claim 1, wherein the screen layer is formed as part of a blanket layer underlying a plurality of gate dielectrics and gate electrodes.
19. The process of claim 1, wherein the screen layer is formed by epitaxial growth subject to at least one of implantation and in situ doping.
20. The process of claim 1, wherein the screen layer is positioned above the bottom of the source and drain.