1. A method of fabricating a semiconductor device, comprising:
forming a first film with an opening on an insulating layer formed on a semiconductor substrate;
forming a second film on said first film in such a way that said opening is buried;
forming a trench pattern on said second film located in the upper portion of said opening;
forming a via pattern by etching said first film using said trench pattern to expose said insulating layer; and
forming a via hole and an interconnect trench in the upper portion of said via hole in said insulating layer employing said via pattern and said trench pattern,
wherein a width of said via hold depends on a part of said trench pattern and said opening having a larger width than said width of the via hole.
2. The method of claim 1, wherein one side of said trench pattern is between said opening.
3. The method of claim 1, wherein said first film is a multilayer.
4. The method of claim 1, wherein said second film is a multilayer.
5. The method of claim 1, wherein said insulating layer is a multilayer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An interconnect apparatus comprising a transaction buffer mechanism including a plurality of transaction buffers, each transaction buffer being operable to buffer transaction packets of a respective type, and a reserve buffer dynamically assignable to one of the transaction buffers where additional capacity is required by that transaction buffer.
2. The interconnect apparatus of claim 1, wherein one transaction buffer is operable to buffer posted transaction packets.
3. The interconnect apparatus of claim 1, wherein one transaction buffer is operable to buffer non-posted transaction packets.
4. The interconnect apparatus of claim 1, wherein one transaction buffer is operable to buffer completion transaction packets.
5. The interconnect apparatus of claim 1, wherein each transaction buffer has a size insufficient to support streaming of packets, but wherein a combination of the capacity of a transaction buffer and the reserve buffer when assigned thereto is sufficient to support packet streaming.
6. The interconnect apparatus of claim 1, comprising control logic for allocating the reserve buffer to a transaction buffer where additional capacity is required by that transaction buffer.
7. The interconnect apparatus of claim 1, comprising control logic for allocating the reserve buffer to a transaction buffer in response to detecting a packet streaming condition.
8. The interconnect apparatus of claim 1, wherein the control logic is configured to report the allocation of the reserve buffer to a transaction buffer as a release of credit for that transaction buffer.
9. The interconnect apparatus of claim 1, operable under a PCI Express protocol.
10. The interconnect apparatus of claim 1, wherein the interconnect apparatus comprises a switch.
11. The interconnect apparatus of claim 1 in the form of an integrated circuit.
12. A computer system comprising a transaction buffer mechanism including a plurality of transaction buffers, each transaction buffer being operable to buffer transaction packets of a respective type, and a reserve buffer dynamically assignable to one of the transaction buffers where additional capacity is required by that transaction buffer.
13. A method of operating an interconnect apparatus comprising a transaction buffer mechanism including a plurality of transaction buffers, the method comprising each transaction buffer buffering transaction packets of a respective type, and dynamically allocating a reserve buffer to one of the transaction buffers where additional capacity is required by that transaction buffer.
14. The method of claim 13, wherein posted transactions are buffered in a first transaction buffer, non-posted transaction packets are buffered in a second transaction buffer, and completed transaction packets are buffered in a third transaction buffer.
15. The method of claim 13, wherein each transaction buffer has a size insufficient to support streaming of packets, but wherein a combination of the
capacity of a transaction buffer and the reserve buffer when assigned thereto is sufficient to support packet streaming.
16. The method of claim 13, wherein the reserve buffer is allocated to a transaction buffer in response to detecting a packet streaming condition.
17. The method of claim 13, wherein the allocation of the reserve buffer to a transaction buffer appears to external devices as a release of credit for that transaction buffer.
18. The method of claim 13, operable under a PCI Express protocol.