All The Claims

1. A method of implementing a multiple writer single reader queue in a lock free and a contention free manner, the method comprising:
receiving a plurality of payloads from a plurality of users;
assigning a first payload of the plurality of payloads to a first writer thread of a plurality of writer threads, and assigning a second payload of the plurality of payloads to a second writer thread of the plurality of writer threads;
creating a first writer queue by the first writer thread exclusively owned by the first writer thread, and creating a second writer queue by the second writer thread exclusively owned by the second writer thread;
enqueuing the first payload as a first queue entry, said first queue entry including a first queue entry number, a first writer queue identifier, a first entry type, a first writer reference, wherein the first payload is enqueued into the first writer queue identified by the first writer queue identifier by the first writer thread identified by the first writer reference, and enqueuing the second payload as a second queue entry, said second queue entry including at least one of a second queue entry number, a second writer queue identifier, a second entry type, a second writer reference, wherein the second payload is enqueued into the second writer queue identified by the second writer queue identifier by the second writer thread identified by the second writer reference;
wherein the first and second queue entry numbers are generated by a queue entry counter which generates queue entry numbers in unique and increasing order in atomic fashion;
dequeuing the first queue entry from the first writer queue and the second queue entry from the second writer queue in order of their respective queue entry numbers, and inserting the retrieved first and second queue entries into a sorted queue maintained by a reader thread, the dequeuing and inserting being done by the reader thread and whereby the first and second queue entries are inserted into the sorted queue in order of their respective queue entry numbers;
identifying a queue entry in the sorted queue having the lowest queue entry number;
enqueuing another queue entry into the sorted queue from the writer queue from which the queue entry having the lowest queue entry number was obtained;
dequeuing from the sorted queue the queue entry having the lowest queue entry number for processing by the reader thread; and
processing the dequeued queue entry from the sorted queue.
2. The method as claimed in claim 1, wherein the first and second entry types comprise a variable to store one of a normal entry, a dummy entry and a remove writer entry.
3. The method as claimed in claim 2, wherein the normal entry indicates that one payload of the plurality of payloads is present in the sorted queue, the dummy entry indicates that one payload of the plurality of payloads is absent in the sorted queue and, the remove writer entry indicates that one writer thread of the plurality of writer threads is required to be removed from the sorted queue.
4. The method as recited in claim 2:
wherein the dummy entry serves as a place holder, and includes a queue entry number, an entry type as a dummy entry, and a null payload;
whereby the number of queue entries within the sorted queue is equal to the number of writer queues.
5. The method as claimed in claim 2, further comprising consulting the first writer queue for the presence of a new payload if (i) the entry type is a dummy entry and (ii) the time is appropriate for processing the entry whose entry number is associated with the dummy entry because the entry having an immediately preceding entry number has been processed.
6. The method as claimed in claim 1 and further comprising:
adding one or more writer threads in real time, wherein the one or more writer threads are recognized by the reader thread; and
removing the one or more writer threads in real time.
7. The method as recited in claim 1, further comprising:
processing the first queue entry from the sorted queue;
if there is a third queue entry that has been enqueued into the first writer queue, then retrieving the third queue entry from the sorted queue;
whereby the number of queue entries within the sorted queue is equal to the number of writer queues.
8. The method as recited in claim 1, further comprising:
processing the first queue entry from the sorted queue;
if there is not a third queue entry that has been enqueued into the first writer queue, then inserting a dummy entry into the sorted queue, the dummy entry including the first queue entry number;
whereby the number of queue entries within the sorted queue is equal to the number of writer queues.
9. The method as claimed in claim 1, wherein, responsive to the processing, the first and second writer queues are checked for respective third and fourth queue entries; and
(i) if the respective third and fourth queue entries are present, dequeueing the respective third and fourth queue entries in the sorted order by queue entry number, and inserting the respective third and fourth queue entries into the sorted queue in the sorted order by queue entry number; and
(ii) if either one of the respective third and fourth queue entries are not present, inserting a dummy entry into the sorted queue, the dummy entry representing the respective one of the first and second writer queues and having an entry type designating it a dummy entry;
whereby the number of entries in the sorted queue remains equal to the number of writer queues even if a writer queue contains no queue entries.
10. A computer program product stored on a non-transitory computer-readable medium that when executed by a processor, performs a method of implementing a multiple writer single reader queue in a lock free and a contention free manner, comprising:
receiving a plurality of payloads from a plurality of users;
assigning a first payload of the plurality of payloads to a first writer thread of a plurality of writer threads, and assigning a second payload of the plurality of payloads to a second writer thread of the plurality of writer threads;
creating a first writer queue by the first writer thread exclusively owned by the first writer thread, and creating a second writer queue by the second writer thread exclusively owned by the second writer thread;
enqueuing the first payload as a first queue entry, said first queue entry including a first queue entry number, a first writer queue identifier, a first entry type, a first writer reference, wherein the first payload is enqueued into the first writer queue identified by the first writer queue identifier by the first writer thread identified by the first writer reference, and enqueuing the second payload as a second queue entry, said second queue entry including at least one of a second queue entry number, a second writer queue identifier, a second entry type, a second writer reference, wherein the second payload is enqueued into the second writer queue identified by the second writer queue identifier by the second writer thread identified by the second writer reference;
wherein the first and second queue entry numbers are generated by a queue entry counter which generates queue entry numbers in unique and increasing order in atomic fashion;
dequeuing the first queue entry from the first writer queue and the second queue entry from the second writer queue in order of their respective queue entry numbers, and inserting the retrieved first and second queue entries into a sorted queue maintained by a reader thread, the dequeuing and inserting being done by the reader thread and whereby the first and second queue entries are inserted into the sorted queue in order of their respective queue entry numbers;
identifying a queue entry in the sorted queue having the lowest queue entry number;
enqueuing another queue entry into the sorted queue from the writer queue from which the queue entry having the lowest queue entry number was obtained;
dequeuing from the sorted queue the queue entry having the lowest queue entry number for processing by the reader thread; and
processing the dequeued queue entry from the sorted queue.
11. The computer program product as claimed in claim 10, wherein the entry type comprises a variable to store one of a normal entry, a dummy entry and a remove writer entry.
12. The computer program product as claimed in claim 11, the normal entry indicates that one payload of the plurality of payloads is present in the sorted queue, the dummy entry indicates that one payload of the plurality of payloads is absent in the sorted queue and, the remove writer entry indicates that one writer thread of the plurality of writer threads is required to be removed from the sorted queue.
13. The computer program product as recited in claim 11, wherein the dummy entry serves as a place holder, and includes a queue entry number, an entry type as a dummy entry, and a null payload, whereby the number of queue entries within the sorted queue is equal to the number of writer queues.
14. The computer program product as claimed in claim 11, further comprising consulting the first writer queue for the presence of a new payload if (i) the entry type is a dummy entry and (ii) the time is appropriate for processing the entry whose entry number is associated with the dummy entry because the entry having an immediately preceding entry number has been processed.
15. The computer program product as claimed in claim 10 and further comprising:
adding one or more writer threads in real time, wherein the one or more writer threads are recognized by the reader thread; and
removing the one or more writer threads in real time.
16. The computer program product as recited in claim 10, further comprising:
processing the first queue entry from the sorted queue;
if there is a third queue entry that has been enqueued into the first writer queue, then retrieving the third queue entry from the sorted queue;
whereby the number of queue entries within the sorted queue is equal to the number of writer queues.
17. The computer program product as recited in claim 10, further comprising:
processing the first queue entry from the sorted queue;
if there is not a third queue entry that has been enqueued into the first writer queue, then inserting a dummy entry into the sorted queue, the dummy entry including the first queue entry number;
whereby the number of queue entries within the sorted queue is equal to the number of writer queues.
18. The computer program product as claimed in claim 10, wherein, responsive to the processing, the first and second writer queues are checked for respective third and fourth queue entries; and
(i) if the respective third and fourth queue entries are present, dequeueing the respective third and fourth queue entries in the sorted order by queue entry number, and inserting the respective third and fourth queue entries into the sorted queue in the sorted order by queue entry number; and
(ii) if either one of the respective third and fourth queue entries are not present, inserting a dummy entry into the sorted queue, the dummy entry representing the respective one of the first and second writer queues and having an entry type designating it a dummy entry;
whereby the number of entries in the sorted queue remains equal to the number of writer queues even if a writer queue contains no queue entries.
19. A system implementing a multiple writer single reader queue in a lock free and a contention free manner, the system comprising:
an electronic device for displaying a plurality of payloads;
a memory that stores instructions;
a processor; and
a communication interface in electronic communication with the electronic device and the processor, the processor responsive to the instructions to receive a plurality of payloads from a plurality of users;
assign a first payload of the plurality of payloads to a first writer thread of a plurality of writer threads, and assign a second payload of the plurality of payloads to a second writer thread of the plurality of writer threads;
create a first writer queue by the first writer thread exclusively owned by the first writer thread, and create a second writer queue by the second writer thread exclusively owned by the second writer thread;
enqueue the first payload as a first queue entry, said first queue entry including a first queue entry number, a first writer queue identifier, a first entry type, a first writer reference, wherein the first payload is enqueued into the first writer queue identified by the first writer queue identifier by the first writer thread identified by the first writer reference, and enqueue the second payload as a second queue entry, said second queue entry including at least one of a second queue entry number, a second writer queue identifier, a second entry type, a second writer reference, and wherein the second payload is enqueued into the second writer queue identified by the second writer queue identifier by the second writer thread identified by the second writer reference;
wherein the first and second queue entry numbers are generated by a queue entry counter which generates queue entry numbers in unique and increasing order in atomic fashion;
dequeue the first queue entry from the first writer queue and the second queue entry from the second writer queue in order of their respective queue entry numbers, and inserting the retrieved first and second queue entries into a sorted queue maintained by a reader thread, the dequeuing and inserting being done by the reader thread and whereby the first and second queue entries are inserted into the sorted queue in order of their respective queue entry numbers;
identify a queue entry in the sorted queue having the lowest queue entry number;
enqueue another queue entry into the sorted queue from the writer queue from which the queue entry having the lowest queue entry number was obtained;
dequeue from the sorted queue the queue entry having the lowest queue entry number for processing by the reader thread; and
process the dequeued queue entry from the sorted queue.
20. The system as claimed in claim 19, wherein a processor is further responsive to the instructions to:
create the plurality of writer threads; and
create the reader thread.
21. The system as claimed in claim 19, wherein a processor is further responsive to the instructions to:
add one or more writer threads in real time; and
remove the one or more writer threads in real time.
22. The system as recited in claim 19, wherein the processor is further responsive to the instructions:
to process the first queue entry from the sorted queue; and
if there is a third queue entry that has been enqueued into the first writer queue, then to retrieve the third queue entry from the sorted queue;
whereby the number of queue entries within the sorted queue is equal to the number of writer queues.
23. The system as recited in claim 19, wherein the processor is further responsive to the instructions:
to process the first queue entry from the sorted queue;
if there is not a third queue entry that has been enqueued into the first writer queue, then to insert a dummy entry into the sorted queue, the dummy entry including the first queue entry number;
whereby the number of queue entries within the sorted queue is equal to the number of writer queues.
24. The system as claimed in claim 19, wherein, responsive to the processing, the first and second writer queues are checked for respective third and fourth queue entries; and
(i) if the respective third and fourth queue entries are present, dequeueing the respective third and fourth queue entries in the sorted order by queue entry number, and inserting the respective third and fourth queue entries into the sorted queue in the sorted order by queue entry number; and
(ii) if either one of the respective third and fourth queue entries are not present, inserting a dummy entry into the sorted queue, the dummy entry representing the respective one of the first and second writer queues and having an entry type designating it a dummy entry;
whereby the number of entries in the sorted queue remains equal to the number of writer queues even if a writer queue contains no queue entries.
25. The system as claimed in claim 19, wherein the first and second entry types comprise a variable to store one of a normal entry, a dummy entry and a remove writer entry.
26. The system as claimed in claim 25, wherein the processor is further responsive to the instructions to consult the first writer queue for the presence of a new payload if (i) the entry type is a dummy entry and (ii) the time is appropriate for processing the entry whose entry number is associated with the dummy entry because the entry having an immediately preceding entry number has been processed.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for arranging a packet radio service in a wireless telecommunication system comprising at least one mobile station, the method comprising:
activating in the mobile station at least one packet data context for packet-switched data transmission of an application in the mobile station,
setting a busy condition automatically for the packet data context in the mobile station for suspension situations,
requesting suspension of the packet data context, and
preventing in the mobile station the packet data context from being suspended in response to the packet data context suspension request being received from outside the application.
2. The method of claim 1, wherein the busy condition is set automatically when activating the packet data context.
3. The method of claim 1, wherein the busy condition is set automatically only for certain predetermined applications.
4. The method of claim 1, wherein the busy condition is set at the request of the application utilizing the packet data context.
5. The method of claim 1, wherein a synchronization session is arranged using the packet data context,
the stage of synchronization is checked in response to the request to suspend the synchronization session or the packet data context, and
the synchronization session and the packet data context are prevented from being suspended in response to the synchronization session having reached a predetermined threshold stage.
6. The method of claim 1, wherein the request to suspend the packet data context is initiated by a user.
7. The method of claim 1, wherein the request to suspend the packet data context is caused by an incoming circuit-switched call to the mobile station.
8. The method of claim 7, wherein the circuit-switched call is diverted to another number.
9. The method of claim 7, wherein the circuit-switched call is diverted to a voice message system.
10. The method of claim 7, wherein caller identification is determined, and
the call is rejected.
11. The method of claim 10, wherein the circuit-switched call is diverted to another number.
12. The method of claim 10, wherein the circuit-switched call is diverted to a voice message system.
13. A mobile station comprising:
means for activating at least one packet data context for packet-switched data transmission of an application in the mobile station,
means for setting a busy condition automatically for the packet data context in the mobile station for suspension situations,
means for receiving a request to suspend the packet data context, and
means for preventing the packet data context from being suspended in response to such a busy condition being set.
14. The mobile station of claim 13, wherein the mobile station further comprises
means for setting a busy condition at the request of the application utilizing the packet data context.
15. The mobile station of claim 13, wherein the mobile station further comprises
means for receiving a setup message of an incoming call,
means for determining caller identification and presenting it to a user, and
means for rejecting the call in response to the busy condition being set.
16. The mobile station of claim 13, wherein the mobile station further comprises
means for arranging a synchronization session, using the packet data context,
means for checking the stage of synchronization in response to the request to suspend the synchronization session or the packet data context, and
means for preventing the synchronization session and the packet data context from being suspended in response to the synchronization session having reached a predetermined threshold stage.

Having thus described the preferred embodiments, what is claimed is:

1. A hand mitt comprising:
first and second side members having first and second peripheries, first and second inner faces and first and second outer faces, respectively, wherein a portion of said first periphery is interconnected with a corresponding portion of said second periphery with said first and second inner faces arranged in opposed facing relation and said first and second outer faces exposed and presenting soft, non-abrasive surfaces;
a hand-receiving recess defined between said respective inner faces and an open mouth providing access to said hand-receiving recess defined between a portion of said first periphery that is unconnected to a portion of said second periphery, said recess defined to include an innermost region located opposite said mouth that converges to a point moving in a direction away from said mouth, said innermost region adapted for receipt of a middle finger of a user’s hand inserted into said recess through said mouth;
a sharply pointed distal end defined by said first and second outer faces, said sharply pointed distal end overlying the converging innermost region of said recess.
2. The hand mitt as set forth in claim 1, wherein said first and second peripheries of said first and second side members define a pentagonal shape and are arranged relative to each other so that said hand mitt, itself, defines an overall pentagonal shape, wherein said sharply pointed distal end of said mitt is defined by a convergence of two linear peripheral edges of said overall pentagonal shape.
3. The hand mitt as set forth in claim 2, wherein said two linear peripheral edges converge at an angle of not more than 135.
4. The hand mitt as set forth in claim 3, wherein said two linear peripheral edges converge at an angle of not more than 110.
5. The hand mitt as set forth in claim 3, wherein said recess is sized to accommodate a user’s entire hand.
6. The hand mitt as set forth in claim 3, wherein said recess is sized to accommodate only four fingers of a user’s hand.
7. The hand mitt as set forth in claim 5, further comprising:
an elastic cuff adjacent and surrounding the mouth of the recess for closely encircling a users wrist when the users hand is placed in the recess.
8. The hand mitt as set forth in claim 1, wherein at least one of said first and second outer faces is impregnated with one of a wax and a cleaning compound.
9. The hand mitt as set forth in claim 1, wherein said first and second side members are defined as a one-piece construction that is folded upon itself.
10. The hand mitt as set forth in claim 1, wherein said first and second side members are each defined from a laminate comprising a first layer of soft absorbent material and a second layer comprising one of foam and a rubberized material, wherein said outer face of each of said first and second side members is defined by said first layer of said laminate and said inner face of each of said first and second side members is defined by said second layer of said laminate.
11. The hand mitt as set forth in claim 10, wherein said laminate comprises a barrier layer between said first and second layers.
12. A device for cleaning or polishing comprising:
a first hand mitt comprising a first exposed surface;
a second hand mitt comprising a second exposed surface;
a flexible strip extending between and interconnecting said first and second hand mitts, said flexible strip defining a third exposed surface.
13. The device as set forth in claim 12, wherein said first, second and third exposed surfaces are defined by a single one-piece member.
14. The device as set forth in claim 12, wherein at least one of said first and second exposed surfaces is impregnated with one of a wax and a polishing compound.
15. The device as set forth in claim 12, wherein each of said first and second mitts defines a pointed distal tip.
16. The device as set forth in claim 15, wherein said pointed distal tip of each of said first and second mitts is defined by linear edges that converge at an angle of not more than 135.
17. The device as set forth in claim 16 wherein each of said first and second mitts is pentagonal in shape and defines a hand-receiving recess having an innermost region adapted for receipt of a user’s middle finger that underlies said pointed distal tip.
18. A method a manufacturing a mitt comprising:
forming a one-piece blank defining first and second pentagonally shaped portions separated by a common edge region;
folding said one-piece blank upon itself at said common edge region so that said first and second pentagonally shaped portions are aligned with each other and together define a mitt having first, second, third, fourth and fifth peripheral edges, wherein said first peripheral edge is defined by said common edge region where said blank is folded; and,
joining said first and second pentagonally shaped portions along said second, third and fourth peripheral edges so that a recess is defined between said first and second pentagonally shaped portions and so that said fifth peripheral edge defines a mouth to said recess, said recess adapted for receipt of at least a portion of a user’s hand.
19. The method as set forth in claim 18, further comprising:
impregnating an exposed outer face of said mitt with one of a wax and a polishing compound.
20. The method as set forth in claim 18, wherein said step of joining said first and second pentagonally shaped portions along said second, third and fourth peripheral edges comprises one of glueing, sewing and welding.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A field effect transistor comprising:
a first semiconductor region of a first conduction type, on which a channel region is formed;
a gate electrode formed on the channel region of the first semiconductor region with a gate insulating film being formed between the gate electrode and the channel region;
source and drain electrodes formed on the first semiconductor region with the channel region of the first semiconductor region being interposed between the source and drain electrodes in a channel length direction;
second semiconductor regions of a second conduction type formed between each of the source and drain electrodes and the channel region, each of the second semiconductor regions forming an extension region of each of the source and drain electrodes; and
third semiconductor regions of the second conduction type formed between each of the source and drain electrodes and each of the first semiconductor region and the second semiconductor region, each of the third semiconductor regions formed by segregation from the source and drain electrodes and having an impurity concentration higher than that of the second semiconductor regions.
2. The field effect transistor according to claim 1, wherein the first semiconductor region is formed of a semiconductor layer formed on a buried insulating film.
3. The field effect transistor according to claim 2, wherein each part of the third semiconductor regions is in direct contact with the buried insulating film.
4. The field effect transistor according to claim 2, wherein a part of each of the source and drain electrodes is in direct contact with the buried insulating film.
5. The field effect transistor according to claim 1, further comprising fourth semiconductor regions of the first conduction type formed between the first semiconductor region and the second semiconductor regions, and having an impurity concentration higher than that of the first semiconductor region.
6. The field effect transistor according to claim 1, further comprising fifth semiconductor regions of the second conduction type formed between a bottom part of the third semiconductor regions and the first semiconductor region.
7. The field effect transistor according to claim 1, wherein the gate electrode being made of Ni silicide and each of the source and drain electrodes being made of Co silicide.
8. A method of manufacturing a field effect transistor, the method comprising:
forming a gate electrode on a part of a first semiconductor region of a first conduction type with a gate insulating film interposed between the gate electrode and the part of the first semiconductor region;
forming second semiconductor regions of a second conduction type on the first semiconductor region with the gate electrode arranged between the second semiconductor regions by ion-implanting an impurity using the gate electrode as a mask, the second semiconductor regions forming source and drain extension regions, respectively;
forming sidewall insulating films on opposite side surfaces of the gate electrode after formation of the second semiconductor regions;
ion-implanting an impurity to the first semiconductor region using the gate electrode and the sidewall insulating films as a mask to form ion-implanted parts;
forming source and drain electrodes by siliciding selectively the first semiconductor region to an area deeper than the ion-implanted part; and
forming third semiconductor regions of the second conduction type having an impurity concentration higher than that of the second semiconductor regions, in an interface between each of the source and drain electrodes and each of the first semiconductor region and the second semiconductor regions, by segregation from the source and drain electrodes.
9. The manufacturing method according claim 8, further comprising: forming fourth semiconductor regions of the first conduction type having an impurity concentration higher than that of the first semiconductor region, at a position deeper than that of the second semiconductor regions, by ion-implanting a different impurity from that used to form the second impurity region in the first semiconductor region using the gate electrode as a mask immediately before or after formation of the second semiconductor regions.
10. The manufacturing method according claim 8, wherein a semiconductor layer formed on a buried insulating film is used as the first semiconductor region.
11. The manufacturing method according claim 10, wherein each part of the third semiconductor layers is formed between each of the source and drain electrodes and the buried insulating film by carrying out the siliciding for forming the source and drain electrodes until immediately before contacting the buried insulating film.
12. The manufacturing method according claim 10, wherein the siliciding for forming the source and drain electrodes is carried out until contacting the buried insulating film.
13. A field effect transistor comprising:
a first semiconductor region of a first conduction type on which a channel region is formed;
a gate electrode formed on the channel region of the first semiconductor region with a gate insulating film interposed between the gate electrode and the channel region;
source and drain electrodes formed on the first semiconductor region with the channel region of the first semiconductor region being interposed between the source and drain electrodes in a channel length direction, the source and drain electrodes being formed of a metal silicide; and
impurity segregation regions of a second conduction type formed between the first semiconductor region and each of the source and drain electrodes, the impurity segregations region being formed by segregation of the impurity into the metal silicide.
14. The field effect transistor according to claim 13, further comprising second semiconductor regions of a second conduction type formed between each of the source and drain electrodes and the first semiconductor region.
15. The field effect transistor according to claim 13, wherein the first semiconductor region is formed of a semiconductor layer formed on a buried insulating film.
16. The field effect transistor according to claim 15, wherein each part of the impurity segregation regions is in direct contact with the buried insulating film.
17. The field effect transistor according to claim 13, further comprising third semiconductor regions of the first conduction type formed between the impurity segregation regions and the first semiconductor region, and having an impurity concentration higher than that of the first semiconductor region.
18. The field effect transistor according to claim 13, wherein the gate electrode being made of Ni silicide and each of the source and drain electrodes being made of Co silicide.
19. A method of manufacturing a field effect transistor, the method comprising:
forming a gate electrode on a part of a first semiconductor region of a first conduction type with a gate insulating film interposed between the gate electrode and the first semiconductor region;
forming sidewall insulating films on opposite sides of the gate electrode;
forming second semiconductor regions of a second conduction type in the first semiconductor region by ion-implanting an impurity to the first semiconductor region using the gate electrode and the sidewall insulating films as a mask;
slimming or removing the sidewall insulating films after the formation of the second semiconductor regions;
adding an impurity of a second conduction type in an area of a surface portion of the first semiconductor region to a level shallower than the second semiconductor regions using the gate electrode as a mask after slimming or removing the sidewall insulating films; and
forming source and drain electrodes by siliciding selectively the surface portion of the first semiconductor region, where the second conduction type impurity is added, and forming segregation regions of the second conduction type between the first semiconductor region and each of the source and drain electrodes by segregation of the impurity into the source and drain electrodes.