All The Claims

1. A personal watercraft comprising:
an engine which is mounted in a body of the watercraft and is equipped with an open-loop water cooling system;
a coolant passage in which water for cooling the engine flows;
a water flow generator configured to operate in association with the engine to generate a water flow in the coolant passage; and
a valve unit configured to restrict a flow of the water in the coolant passage.
2. The personal watercraft according to claim 1,
wherein the coolant passage includes an upstream passage located upstream of the engine in the water flow direction and a downstream passage located downstream of the engine; and
wherein the downstream passage is coupled to an oil cooler passage in which the water exchanges heat with an engine oil sent to an oil cooler configured to control a temperature of the engine oil.
3. The personal watercraft according to claim 1,
wherein the coolant passage includes an upstream passage located upstream of the engine in the water flow direction and a plurality of downstream passages located downstream of the engine; and
wherein the valve unit is configured to substantially open and close one of the plurality of downstream passages.
4. The personal watercraft according to claim 3,
wherein the downstream passage which is provided with the valve unit is coupled to a cylinder block passage provided in a cylinder block of the engine;
wherein the upstream passage, and the downstream passage which is not provided with the valve unit are coupled to a cylinder head passage provided in a cylinder head of the engine; and
wherein the cylinder block passage and the cylinder head passage are connected to each other.
5. The personal watercraft according to claim 1,
wherein the valve unit includes a valve bore formed in the coolant passage, a valve plug accommodated in the valve bore; and a downstream seat portion which is located on a downstream side of the valve bore and is configured to seat the valve plug thereon; and
wherein the valve plug is seated on the downstream seat portion to close a passage in the valve bore when a flow rate of the water flowing in the coolant passage is predetermined value or larger, and is away from the downstream seat portion when the flow rate of the water flowing in the coolant passage is smaller than the predetermined value.
6. The personal watercraft according to claim 5,
wherein the valve unit includes an upstream seat portion which is located on an upstream side of the valve bore and is configured to seat the valve plug thereon when a pressure of the water flowing in the coolant passage is smaller than a predetermined value; and
wherein the upstream seat portion is provided with a connecting portion which permits the water to flow in the valve bore with the valve plug seated on the upstream seat portion.
7. The personal watercraft according to claim 6,
wherein the valve plug is configured to drop by a gravitational force to be seated on the upstream seat portion.
8. The personal watercraft according to claim 6,
wherein the valve plug is configured to be subjected to a force applied from a biasing member disposed within the valve bore to be seated on the upstream seat portion.
9. The personal watercraft according to claim 1,
wherein the coolant passage includes an oil cooler passage in which the water exchanges heat with an engine oil sent to an oil cooler configured to control a temperature of an engine oil;
an inlet passage coupled to an inlet port of the oil cooler passage;
an outlet passage coupled to an outlet port of the oil cooler passage; and
a bypass passage configured to directly couple the inlet passage to the outlet passage.
10. A personal watercraft comprising:
an engine which is mounted in a body of the watercraft and is equipped with an open-loop water cooling system;
a coolant passage in which water for cooling the engine flows; and
a water flow generator configured to operate in association with the engine to generate a water flow in the coolant passage;
wherein the coolant passage includes:
an oil cooler passage in which the water exchanges heat with an engine oil sent to an oil cooler configured to control a temperature of the engine oil;
an inlet passage coupled to an inlet port of the oil cooler passage;
an outlet passage coupled to an outlet port of the oil cooler passage; and
a bypass passage configured to directly couple the inlet passage to the outlet passage.
11. The personal watercraft according to claim 10, further comprising:
a bypass valve unit configured to restrict a flow of the water flowing in the bypass passage.
12. The personal watercraft according to claim 11, further comprising:
an actuator configured to drive the bypass valve unit; and
a controller configured to control the actuator;
wherein the controller is configured to control the actuator according to a temperature of the water flowing in the coolant passage.
13. A personal watercraft comprising:
an engine which is mounted in a body of the watercraft and is equipped with an open-loop water cooling system;
a coolant passage in which water for cooling the engine flows; and
a water flow generator configured to operate in association with the engine to generate a water flow in the coolant passage;
wherein the coolant passage includes an upstream passage located upstream of the engine in a water flow direction and a downstream passage located downstream of the engine; and
wherein the downstream passage is coupled to an oil cooler passage in which the water exchanges heat with an engine oil sent to an oil cooler configured to control a temperature of the engine oil.
14. The personal watercraft according to claim 13,
wherein a temperature of the water flowing into the oil cooler passage is higher than the temperature of the engine oil within the oil cooler when an engine speed of the engine is low; and wherein
the temperature of the water flowing into the oil cooler passage is lower than the temperature of the engine oil within the oil cooler when the engine speed of the engine is high.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A memory array comprising:
a plurality of addressable memory locations; and
a circuit to stage the data output from an addressable memory location so that different stages of the data from that addressable memory location are to be output at different times, wherein each stage is a field of the data stored at the memory location.
2. The memory array of claim 1, wherein the different stages are each output during a different clock cycle.
3. The memory array of claim 1, wherein the circuit further comprises a main array control block, and wherein the memory array is to output a first field that is stored at an address at an earlier stage than a second field that is stored at that address if the first field is stored closer to the main array control block than the second field.
4. The memory array of claim 1, wherein the circuit further comprises a main array control block, wherein a plurality of fields having different levels of time criticality are stored at an individual address, and wherein a more time critical field is stored closer to the main array control block than a less time critical field.
5. The memory array of claim 1, wherein the memory array has a plurality of sides, wherein the memory array has an address input port and a plurality of data output ports, and wherein the address input port is on a different side of the memory array than the data output ports.
6. The memory array of claim 1, wherein each addressable memory location comprises a plurality of memory cells, and wherein the memory array further comprises:
an address input port on a first side of the memory array;
a plurality of data output ports on a second side of the memory array; and
a plurality of paths that traverse from the address input port to a one of the memory cells and from that memory cell to a data output port, wherein each path traverses a line between the first side and the second side only once.
7. A memory array comprising:
a first bank comprising a plurality of memory cells;
an input port to receive an address that identifies a memory location, wherein each memory location comprises a plurality of subdivisions, wherein each subdivision comprises a plurality of said first bank memory cells; and
a stage delay circuit to cause each of the memory location subdivisions in the first bank that are identified by a particular address to output data during a different cycle of a clock than any other memory location subdivisions in the first bank that are identified by that address.
8. The memory array of claim 7, wherein the memory array further comprises a main array control block.
9. The memory array of claim 8, wherein memory location subdivisions in the first bank that are identified by a particular address are located at a different distances from the main array control block, and wherein the memory array is to output data stored in a first subdivision that is identified by that address before data stored in a second subdivision that is identified by that address if the first subdivision is located closer to the main array control block than the second subdivision.
10. The memory array of claim 8, wherein the memory array further comprises a second bank coupled to the main array control block, the second bank comprising a plurality of cells, wherein each of the subdivisions in the plurality of memory locations further comprises a plurality of said second bank memory cells, wherein the stage delay circuit is to cause each of the memory location subdivisions in the second bank that are identified by a particular address to output data during a different clock cycle than any other memory location subdivisions in the second bank that are identified by that address.
11. The memory array of claim 10, wherein the main array control block has a plurality of sides, and wherein the first bank is located on a different side of the main array control block than the second bank.
12. The memory array of claim 11, wherein a subdivision of a memory location in the first bank corresponds to a subdivision of that memory location in the second bank, and wherein the memory array outputs data from the corresponding subdivisions in the first bank and second bank during the same clock cycle.
13. The memory array of claim 7, wherein the memory array further comprises a plurality of data output ports, wherein the memory array has a plurality of sides, and wherein the input port and the plurality of data output ports are on opposite sides of the memory array.
14. A memory array comprising:
a main array control block to control the output of data items from the memory array for a plurality of addresses, wherein the main array control block has a plurality of sides;
a first bank of memory cells located on a first side of the main array control block, wherein the first bank is to store a first field of each of said data items; and
a second bank of memory cells located on a different side of the main array control block than the first bank, wherein the second bank is to store a second field of each of said data items.
15. The memory array of claim 14, wherein the memory array is to output the data for an individual address in different stages.
16. The memory array of claim 15, wherein data for a first stage for an individual memory address is output from both the first bank and the second bank.
17. The memory array of claim 14, wherein each data item comprises a plurality of fields, and wherein the memory array is to output a first field for a data item at an earlier stage than a second field for that data item if the first field is located closer to the main array control block than the second field.
18. The memory array of claim 14, wherein the memory array has a plurality of sides, wherein the memory array has an address input port and a plurality of data output ports, and wherein the address input port is on a different side of the memory array than the data output ports.
19. The memory array of claim 14, wherein for each individual address the memory array is to store a plurality of data fields having different levels of time criticality, and wherein a more time critical field is stored closer to the main array control block than a less time critical field.
20. A method comprising:
sending a request to a memory array to read from an address; and
receiving the data item stored at the address from the memory array, wherein the data item is output as a plurality of data fields, wherein the fields are output in stages, and wherein a most time critical field in the data item is output before a less time critical field in the data item.
21. The method of claim 20, wherein the method further comprises:
receiving a first field that is output at a first stage; and
beginning an operation using the first field before a second field is output at a second stage.
22. The method of claim 21, wherein the memory array is a trace cache.
23. The method of claim 21, wherein the memory array includes a main array control block, wherein the first field is stored in the memory array in a first subdivision of cells and the second field is stored in the memory array in second subdivision of cells, and wherein the main array control block is closer to the first subdivision of cells than the second subdivision of cells.

What is claimed is:

1. An input device comprising:
a case including a rib formed therein to extend in a given direction;
circuit boards each including an input part, the circuit boards being temporarily fastened to said case via the rib in process of assembling the input device; and
a support member which is fixed to said case so as to support said circuit boards between the support member and said case after said circuit boards are temporarily fastened to said case.
2. The input device as claimed in claim 1, wherein said circuit boards are slanted with respect to the direction in which the rib extends in being temporarily fastened to said case, and are fixed to said case in slanted states by said support member.
3. The input device as claimed in claim 1, wherein each of two of said circuit boards include first and second end portions on first and second parallel sides, and is temporarily fastened to said case with the first end portion engaging the rib and opposed end portions of the second end portion engaging claw parts formed on the rib.
4. The input device as claimed in claim 2, wherein each of two of said circuit boards include first and second end portions on first and second parallel sides, and is temporarily fastened to said case with the first end portion engaging the rib and opposed end portions of the second end portion engaging claw parts formed on the rib.
5. The input device as claimed in claim 1, wherein one of said circuit boards has holes formed therein, and is temporarily fastened to said case with the holes engaging the rib and a first side of the one of said circuit boards engaging the rib by rotationally moving the one of said circuit boards with the holes serving fulcrums in a direction reverse to the direction in which the rib extends.
6. The input device as claimed in claim 2, wherein one of said circuit boards has holes formed therein, and is temporarily fastened to said case with the holes engaging the rib and a first side of the one of said circuit boards engaging the rib by rotationally moving the one of said circuit boards with the holes serving fulcrums in a direction reverse to the direction in which the rib extends.
7. The input device as claimed in claim 5, wherein:
the one of said circuit boards further includes a second side parallel to the first side thereof; and
the holes are formed close to the second side.
8. The input device as claimed in claim 6, wherein:
the one of said circuit boards further includes a second side parallel to the first side thereof; and
the holes are formed close to the second side.
9. An input device having input parts, comprising:
a control part which outputs data input from one of the input parts after a passage of a given period of time if the one of the input parts is operated within the given period of time, and outputs data input from two or more of the input parts after a passage of a given period of time if the two or more of the input parts are operated within the given period of time.
10. The input device as claimed in claim 9, wherein said control part outputs data from predetermined two of the input parts if the predetermined two of the input parts are operated within a given period of time.
11. The input device as claimed in claim 10, wherein said control part outputs data from an operated one of the input parts to a host computer upon receiving a predetermined command from the host computer.
12. The input device as claimed in claim 9, wherein said control part sets data supplied from a first predetermined one of the input parts in an outputtable state when the input device is activated, and sets data supplied from two or more of the input parts in an outputtable state if a second predetermined one of the input parts is operated.
13. The input device as claimed in claim 12, wherein said control part sets the data supplied from the two or more of the input parts in the outputtable state based on an operation of the second predetermined one of the input parts when a host computer supplies said control part with a command indicating that data from two or more of the input parts is receivable in the host computer.
14. The input device as claimed in claim 9, wherein said control part detects operation frequencies of the input parts so as to adjust data scanning frequencies thereof in accordance with the operation frequencies.
15. The input device as claimed in claim 14, wherein the data scanning frequencies are adjusted to become higher if the operation frequencies become higher and to become lower if the operation frequencies become lower.
16. The input device as claimed in claim 14, wherein a data scanning frequency of one of the input parts in operation is increased for a certain period of time if the one of the input parts has a low operation frequency compared with a rest of the input parts.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of making a transparent panel-form loudspeaker, the loudspeaker comprised of a rectangular transparent panel having a length a and a width b, wherein b is less than or equal to a to be capable of sustaining flexural vibration over an area of the rectangular transparent panel, said method comprising the steps of:
(a) analyzing the distributions of modal parameters, which include natural frequencies, modal amplitudes, mode shapes and phase angles, in the modal analysis of said rectangular transparent panel which is driven by a preselected number of transducers to generate flexural vibration of said rectangular transparent panel and supported peripherally by a flexible suspension device comprised of a continuous corrugated cloth support and several discrete supports, said modal parameters varying according to values of design parameters of said transparent panel-form loudspeaker including a ratio of elastic modulus to density of the material used to fabricate said rectangular transparent panel, a ratio of length to thickness of said rectangular transparent panel, locations of said transducers and discrete supports on a peripheral edge of said rectangular transparent panel;
(b) analyzing a sound pressure level spectrum generated by said transparent panel-form loudspeaker, said sound pressure level spectrum also varying according to the values of said design parameters of said panel-form loudspeaker;
(c) identifying favorable modal parameters which are beneficial to sound radiation and unfavorable modal parameters which have adverse effects on the sound radiation;
(d) selecting the values of said design parameters resulting in suppressing the adverse effects of the unfavorable modal parameters, magnifying beneficial effects of the unfavorable modal parameters, and achieving a desired sound pressure level spectrum over a specific frequency range; and
(e) making said rectangular transparent panel of said panel-form loudspeaker with selected values of said design parameters;
wherein said design parameters of the transparent panel-form loudspeaker are selected via a two-level optimization approach in which the ratio of elastic modulus to density and the ratio of length to thickness of the transparent panel are selected to maximize the sound pressure levels at some specific frequencies for the transparent panel-form loudspeaker at a first level of optimization, while locations of said transducers and said discrete supports of the flexible suspension device on a peripheral edge of the rectangular transparent panel are selected to make the panel-form loudspeaker produce more uniform distribution of the sound pressure level in a specific frequency range at a second level of optimization; and
wherein said transducers are located at points with distances greater than one tenth of lengths of edges on which the transducers are mounted away from ends of the edges and the distances between supporting points of discrete supports and said transducers are greater than one tenth of the length of the edge on which both said supporting points and the transducers are situated.
2. The method according to claim 1 wherein said transport panel used in fabricating the transparent panel-form loudspeaker is selected to have said ratio of elastic modulus to density greater than 80 and less than 180 GPa(gcom3) and said ratio of length to thickness greater than 80 and less than 600.