All The Claims

1. Actuator in the form of a single-layer or multi-layer flat plate, comprising:
an upper face;
a lower face;
at least one layer having two electrodes spaced from each other by a linear separating area and arranged opposite each other both on its upper face and on its lower face, said electrodes of said upper face are arranged at an offset from said electrodes of said lower face;
wherein said actuator comprises at least one friction element, said friction element being arranged along said separating area;
wherein the electrodes of said upper face are configured to oscillate deformations of said actuator along a first axial direction for driving a movable element in contact with said actuator in said first axial direction and said electrodes of said lower face are configured to oscillate deformations of said actuator along a second axial direction for driving the movable element in contact with said actuator in said second axial direction, when the electrodes of said upper face and the electrodes of said lower face are electrically actuated respectively.
2. Actuator according to claim 1, wherein said actuator has the shape of a polygonal plate.
3. Actuator according to claim 2, wherein said actuator has the shape of a square plate.
4. Actuator according to claim 1, wherein said electrodes of said upper face are arranged at an offset from said electrodes of said lower face by essentially 90\xb0.
5. Actuator according to claim 1, wherein said friction element is inserted into said actuator.
6. Actuator according to claim 5, wherein said friction element is inserted into a through hole provided in said actuator.
7. Actuator according to claim 1, wherein said actuator has a multilayer structure and an odd number of layers, where said respective electrodes facing each other on adjacent layers have the same orientation.
8. Actuator according to claim 7, wherein the uppermost layer and lowermost layer of said actuator are inactive layers.
9. Actuator according to claim 8, wherein said uppermost layer andor said lowermost inactive layer areis provided with termination electrodes.
10. Actuator according to claim 1, wherein said actuator is operated while exciting the second resonant frequency or an integral multiple of the second longitudinal resonance frequency.
11. Actuator according to claim 1, wherein, said electrodes of said upper face and said electrodes of said lower face are configured to oscillate hula-hoop-like deformations for rotationally driving a movable element in contact with said actuator by dephased electrically actuating said electrodes of said upper face and said electrodes of said lower face.
12. Actuator according to claim 1, wherein said deformations obtained by electrical actuation of said electrodes are located in the plane of said actuator.
13. Motor, comprising said actuator according to claim 1 and the moveable element to be driven by said actuator.
14. Actuator according to claim 1, wherein said actuator includes a piezoelectric material.
15. Actuator according to claim 1, wherein said at least one friction element is arranged at the center or at one end of said linear separating area.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An integrated heterodyne terahertz transceiver, comprising:
a quantum cascade laser, comprising
a substrate providing a bottom waveguide layer,
a plurality of layered heterostructures of two or more semiconductor alloys on the substrate,
a top waveguide layer on the layered semiconductor heterostructures, thereby providing an active semiconductor core between the top and bottom waveguide layers; and

at least one receiver formed in a hole in the top waveguide layer of the quantum cascade laser, comprising
a rectifying metal contact on the top surface of the layered semiconductor heterostructures exposed by the hole, thereby forming a metal-to-semiconductor Schottky diode, and
an antenna or horn connected to the rectifying metal contact for receiving a terahertz signal;

wherein the quantum cascade laser couples terahertz local oscillator power to the Schottky diode to mix with the received terahertz signal to provide an intermediate frequency output signal.
2. The integrated heterodyne terahertz transceiver of claim 1, wherein the substrate comprises a semiconductor or metal.
3. The integrated heterodyne terahertz transceiver of claim 2, wherein the semiconductor substrate comprises gallium arsenide.
4. The integrated heterodyne terahertz transceiver of claim 1, wherein the layered semiconductor heterostructures comprise a ridge structure.
5. The integrated heterodyne terahertz transceiver of claim 1, wherein the two or more semiconductor alloys comprise gallium arsenide and aluminum gallium arsenide.
6. The integrated heterodyne terahertz transceiver of claim 1, wherein the top waveguide layer comprises a metal or a doped semiconductor.
7. The integrated heterodyne terahertz transceiver of claim 6, wherein the metal comprises gold.
8. The integrated heterodyne terahertz transceiver of claim 6, wherein the metal comprises a metal stack of nickel, gold, and germanium, or palladium, germanium, and gold.
9. The integrated heterodyne terahertz transceiver of claim 1, wherein the bottom waveguide layer comprises a metal or a doped semiconductor.
10. The integrated heterodyne terahertz transceiver of claim 9, wherein the metal comprises gold.
11. The integrated heterodyne terahertz transceiver of claim 9, wherein the metal comprises a metal stack of nickel, gold, and germanium, or palladium, germanium, and gold.
12. The integrated heterodyne terahertz transceiver of claim 1, wherein the rectifying metal contact comprises titanium.
13. The integrated heterodyne terahertz transceiver of claim 1, wherein the antenna comprises a patch antenna.
14. The integrated heterodyne terahertz transceiver of claim 1, wherein the received terahertz signal has a frequency of 100 GHz to 10 THz.
15. The integrated heterodyne terahertz transceiver of claim 1, further comprising a coplanar waveguide or microstrip line on the layered semiconductor heterostructures to bring off the intermediate frequency output signal.

1. A color printing device, whereby the color printing device comprises a reciprocating color measurement device and a reciprocating optical density sensor.
2. A color printing device according to claim 1, whereby the color measurement device and the optical density sensor reciprocate along the same reciprocating direction.
3. A color printing device according to claim 2, whereby the printing device comprises a media advance mechanism for advancing a media in a media-path direction, and whereby the reciprocating direction is transverse to the media-path direction.
4. In a color printing device, a mobile carriage comprising a color printhead, a color measurement device and an optical density sensor.
5. The reciprocating carriage of claim 4, whereby the color measurement device is a spectrophotometer.
6. The reciprocating carriage of claim 5, whereby the optical density sensor is a densitometer.
7. The reciprocating carriage of claim 5, whereby the color printhead comprises at least 8 ink containers.
8. A color measurement method comprising the following steps:
identify the position of a pattern on a two-dimensional media using a mobile optical density sensor,
derive the position of a color patch on the media from the position of the pattern,
measure the color of the color patch using a color measurement device.
9. A method according to claim 8, whereby the optical density sensor and the color measurement device are comprised in a printing device.
10. A method according to claim 9, whereby the color patch is printed by the printing device.
11. A method according to claim 9, whereby the color patch is printed by another printing device.
12. A method according to claim 8, comprising the step of deriving the position of a plurality of color patches on the media from the position of the pattern.
13. A method according to claim 12, whereby the plurality of color patches forms an array.
14. A method according to claim 8, whereby the pattern comprises a plurality of straight segments.
15. A method according to claim 8, whereby the pattern is located towards a side of the media.
16. A method according to claim 8, whereby the pattern is located towards a leading edge of the media.
17. A method according to claim 8, whereby the pattern comprises a repetition of a sub-pattern.
18. A method according to claim 12, whereby at least some patches have a polygonal perimeter comprising at least 5 sides.
19. A method according to claim 8, whereby the optical density sensor is a first device and the color measurement device a second device different from the first device.
20. A method according to claim 19, whereby the optical density sensor and the color measurement device are mechanically coupled.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A monolithic semiconductor device, comprising:
a first substrate;
an insulating layer formed over the first substrate;
a second substrate disposed over the insulating layer;
a power metal-oxide-semiconductor field-effect transistor (MOSFET) with body diode formed over the second substrate;
a first Schottky diode formed over the second substrate in proximity to the power MOSFET;
an insulation trench formed within the second substrate between the power MOSFET and first Schottky diode;
a first electrical connection formed between a source of the power MOSFET and an anode of the first Schottky diode; and
a second electrical connection formed between a drain of the power MOSFET and a cathode of the first Schottky diode.
2. The monolithic semiconductor device of claim 1, wherein the isolation trench surrounds the power MOSFET and first Schottky diode.
3. The monolithic semiconductor device of claim 1, further including:
a row of first interconnect sites coupled to the drain of the power MOSFET and cathode of the first Schottky diode;
a row of second interconnect sites coupled to the source of the power MOSFET and anode of the first Schottky diode; and
a third interconnect site coupled to a gate of the power MOSFET.
4. The monolithic semiconductor device of claim 3, wherein the first and second interconnect sites include a solder bump or wirebond.
5. The monolithic semiconductor device of claim 3, wherein the third interconnect site is disposed within the row of first interconnect site or within the row of second interconnect sites.
6. The monolithic semiconductor device of claim 1, wherein the first Schottky diode reduces charge build-up within the body diode and reverse recovery time of the power MOSFET.
7. The monolithic semiconductor device of claim 1, wherein the power MOSFET operates at higher switching speeds to increase audio sample rate.
8. A monolithic semiconductor device, comprising:
a first substrate;
a first power metal-oxide-semiconductor field-effect transistor (MOSFET) with body diode formed over the first substrate;
a first Schottky diode formed over the first substrate in proximity to the first power MOSFET;
a first electrical connection formed between a source of the first power MOSFET and an anode of the first Schottky diode; and
a second electrical connection formed between a drain of the first power MOSFET and a cathode of the first Schottky diode.
9. The monolithic semiconductor device of claim 8, further including:
a row of first interconnect sites coupled to the drain of the first power MOSFET and cathode of the first Schottky diode;
a row of second interconnect sites coupled to the source of the first power MOSFET and anode of the first Schottky diode; and
a third interconnect site coupled to a gate of the first power MOSFET.
10. The monolithic semiconductor device of claim 8, wherein the first Schottky diode reduces charge build-up within a body diode and reverse recovery time of the first power MOSFET.
11. The monolithic semiconductor device of claim 8, further including:
a second power MOSFET with body diode formed over the first substrate; and
a second Schottky diode formed over the first substrate in proximity to the second power MOSFET.
12. The monolithic semiconductor device of claim 8, further including an insulation trench formed within the first substrate between the first power MOSFET and first Schottky diode.
13. The monolithic semiconductor device of claim 12, wherein the isolation trench surrounds the first power MOSFET and first Schottky diode.
14. The monolithic semiconductor device of claim 8, further including:
an insulating layer formed over the first substrate; and
a second substrate disposed over the insulating layer.
15. A semiconductor device, comprising:
an electronic circuit; and
a switching device operating in response to the electronic circuit, the switching device including,
(a) a substrate,
(b) a power metal-oxide-semiconductor field-effect transistor (MOSFET) with body diode formed over the substrate,
(c) a Schottky diode formed over the substrate in proximity to the power MOSFET,
(d) a first electrical connection formed between a source of the power MOSFET and an anode of the Schottky diode, and
(e) a second electrical connection formed between a drain of the power MOSFET and a cathode of the Schottky diode.
16. The semiconductor device of claim 15, wherein the electronic circuit includes a pulse width modulator having an output coupled to a gate of the power MOSFET.
17. The semiconductor device of claim 15, wherein the electronic circuit includes an audio amplifier having an output coupled to a gate of the power MOSFET.
18. The semiconductor device of claim 15, further including:
a row of first interconnect sites coupled to the drain of the power MOSFET and cathode of the Schottky diode;
a row of second interconnect sites coupled to the source of the power MOSFET and anode of the Schottky diode; and
a third interconnect site coupled to a gate of the power MOSFET.
19. The semiconductor device of claim 15, further including an insulation trench formed within the substrate between the power MOSFET and Schottky diode.
20. A method of making a monolithic semiconductor device, comprising:
providing a first substrate;
forming a first power metal-oxide-semiconductor field-effect transistor (MOSFET) with body diode over the first substrate;
forming a first Schottky diode over the first substrate in proximity to the first power MOSFET;
forming a first electrical connection between a source of the first power MOSFET and an anode of the first Schottky diode; and
forming a second electrical connection between a drain of the first power MOSFET and a cathode of the first Schottky diode.
21. The method of claim 20, further including:
forming a row of first interconnect sites electrically connected to the drain of the first power MOSFET and cathode of the first Schottky diode;
forming a row of second interconnect sites electrically connected to the source of the first power MOSFET and anode of the first Schottky diode; and
forming a third interconnect site electrically connected to a gate of the first power MOSFET.
22. The method of claim 20, further including:
forming a second power MOSFET with body diode formed over the first substrate; and
forming a second Schottky diode formed over the first substrate in proximity to the second power MOSFET.
23. The method of claim 20, further including forming an insulation trench within the first substrate between the first power MOSFET and first Schottky diode.
24. The method of claim 23, wherein the isolation trench surrounds the first power MOSFET and first Schottky diode.
25. The method of claim 20, further including:
forming an insulating layer over the first substrate; and
disposing a second substrate over the insulating layer.