All The Claims

1. A method of controlling a separation distance between a print head and a substrate, comprising the steps of:
(a) biasing a print head toward a substrate onto which flowable material from the print head is applied under pressure; and
(b) controlling a separation distance between the print head and substrate by forming a gas cushion between the print head and substrate that opposes the biasing applied in step (a),
wherein the print head includes a nozzle plate having at least one array of nozzles and wherein the method further comprises the step of translating the nozzle plate in a direction toward or away from the substrate using the gas cushion.
2. The method of claim 1, further comprising the step of providing the print head in a fixture that is spaced from the substrate by a substantially fixed distance, wherein step (a) further comprises biasing the print head away from the fixture using at least one biasing member coupled to both the fixture and the print head.
3. The method of claim 1, further comprising the step of applying the gas cushion via outlets in the nozzle plate that are located around the perimeter of the at least one array of nozzles.
4. The method of claim 3, further comprising the step of venting the gas cushion using a plurality of vents positioned between the outlets and nozzles such that gas from the gas cushion vents from between the nozzle plate and the substrate without substantially interfering with the application of the flowable material onto the substrate.
5. The method of claim 1, wherein the flowable material comprises an organic material and wherein the method further comprises the step of carrying out organic vapor jet printing by applying the organic material to the substrate through the print head while simultaneously carrying out steps (a) and (b).
6. A printing head mechanism for use in applying flowable material to a substrate, comprising:
a print head mounted for translational movement relative to the substrate on which flowable material from the print head is to be applied, said print head being biased toward the substrate in the absence of an applied external force; and
a gas cushion feed assembly that supplies a gas under pressure between said print head and the substrate which opposes biasing of said print head toward the substrate so as to form a space between said print head and the substrate,
wherein said print head includes a nozzle plate having a surface at which one or more nozzles is located and which confronts the substrate when in use, and wherein the print head includes a nozzle feeder connected to said nozzle plate for supplying the flowable material under pressure to said nozzle plate, said nozzle plate including passages that provide fluidic communication between said nozzle feeder and said one or more nozzles, said one or more nozzles comprising apertures located in the surface of said nozzle plate, wherein when in use, said surface of said nozzle plate is positioned opposite the substrate with said surface being spaced from the substrate by a separation distance across which the flowable material moves under pressure as it is applied by said print head from said one or more nozzles onto the substrate.
7. A printing head mechanism as defined in claim 6, further comprising a fixture supporting said print head, said print head being biased toward the substrate via at least one biasing member disposed between said print head and said fixture.
8. A printing apparatus including a printing head mechanism as defined in claim 6, wherein said print head includes a plurality of nozzles and a plurality of outlets disposed about said nozzles, and further comprising a gas pressure source, a control valve connected between said gas pressure source and said outlets to control the supply of gas to said outlets based on an input control signal to said control valve, and a controller that generates and supplies the control signal to said control valve.
9. A printing apparatus as defined in claim 8, wherein said print head includes at least one vent positioned between said one or more outlets and said nozzles, said one or more vents being sized to permit gas from the gas cushion to vent from between said print head and the substrate without substantially interfering with the application of the flowable material onto the substrate.
10. A printing head mechanism for use in applying flowable material to a substrate, comprising:
a print head having a nozzle plate and a nozzle feeder connected to said nozzle plate for supplying flowable material under pressure to said nozzle plate, said nozzle plate including at least one array of nozzles and passages that provide fluidic communication between said nozzle feeder and said nozzles, said nozzles comprising apertures located in a surface of said nozzle plate, wherein when in use, said surface of said nozzle plate is positioned opposite the substrate with said surface being spaced from the substrate by a separation distance across which the flowable material moves under pressure as it is applied by said print head from said nozzles onto the substrate;
a fixture supporting said nozzle plate and permitting relative motion between said fixture and said nozzle plate such that said separation distance is adjustable;
one or more biasing members coupled to said print head and said fixture, said one or more biasing members biasing said nozzle plate toward the substrate when in use; and
a gas cushion feed assembly comprising at least one gas cushion feed line and one or more outlets located at said nozzle plate such that gas supplied through said one or more outlets provides a gas cushion between said nozzle plate and the substrate that opposes the biasing of said one or more biasing members to thereby permit control of the separation distance based on the pressure of the gas supplied via said gas feed lines.
11. A printing head mechanism as defined in claim 10, wherein said one or more biasing members comprise a plurality of springs positioned between said fixture and said nozzle plate.
12. A printing head mechanism as defined in claim 10, wherein said nozzle plate includes a central region at which said nozzles are located and wherein said one or more outlets comprise a plurality of outlets connected to said feed lines and being located in said nozzle plate in an area surrounding and spaced from said nozzles.
13. A printing head mechanism as defined in claim 10, wherein said nozzle plate includes at least one vent positioned between said one or more outlets and said apertures of said nozzles, said one or more vents being sized to permit gas from the gas cushion to vent from between said nozzle plate and the substrate without substantially interfering with the application of the flowable material onto the substrate.
14. A printing head mechanism as defined in claim 10, wherein said fixture has a fixed spacing relative to the substrate when in use.
15. A printing head mechanism as defined in claim 10, wherein said nozzle feeder extends longitudinally in a direction substantially perpendicular to said surface and is attached to said print head at a rear surface of said nozzle plate.
16. A printing head mechanism as defined in claim 10, wherein said fixture comprises a collar surrounding said nozzle feeder.
17. A printing apparatus comprising a printing head mechanism as defined in claim 10 and further including:
a gas pressure source;
a control valve connected between said gas pressure source and said at least one feed line to control the supply of gas into at least one said feed line based on an input control signal to said control valve; and
a controller that generates and supplies the control signal to said control valve.
18. An organic vapor jet printing apparatus comprising the printing head mechanism of claim 10.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A chocolate or chocolate-like food comprising an oil and fat,
said oil and fat comprising 50 to 85% by weight of triglyceride in which oleic acid is bound at position 2 and saturated fatty acids having 16 or more carbon atoms is bound at positions 1 and 3 (XOX type triglyceride); and 5 to 18% by weight of triglyceride in which two oleic acids are bound and one saturated fatty acid having 16 or more carbon atoms is bound (XO2 type triglyceride).
2. The chocolate or chocolate-like food according to claim 1, wherein said oil and fat comprises, as said XOX type triglyceride, 12 to 40% by weight of triglyceride in which oleic acid is hound at position 2 and palmitic acid and stearic acid are bound at each of positions 1 and 3 (POSt type triglyceride); and 22 to 36% by weight of triglyceride in which oleic acid is bound at position 2 and stearic acid is bound at positions 1 and 3 (StOSt type triglyceride).
3. The chocolate or chocolate-like food according to claim 1, wherein said oil and fat comprises as said XO2 type triglyceride, 4 to 16% by weight of triglyceride in which two oleic acids are bound and one stearic acid is bound (StO2 type triglyceride.).
4. The chocolate or chocolate-like food according to claim 1, wherein said oil and fat comprises less than 5% by weight of triglyceride in which unsaturated fatty acid having 16 or more carbon atoms is bound at all of positions 1, 2, and 3 (U3 type trialyceride) and less than 2% by weight of trans fatty acid as a constituent fatty acid.
5. The chocolate or chocolate-like food according to claim 1,
wherein said oil and fat is a mixed oil and fat comprising 5 to 40% by weight of the following oil and fat composition A:
a oil and fat composition comprising 30 to 50% by weight of StOSt type triglyceride and 20 to 45% by weight of StO2 type triglyceride.
6. The chocolate or chocolate-like food according to claim 5, wherein said oil and fat composition A comprises less than 2% by weight of triglyceride in which oleic acid is bound at position 2 and stearic acid and arachidic acid are bound at each of positions 1 and 3 (StOAr type triglyceride).
7. A chocolate product comprising said chocolate or chocolate-like food according to claim 1.
8. A method of inhibiting low-temperature bloom on a chocolate or chocolate-like food comprising an oil and fat,
comprising making a content of triglyceride having, an oleic acid at position 2 and saturated fatty acids having 16 or more carbon atoms at positions 1 and 3 (XOX type triglyceride) to 50 to 85% by weight; and making a content of triglyceride in which two oleic acids are bound and one saturated fatty acid having 16 or more carbon atoms is bound (XO2 type triglyceride) to 5 to 18% by weight in said oil and fat.
9. An oil and fat composition comprising 30 to 50% by weight of triglyceride in which oleic acid is bound at position 2 and stearic acid is bound at positions 1 and 3 (StOSt type triglyceride) and 20 to 45% by weight of triglyceride in which two oleic acids are bound and one stearic acid is bound (StO2 type triglyceride).
10. The oil and fat composition according to claim 9, wherein a content of StOSt type triglyceride is 30 to 47% by weight, said oil and fat composition comprising less than 2% by weight of triglyceride in which oleic acid is bound at position 2 and stearic acid and arachidic acid are bound at each of positions 1 and 3 (StOAr type triglyceride).
11. The oil and fat composition according to claim 9, which said oil and fat composition is one used in said chocolate or chocolate-like food.
12. A method of producing said oil and fat composition according to claim 9,
comprising the step of bringing an oil and fat rich in triglyceride in which oleic acid is bound at position 2 and lower alkyl ester of stearic acid into a transesterification reaction.
13. A method of producing a chocolate or chocolate-like food comprising an oil and fat,
comprising the step of blending the oil and fat composition according to claim 9 in said oil and fat of said chocolate or chocolate-like food in an amount of 5 to 40% by weight.
14. A method of inhibiting low-temperature bloom on a chocolate or chocolate-like food comprising, an oil and fat,
comprising the step of blending the oil and fat composition according to claim 9 in said oil and fat of said chocolate or chocolate-like food in an amount of 5 to 40% by weight.
15. A low-temperature bloom inhibitor comprising 30 to 50% by weight of triglyceride in which oleic acid is bound at position 2 and stearic acid is bound at positions 1 and 3 (StaSt type triglyceride) and 20 to 45% by weight of triglyceride in which two oleic acids are bound and one stearic acid is bound (StO2 type triglyceride).

1-13. (canceled)
14. A method of producing a polytetrafluoroethylene laminated article, wherein after a polytetrafluoroethylene sheet and heat-meltable resin film or sheet are directly subjected to thermo-fusing, a rapid temperature lowering is prevented to sufficiently crystallize molten polytetrafluoroethylene.
15-30. (canceled)
31. The production method of claim 14, wherein the laminated article is held within a temperature range of less than a melting point of polytetrafluoroethylene and not less than 300\xb0 C. to prevent a rapid temperature lowering.
32. The production method of claim 14, wherein a polytetrafluoroethylene sheet having a specific weight exceeding 2.175 is used as said polytetrafluoroethylene sheet.
33. The production method of claim 14, wherein a heat resistant woven fabric is overlaid on the opposite side of said heat-meltable resin film or sheet, and the heat-meltable resin film or sheet and the heat resistant woven fabric are subjected to thermo-fusing.
34. The production method of claim 33, wherein the heating is carried out from the side of heat resistant woven fabric.
35. (canceled)
36. The production method of claim 14, wherein a laminated article having a layered structure comprising a polytetrafluoroethylene sheet having an average specific weight of not less than 2.175 and a heat-meltable resin layer is produced by using a polytetrafluoroethylene sheet having a specific weight exceeding 2.175 as said polytetrafluoroethylene sheet.
37. The production method of claim 14, wherein a laminated article having a layered structure obtained by laminating a polytetrafluoroethylene sheet having an average specific weight of not less than 2.175 and a heat resistant woven fabric by interposing a heat-meltable resin layer therebetween is produced by using a polytetrafluoroethylene sheet having a specific weight exceeding 2.175 as said polytetrafluoroethylene sheet.
38. The production method of claim 14, wherein the heating is stopped at a time when an un-molten layer remains in said polytetrafluoroethylene sheet.
39. The production method of claim 14, wherein a polytetrafluoroethylene sheet surface reverse to the laminated surface thereof is heat-treated at a temperature of not less than a melting point of polytetrafluoroethylene before or after said thermo-fusing or at the same time as said thermo-fusing.
40. The production method of claim 14, wherein the laminated article is a backing sheet.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. Flip-flop circuitry comprising:
first and second inverter circuits;
first and second passgate circuits for respectively applying an input signal to the first inverter circuit and an output signal of the first inverter circuit to the second inverter circuit in response to respective first and second phases of a first control signal; and
a third passgate circuit connected in parallel with the second passgate circuit and responsive to a second control signal, wherein the parallel combination comprising the second and third passgate circuits is connected in series between the first and second inverter circuits.
2. The circuitry defined in claim 1 wherein the first control signal is a clock signal.
3. The circuitry defined in claim 1 wherein each of the inverter circuits consists essentially of a pair of CMOS transistors.
4. The circuitry defined in claim 1 wherein each of the first and second passgate circuits consists essentially of a pair of CMOS transistors.
5. The circuitry defined in claim 1 wherein the third passgate circuit consists essentially of a pair of CMOS transistors.
6. The circuitry defined in claim 1 further comprising:
a third inverter circuit for receiving the first phase of the first control signal and for producing therefrom the second phase of the first control signal.
7. The circuitry defined in claim 6 wherein the third inverter circuit consists essentially of a pair of CMOS transistors.
8. The circuitry defined in claim 6 wherein the flip-flop circuitry consists essentially of the first, second, and third inverter circuits and the first, second, and third passgate circuits.
9. The circuitry defined in claim 1 wherein the sole circuitry connected between a data output terminal of the first passgate circuit and a data input terminal of the second passgate circuit is a pair of CMOS transistors forming the first inverter circuit.
10. The circuitry defined in claim 1 wherein the sole circuitry connected between a data output terminal of the second passgate circuit and a data output terminal of the flip-flop circuitry is a pair of CMOS transistors forming the second inverter circuit.
11. A plurality of flip-flop circuitries as defined in claim 1 connected in a series with one another.
12. The plurality of flip-flop circuitries connected in a series as defined in claim 11 further comprising a plurality of scan flip-flop circuitries connected within the series.
13. The plurality of flip-flop circuitries connected in a series as defined in claim 11 further comprising circuitry for applying the second control signal of at least one of the flip-flop circuits,
wherein said circuitry applying increases or decreases an amount of time it takes for a signal to propagate through the series of flip-flop circuitries.
14. The plurality of flip-flop circuitries connected in a series as defined in claim 11 further comprising a plurality of combinatorial logic circuitries connected within the series.
15. The plurality of flip-flop circuitries connected in a series as defined in claim 11 further comprising a scan chain connected to the said plurality of flip-flop circuitries.
16. Scan chain circuitry comprising:
a first and a second plurality of scan flip-flop circuitries connected together to form a first and a second scan chain; and
a plurality of bypass flip-flop circuitries connected together to form at least one serial chain, wherein the at least one serial chain is connected between one of the first plurality of scan flip-flop circuitries and one of the second plurality of scan flip-flop circuitries, wherein each of the plurality of bypass flip-flop circuitries comprises:
first and second inverter circuits,
first and second passgate circuits for respectively applying an input signal to the first inverter circuit and an output signal of the first inverter circuit to the second inverter circuit in response to respective first and second phases of a first control signal, and
a third passgate circuit connected in parallel with the second passgate circuit and responsive to a second control signal, wherein the parallel combination comprising the second and third passgate circuits is connected in series between the first and second inverter circuits.
17. The scan chain circuitry of claim 16 further comprising combinatorial logic circuitries connected within the at least one serial chain.
18. The scan chain circuitry of claim 16 wherein a test vector is shifted into the first scan chain.
19. The scan chain circuitry of claim 16 wherein an output vector is shifted out of the second scan chain.
20. The scan chain circuitry of claim 16 wherein the plurality of bypass flip-flop circuitries are in bypass mode.
21. Flip-flop apparatus comprising:
first passgate means for applying an input signal to a first means for inverting in response to a first phase of a first control signal;
second passgate means for applying the output of the first means for inverting to a second means for inverting in response to a second phase of the first control signal; and
third passgate means for applying connected in parallel with the second passgate means for applying and responsive to a second control signal, wherein the parallel combination comprising the second and third passgate means for applying is connected in series between the first and second means for inverting.
22. The apparatus defined in claim 21 wherein the first control signal is a clock signal.
23. The apparatus defined in claim 21 wherein each of the means for inverting consists essentially of a pair of CMOS transistors.
24. The apparatus defined in claim 21 wherein each of the first and second passgate means for applying consists essentially of a pair of CMOS transistors.
25. The apparatus defined in claim 21 wherein the third passgate means for applying consists essentially of a pair of CMOS transistors.
26. The apparatus defined in claim 21 further comprising:
third means for inverting for receiving the first phase of the first control signal and for producing therefrom the second phase of the first control signal.
27. The apparatus defined in claim 26 wherein the third means for inverting consists essentially of a pair of CMOS transistors.
28. The apparatus defined in claim 26 wherein the flip-flop apparatus consists essentially of the first, second, and third means for inverting and the first, second, and third passgate means for applying.
29. The apparatus defined in claim 21 wherein the sole circuitry connected between a data output terminal of the first passgate means for applying and a data input terminal of the second passgate means for applying is a pair of CMOS transistors forming the first means for inverting.
30. The apparatus defined in claim 21 wherein the sole circuitry connected between a data output terminal of the second passgate means for applying and a data output terminal of the flip-flop apparatus is a pair of CMOS transistors forming the second means for inverting.
31. A plurality of flip-flop apparatuses as defined in claim 21 connected in a series with one another.
32. The plurality of flip-flop apparatuses connected in a series as defined in claim 31 further comprising a plurality of scan flip-flop apparatuses connected within the series.
33. The plurality of flip-flop apparatuses connected in a series as defined in claim 31 further comprising means for applying the second control signal of at least one of the flip-flop circuits,
wherein said means for applying increases or decreases an amount of time it takes for a signal to propagate through the series of flip-flop apparatuses.
34. The plurality of flip-flop apparatuses connected in a series as defined in claim 31 further comprising a plurality of combinatorial logic apparatuses connected within the series of flip-flop apparatuses.
35. The plurality of flip-flop apparatuses connected in a series as defined in claim 31 further comprising a scan chain apparatus connected to said plurality of flip-flop apparatuses.
36. Scan chain apparatus comprising:
a first and a second plurality of scan flip-flop means connected together to form a first and a second scan chain means; and
a plurality of bypass flip-flop means connected together to form at least one serial chain means, wherein the at least one serial chain means is connected between one of the first plurality of scan flip-flop means and one of the second plurality of scan flip-flop means, wherein each of the plurality of bypass flip-flop means comprises:
first passgate means for applying an input signal to a first means for inverting in response to a first phase of a first control signal,
second passgate means for applying the output of the first means for inverting to a second means for inverting in response to a second phase of the first control signal, and
third passgate means for applying connected in parallel with the second passgate means for applying and responsive to a second control signal, wherein the parallel combination comprising the second and third passgate means for applying is connected in series between the first and second means for inverting.
37. The scan chain apparatus of claim 36 further comprising combinatorial logic means connected within the at least one serial chain means.
38. The scan chain apparatus of claim 36 wherein a test vector means is shifted into the first scan chain means.
39. The scan chain apparatus of claim 36 wherein an output vector means is shifted out of the second scan chain means.
40. The scan chain apparatus of claim 36 wherein the plurality of bypass flip-flop means are in bypass mode.
41. A method of flip-flop circuit operation comprising:
applying with first passgate circuitry an input signal to a first inverter in response to a first phase of a first control signal;
using the first inverter to invert the input signal to produce a first inverter output signal;
further applying with second passgate circuitry the first inverter output signal to a second inverter in response to a second phase of the first control signal;
alternatively applying with third passgate circuitry the first inverter output signal to the second inverter in response to a second control signal; and
using the second inverter to invert the first inverter output signal as applied to the second inverter by the further applying or the alternatively applying.
42. The method of claim 41 wherein the first control signal is a clock signal.
43. The method of claim 41 wherein each of the inverters consists essentially of a pair of CMOS transistors.
44. The method of claim 41 wherein the first passgate circuitry consists essentially of a pair of CMOS transistors.
45. The method of claim 41 wherein the second passgate circuitry consists essentially of a pair of CMOS transistors.
46. The method of claim 41 wherein the third passgate circuitry consists essentially of a pair of CMOS transistors.
47. The method of claim 41 further comprising:
receiving the first phase of the first control signal with a third inverter; and
using the third inverter to invert the received first phase of the first control signal to produce therefrom the second phase of the first control signal.
48. The method of claim 47 wherein the third inverter consists essentially of a pair of CMOS transistors.
49. A method of scan chain operation comprising:
connecting a first and a second plurality of scan flip-flop circuitries together to form a first and a second scan chain;
connecting a plurality of bypass flip-flop circuitries together to form at least one serial chain; and
connecting the at least one serial chain between one of the first plurality of scan flip-flop circuitries and one of the second plurality of scan flip-flop circuitries, wherein the operation of each of the plurality of bypass flip-flop circuitries comprises:
applying with first passgate circuitry an input signal to a first inverter in response to a first phase of a first control signal,
using the first inverter to invert the input signal to produce a first inverter output signal,
further applying with second passgate circuitry the first inverter output signal to a second inverter in response to a second phase of the first control signal,
alternatively applying with third passgate circuitry the first inverter output signal to the second inverter in response to a second control signal, and
using the second inverter to invert the first inverter output signal as applied to the second inverter by the further applying or the alternatively applying.
50. The method of claim 49 further comprising connecting combinatorial logic circuitries within the at least one serial chain.
51. The method of claim 49 further comprising shifting a test vector into the first scan chain.
52. The method of claim 49 further comprising shifting an output vector out of the second scan chain.
53. The method of claim 49 further comprising putting the plurality of bypass flip-flop circuitries into bypass mode.