1. A method of simulating an electrostatic discharge (ESD) circuit layout, comprising a computer processor for performing the following steps:
providing a netlist that describes connectivity among components in an electronic circuit;
pre-simulating the netlist for modeling of circuit operation;
generating a circuit layout corresponding to the electronic circuit according to a result of the pre-simulation, the generated circuit layout including an ESD circuit layout and a plurality of back-end layers for connecting individual components of the electronic circuit;
extracting parasitic according to the generated circuit layout;
providing an ESD waveform for simulating the ESD circuit layout; and
post-simulating the ESD circuit layout according to the ESD waveform and a result of the parasitic extraction;
wherein the back-end layers are subjected to the post-simulation and the post-simulation step comprises:
coupling one of a plurality of pads of the electronic circuit with the ESD waveform and grounding another of the pads, thereby forming an ESD path;
reporting currents passing through the corresponding back-end layers, respectively;
comparing the reported current with a corresponding given rated current; and
highlighting the back-end layer that has the reported current equal or greater than the corresponding rated current.
2. The method of claim 1, wherein the netlist is pre-simulated by a transistor-level circuit simulation tool.
3. The method of claim 1, wherein the back-end layers comprises one or more of the following: metal layers, vias and contacts.
4. The method of claim 1, wherein the extracted parasitics comprise parasitic capacitance and parasitic resistance.
5. The method of claim 1, wherein the extracted parasitic is represented in a Detailed Standard Parasitic Format (DSPF) file.
6. The method of claim 1, in the parasitic extraction step, a layout versus schematic (LVS) tool is used to verify whether the circuit layout matches the netlist.
7. The method of claim 1, wherein the pads in each said ESD path is either a power pad, a ground pad or an inputoutput (IO) pad.
8. The method of claim 7, wherein the ESD path is established between (1) two of the powerground pads, (2) the IO pad and the powerground pad, or (3) two of the IO pads.
9. The method of claim 1, wherein the post-simulation step further comprises:
ranking the comparing results of the back-end layers; and
visually expressing the back-end layers with a color scale that is divided into several sections represented by different colors associated with different ranks, respectively.
10. The method of claim 1, wherein the post-simulation step further comprises:
making change to a width, quantity or a location of the back-end layers according to the comparing results.
11. The method of claim 1, wherein the post-simulation is performed further according to a result of the pre-simulation.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of manufacturing a package carrier comprising:
providing a holding substrate and a conductive layer, wherein the conductive layer is formed on the holding substrate;
forming an insulating pattern on the conductive layer, wherein the insulating pattern exposes a portion of the conductive layer;
providing a supporting board;
detachably connecting the insulating pattern to the supporting board, wherein the insulating pattern is in contact with the supporting board;
removing the holding substrate and letting the conductive layer remain after detachably connecting the insulating pattern to the supporting board; and
patterning the conductive layer to form a wiring layer after removing the holding substrate.
2. The method of manufacturing the package carrier according to claim 1, wherein the insulating pattern is a solder mask layer.
3. The method of manufacturing the package carrier according to claim 1 further comprising forming a bonding material on the portion of the conductive layer exposed by the insulating pattern.
4. The method of manufacturing the package carrier according to claim 3, wherein the bonding material is a solder layer, metallic layer or organic solderablilty preservatives (OSP) layer.
5. The method of manufacturing the package carrier according to claim 1, wherein the supporting board has a recess pattern fitting the insulating pattern, and the insulating pattern is deposed in the recess pattern after the insulating pattern is detachably connected to the supporting board.
6. The method of manufacturing the package carrier according to claim 1, wherein the holding substrate includes a main plate and a release layer, and the release layer is interposed between the main plate and the conductive layer.
7. The method of manufacturing the package carrier according to claim 1 further comprising forming a solder mask layer on the wiring layer after the wiring layer is formed.
8. The method of manufacturing the package carrier according to claim 7, wherein the supporting board comprises a metal layer electrically connected to the wiring layer, the method after forming the solder mask layer further comprising:
electrifying the metal layer to electroplate the wiring layer, thereby forming a protective layer, wherein the solder mask layer exposes the protective layer.
9. The method of manufacturing the package carrier according to claim 1 further comprising changing a surface roughness of the wiring layer after the wiring layer is formed.
10. The method of manufacturing the package carrier according to claim 1 comprising:
providing at least two conductive layers, wherein the holding substrate is interposed between the conductive layers;
forming two insulating patterns respectively on the conductive layers;
providing two supporting boards;
detachably connecting the insulating patterns to the supporting boards respectively, wherein the insulating patterns is in contact with the supporting boards respectively;
removing the holding substrate and letting the conductive layers remain after detachably connecting the insulating patterns to the supporting boards; and
patterning the conductive layers to form wiring layers respectively after removing the holding substrate.
11. A method of manufacturing a package carrier comprising:
forming a circuit structure and an insulating pattern on a holding substrate, wherein the insulating pattern is attached to the circuit structure, and the circuit structure is interposed between the insulating pattern and the holding substrate;
providing a supporting board;
detachably connecting the insulating pattern to the supporting board, wherein the insulating pattern is in contact with the supporting board; and
removing the holding substrate and letting the circuit structure remain after detachably connecting the insulating pattern to the supporting board.
12. The method of manufacturing the package carrier according to claim 11, wherein forming the circuit structure comprises:
providing a conductive layer on the holding substrate;
forming a barrier layer on the conductive layer; and
forming at least one wiring layer on the barrier layer, wherein the insulating pattern is formed on the wiring layer.
13. The method of manufacturing the package carrier according to claim 12, wherein the barrier layer and the conductive layer are removed after removing the holding substrate.
14. The method of manufacturing the package carrier according to claim 12, wherein forming the wiring layer comprises forming a seed layer on the barrier layer interposed between the conductive layer and the seed layer; further remove the seed layer after removing the holding substrate.
15. The method of manufacturing the package carrier according to claim 11, wherein forming the circuit structure comprises:
forming a first wiring layer on the holding substrate;
forming a plurality of metal posts on the first wiring layer;
after forming the metal posts, forming a dielectric layer covering the first wiring layer and the metal posts; and
forming a second wiring layer connected to the metal posts on the dielectric layer.
16. A package carrier, comprising:
a circuit structure comprising at least one connecting pad and a mounting pad, wherein the mounting pad is used for mounting an electronic component, and the connecting pad is used for electrically connecting the electronic component; and
an insulating pattern attached to the circuit structure.
17. The package carrier according to claim 16, wherein the circuit structure further comprises:
at least two wiring layers, one of the wiring layers comprising the connecting pad and the mounting pad;
at least one dielectric layer interposed between the wiring layers; and
a plurality of metal posts electrically connected to the wiring layer and arranged in the dielectric layer.
18. The package carrier according to claim 16, wherein the circuit structure is a wiring layer, and the insulating pattern in contact with the wiring layer has an opening exposing the connecting pad.
19. The package carrier according to claim 16 further comprising a supporting board having a recess pattern fitting the insulating pattern, wherein the insulating pattern is detachably connected to the supporting board, and the insulating pattern is disposed in the recess pattern.
20. The package carrier according to claim 19, wherein the supporting board comprises:
a plastic board; and
a metal layer laminated on the plastic board and having the recess pattern, wherein the metal layer is interposed between the insulating pattern and the plastic board.
21. A method of manufacturing an electronic package comprising:
mounting the electronic component on the mounting pad of the package carrier according to claim 19;
forming a molding layer encapsulating the electronic component on the circuit structure; and
removing the supporting board after forming the molding layer.
22. The method of manufacturing the electronic package according to claim 21 further comprising:
dicing the supporting board, the insulating pattern and the circuit structure to form a plurality of strips before mounting the electronic component on the circuit structure, wherein the electronic component is mounted on one of the strips.
23. The method of manufacturing the electronic package according to claim 22 further comprising dicing the strip after removing the supporting board.
24. An electronic package, comprising:
the package carrier according to claim 16;
the electronic component mounted on the mounting pad and electrically connected to at least one connecting pad, wherein the mounting pad and the connecting pad are both interposed between the electronic component and the insulating pattern; and
a molding layer covering the electronic component.
25. The electronic package according to claim 24, wherein the package carrier further comprises a supporting board having a recess pattern fitting the insulating pattern, and the insulating pattern is detachably connected to the supporting board and disposed in the recess pattern.