1. A pH-change sensor, comprising:
a first IST-operational-transconductance-amplifier (the \u201cfirst IOTA\u201d) having:
(a) an output (the \u201cfirst IOTA output\u201d),
(b) an ion-sensitive transistor (the \u201cfirst IST\u201d) having a drain region, and
(c) a load transistor (the \u201cfirst load transistor\u201d) having a source region, a drain region, and a channel region, the channel region electrically connecting the source region and the drain region,
wherein the drain region of the first IST is electrically connected to the drain region of the first load transistor;
a second IST-operational-transconductance-amplifier (the \u201csecond IOTA\u201d) having:
(a) an output (the \u201csecond IOTA output\u201d),
(b) an ion-sensitive transistor (the \u201csecond IST\u201d) having a drain region, and
(c) a load transistor (the \u201csecond load transistor\u201d) having a source region, a drain region and a channel region, the channel region electrically connecting the source region and the drain region,
wherein the drain region of the second IST is electrically connected to the drain region of the second load transistor;
a differential sensor having:
(a) a first input connected to the first IOTA output,
(b) a second input connected to the second IOTA output, and
(c) an output (the \u201cdifferential sensor output\u201d), wherein the differential sensor output may be used to provide an indication of a voltage difference between the first input and the second input;
wherein the first load transistor provides a drain-to-source resistance (the \u201cfirst rds\u201d), and the second load transistor provides a drain-to-source resistance (the \u201csecond rds\u201d), and the first rds is different from the second rds.
2. The sensor of claim 1, wherein the first IST is an ion-sensitive field-effect transistor.
3. The sensor of claim 1, wherein the first IST is an n-channel transistor.
4. The sensor of claim 3, wherein the first load transistor is a p-channel transistor.
5. The sensor of claim 1, wherein the first IST is a p-channel transistor.
6. The sensor of claim 5, wherein the first load transistor is an n-channel transistor.
7. The sensor of claim 1, wherein the first load transistor is a field-effect transistor.
8. The sensor of claim 7, wherein the first load transistor is a metal-oxide semiconductor field-effect transistor.
9. The sensor of claim 1, wherein the channel region of the first load transistor has a width that is different from a width of the channel region of the second load transistor.
10. The sensor of claim 9, wherein the channel region of the first load transistor has a length that is substantially similar to a length of the channel region of the second load transistor.
11. The sensor of claim 1, wherein the first IST and the second IST are substantially similar.
12. The sensor of claim 1, wherein the first IST and the second IST are substantially similarly sensitive to pH.
13. The sensor of claim 1, wherein the differential sensor is a differential amplifier.
14. The sensor of claim 1, wherein the first IST includes a pH-sensitive layer comprised of a compound selected from the group of silicon nitride (Si3N4), silicon oxide (SiO2), aluminum oxide (Al2O3), Titanium Pent-oxide (Ti2O5) and Tin Oxide (Sn02).
15. The sensor of claim 1, wherein the first IST has a pH sensitive layer that is electrically connected to a gate of the first IST.
16. The sensor of claim 15, wherein the first IST further comprises a xerogel at least partially covering the pH-sensitive layer.
17. A pH-change sensor, comprising:
a first ion-sensitive-transistor-operational-transconductance-amplifier (the \u201cfirst IOTA\u201d) having an ion-sensitive transistor (the \u201cfirst IST\u201d) electrically connected to a load transistor (the \u201cfirst load transistor\u201d), and also having an output (the \u201cfirst output\u201d);
a second ion-sensitive-transistor-operational-transconductance-amplifier (the \u201csecond IOTA\u201d) having an ion-sensitive transistor (the \u201csecond IST\u201d) electrically connected to a load transistor (the \u201csecond load transistor\u201d), and also having an output (the \u201csecond output\u201d);
a differential sensor having a first input, a second input and an output (the \u201cdifferential sensor output\u201d), wherein the first input is in communication with the first output, wherein the second input is in communication with the second output, wherein the differential sensor output may be used to provide an indication of a voltage difference between the first input and the second input;
wherein the first load transistor provides a drain-to-source resistance (the \u201cfirst rds\u201d), and the second load transistor provides a drain-to-source resistance (the \u201csecond rds\u201d), and the first rds is different from the second rds;
wherein the first IST and the second IST are substantially similarly sensitive to pH.
18. The sensor of claim 17, wherein the first IST is an ion-sensitive field-effect transistor.
19. The sensor of claim 17, wherein the first IST and the second IST are substantially similar.
20. The sensor of claim 17, wherein the differential sensor is a differential amplifier.
21. The sensor of claim 17, wherein the first IST includes a pH-sensitive layer comprised of a compound selected from the group of silicon nitride (Si3N4), silicon oxide (SiO2), aluminum oxide (Al2O3), Titanium Pent-oxide (Ti2O5) and Tin Oxide (Sn02).
22. The sensor of claim 21, wherein the first IST has a pH-sensitive layer that is electrically connected to the gate of the first IST.
23. The sensor of claim 22, wherein the first IST further comprises a xerogel at least partially covering the pH-sensitive layer.
24. A method of indicating a change in pH, comprising:
providing a sensor having:
(a) a first ion-sensitive-transistor-operational-transconductance-amplifier (the \u201cfirst IOTA\u201d) having an ion-sensitive transistor (the \u201cfirst IST\u201d) electrically connected to a load transistor (the \u201cfirst load transistor\u201d), and also having an output (the \u201cfirst output), the first IST having a pH sensitive layer (the \u201cfirst pH sensitive layer\u201d);
(b) a second ion-sensitive-transistor-operational-transconductance-amplifier (the \u201csecond IOTA\u201d) having an ion-sensitive transistor (the \u201csecond IST\u201d) electrically connected to a load transistor (the \u201csecond load transistor\u201d), and also having an output (the \u201csecond output), the second IST having a pH sensitive layer (the \u201csecond pH sensitive layer\u201d), wherein the first load transistor provides a drain-to-source resistance (the \u201cfirst rds\u201d) in the first IOTA, and the second load transistor provides a drain-to-source resistance (the \u201csecond rds\u201d) in the second IOTA, and the first rds is different from the second rds, and
(c) a differential sensor having a first input, a second input and an output (the \u201cdifferential sensor output\u201d), wherein the first input is in communication with the first output, wherein the second input is in communication with the second output, and wherein the differential sensor output may be used to provide an indication of a voltage difference between the first input and the second input;
placing the first pH sensitive layer and the second pH sensitive layer in contact with a substance;
changing a pH of the substance;
detecting a difference between an output of the first IOTA and an output of the second IOTA, and providing the difference to indicate a change in the pH of the substance.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A package comprising:
a metal pad over a substrate;
a passivation layer extending at least partially over the metal pad;
a metal pillar over and electrically coupled to the metal pad;
a dielectric layer over the passivation layer;
a package material over the dielectric layer, wherein the dielectric layer comprises a bottom portion between the passivation layer and the package material, and a sidewall portion between a sidewall of the metal pillar and a sidewall of the package material;
a polymer layer over the package material and the metal pillar; and
a post-passivation interconnect (PPI) extending into an opening in the polymer layer and electrically coupled to the metal pillar.
2. The package of claim 1, wherein the bottom portion of the dielectric layer has a first thickness close to a second thickness of the sidewall portion of the dielectric layer.
3. The package of claim 1, wherein the package material comprises a molding compound or a polymer.
4. The package of claim 1, wherein a top surface of the package material, top edges of the dielectric layer, and a top surface of the metal pillar are substantially level with each other.
5. The package of claim 4, further comprising a molding compound on a sidewall of the substrate, wherein a top surface of the molding compound is further level with the top surface of the package material, the top edges of the dielectric layer, and the top surface of the metal pillar.
6. The package of claim 1, wherein the dielectric layer comprises a material selected from a group consisting essentially of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbide, tetra-ethyl-ortho-silicate (TEOS) oxide, silicon oxide, and combinations thereof.
7. A package comprising:
a metal pad over a substrate;
a passivation layer comprising a portion covering an edge portion of the metal pad;
a dielectric layer over the passivation layer, wherein a portion of the dielectric layer extends into an opening in the passivation layer, wherein the portion of the dielectric layer contacts the metal pad;
a first polymer layer over the dielectric layer, wherein the dielectric layer is disposed between the metal pad and the first polymer layer; and
a post-passivation interconnect (PPI) comprising a via extending into an opening in the first polymer layer, wherein the via contacts the metal pad.
8. The package of claim 7, further comprising:
a molding compound contacting a sidewall of the substrate, wherein the first polymer layer does not extend over the molding compound; and
a second polymer layer over and vertically overlapping the first polymer layer and the molding compound, wherein the via extends through the second polymer layer into the opening in the first polymer layer.
9. The package of claim 8, wherein the first polymer layer comprises a sidewall contacting a sidewall of the molding compound, wherein the dielectric layer comprises an edge contacting the sidewall of the molding compound, and wherein a top surface of the molding compound is level with a top surface of the first polymer layer.
10. The package of claim 8 further comprising a dielectric hard mask layer over the second polymer layer and under a portion of the PPI.
11. The package of claim 7, wherein an edge of the dielectric layer contacts a sidewall of the via.
12. The package of claim 7, wherein the dielectric layer comprises a material selected from a group consisting essentially of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbide, tetra-ethyl-ortho-silicate (TEOS), silicon oxide, and combinations thereof.
13. A package comprising:
a metal feature over a substrate, wherein the metal feature comprises a metal pad;
a passivation layer covering an edge portion of the metal pad;
a dielectric layer over the passivation layer, wherein a portion of the dielectric layer contacts the metal feature;
a packaging material over the dielectric layer, wherein the dielectric layer is disposed between the metal feature and the packaging material; and
a post-passivation interconnect (PPI) comprising a via extending into an opening in the packaging material, wherein the via contacts the metal pad.
14. The package of claim 13, wherein metal feature further comprises a metal pillar over and electrically coupled to the metal pad, wherein the dielectric layer is disposed on a sidewall of the metal pillar between the sidewall of the metal pillar and the packaging material.
15. The package of claim 13, wherein the dielectric layer is disposed on a top surface of the passivation layer, wherein the dielectric layer is disposed between the passivation layer and the packaging material.
16. The package of claim 15, wherein a first portion of the dielectric layer between the passivation layer and the packaging material has a first thickness, wherein a second portion of the dielectric layer between the metal feature and the packaging material has a second thickness, and wherein the second thickness is substantially equal to the first thickness.
17. The package of claim 13, wherein the package material comprises a molding compound or a polymer.
18. The package of claim 13, wherein a top surface of the package material, top edges of the dielectric layer, and a top surface of the metal feature are substantially level with each other.
19. The package of claim 13, wherein the dielectric layer comprises a material selected from a group consisting essentially of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbide, tetra-ethyl-ortho-silicate (TEOS), silicon oxide, and combinations thereof.
20. The package of claim 13 further comprising a solder ball over the PPI and electrically coupled to the PPI.