All The Claims

1-19. (canceled)
20. A method for converting a subset of a plurality of semiconductor fins on a semiconductor structure into dielectric fins, comprising:
masking a first subset of the plurality of fins, leaving a second subset of the plurality of fins as unmasked fins; and
applying a gas cluster ion beam to the unmasked fins to convert the unmasked fins into dielectric fins.
21. The method of claim 20, wherein masking the first subset of fins comprises depositing photoresist.
22. The method of claim 20, wherein masking the first subset of fins comprises depositing oxide.
23. The method of claim 20, wherein applying a gas cluster ion beam to the unmasked fins comprises applying a gas cluster ion beam at an angle ranging from about 10 degrees to about 20 degrees from vertical.
24. The method of claim 20, wherein applying a gas cluster ion beam to the unmasked fins comprises applying a gas cluster ion beam with a nitrogen species, at an energy ranging from 1 KeV to 100 KeV, and at a dosage ranging from about 5E13 atoms per cubic centimeter to about 2E15 atoms per cubic centimeter.
25. A method for converting a subset of a plurality of semiconductor fins on a semiconductor structure into dielectric fins, comprising:
masking a first subset of the plurality of fins, leaving a second subset of the plurality of fins as unmasked fins; and
applying ion implantation to the unmasked fins to convert the unmasked fins into dielectric fins.
26. The method of claim 25, wherein masking the first subset of fins comprises depositing photoresist.
27. The method of claim 25, wherein masking the first subset of fins comprises depositing oxide.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A radiation hardened digital circuit, comprising:
a delay network configured to receive a global clock signal and generate a first delayed clock signal from the global clock signal such that the first delayed clock signal is delayed with respect to the global clock signal; and
a first Muller C element configured to receive the global clock signal and the first delayed clock signal, wherein the first Muller C element is configured to:
generate a first clock input signal;
set the first clock input signal to one of a set of clock states in response to the first delayed clock signal and the global clock signal each being provided in a same one of the set of clock states, wherein the set of clock states comprises a first clock state and a second clock state; and
hold the first clock input signal in the one of the set of clock states in response to the first delayed clock signal and the global clock signal being provided in different ones of the set of clock states.
2. The radiation hardened digital circuit of claim 1, further comprising:
a first pulsed clock generator configured to generate a first pulsed clock signal from the first clock input signal; and
a first latch configured to receive the first pulsed clock signal and a first input bit signal having a first input bit state, the first latch is being configured to:
generate a first output bit signal;
sample the first input bit state to set a first output bit state of the first output bit signal based on the first input bit state in response to the first pulsed clock signal being in one of the set of clock states; and
hold the first output bit state while the first pulsed clock signal is in an other one of the set of clock states.
3. The radiation hardened digital circuit of claim 1 further comprising a second Muller C element wherein:
the delay network is further configured to generate a second delayed clock signal from the first delayed clock signal such that that the second delayed clock signal is delayed with respect to the first delayed clock signal; and
the second Muller C element is configured to receive the global clock signal and the second delayed clock signal, wherein the second Muller C element is configured to:
generate a second clock input signal such that the second clock input signal is delayed with respect to the first clock input signal;
set the second clock input signal to one of a set of clock states in response to the second delayed clock signal and the global clock signal each being provided in a same one of the set of clock states; and
hold the second clock input signal in the one of the set of clock states in response to the second delayed clock signal and the global clock signal being provided in different ones of the set of clock states.
4. The radiation hardened digital circuit of claim 3, further comprising:
a first pulsed clock generator configured to generate a first pulsed clock signal from the first clock input signal;
a second pulsed clock generator configured to generate a second pulsed clock signal from the second clock input signal such that the second pulsed clock signal is delayed with respect to the first pulsed clock signal;
a first latch configured to receive the first pulsed clock signal and a first input bit signal having a first input bit state, the first latch is being configured to:
generate a first output bit signal;
sample the first input bit state to set a first output bit state of the first output bit signal based on the first input bit state in response to the first pulsed clock signal being in one of the set of clock states; and
hold the first output bit state while the first pulsed clock signal is in an other one of the set of clock states; and

a second latch configured to receive the second pulsed clock signal and the first input bit signal, the second latch is being configured to:
generate a second output bit signal;
sample the first input bit state to set a second output bit state of the second output bit signal based on the first input bit state in response to the second pulsed clock signal being in one of the set of clock states; and
hold the second output bit state while the second pulsed clock signal is in an other one of the set of clock states.
5. The radiation hardened digital circuit of claim 4 further comprising:
a third pulsed clock generator configured to receive the global clock signal and generate a third pulsed clock signal from the global clock signal; and
a third latch configured to receive the third pulsed clock signal and the first input bit signal, the third latch is being configured to:
generate a third output bit signal;
sample the first input bit state to set a third output bit state of the third output bit signal based on the first input bit state in response to the third pulsed clock signal being in one of the set of clock states; and
hold the third output bit state while the third pulsed clock signal is in an other one of the set of clock states.
6. The radiation hardened digital circuit of claim 5 further comprising a majority gate configured to receive the first output bit signal, the second output bit signal, and the third output bit signal wherein the majority gate is configured to generate a first resultant output bit signal set to a majority bit state of the first output bit state, the second output bit state, and the third output bit state.
7. The radiation hardened digital circuit of claim 6 further comprising a first delay element configured to receive the global clock signal and generate the first delayed clock signal from the global clock signal.
8. The radiation hardened digital circuit of claim 7 further comprising a second delay element configured to receive the first delayed clock signal and generate the second delayed clock signal from the first delayed clock signal.
9. The radiation hardened digital circuit of claim 8 wherein the first delay element and the second delay element are identical.
10. The radiation hardened digital circuit of claim 4 further comprising a global clock tree wherein the first Muller C element and the second Muller C element are coupled to the first pulsed clock generator and the second pulsed clock generator through the global clock tree.
11. The radiation hardened digital circuit of claim 3 further comprising a third Muller C element wherein:
the delay network is further configured to generate a third delayed clock signal from the second delayed clock signal such that that the third delayed clock signal is delayed with respect to the third delayed clock signal; and
the third Muller C element is configured to receive the global clock signal and the third delayed clock signal, wherein the third Muller C element is configured to:
generate a third clock input signal such that the third clock input signal is delayed with respect to the second clock input signal;
set the third clock input signal to one of a set of clock states in response to the third delayed clock signal and the global clock signal each being provided in a same one of the set of clock states; and
hold the third clock input signal in the one of the set of clock states in response to the third delayed clock signal and the global clock signal being provided in different ones of the set of clock states.
12. The radiation hardened digital circuit of claim 11, further comprising:
a first pulsed clock generator configured to generate a first pulsed clock signal from the first clock input signal;
a second pulsed clock generator configured to generate a second pulsed clock signal from the second clock input signal such that the second pulsed clock signal is delayed with respect to the first pulsed clock signal;
a third pulsed clock generator configured to generate a third pulsed clock signal from the third clock input signal such that the third pulsed clock signal is delayed with respect to the second pulsed clock signal;
a first latch configured to receive the first pulsed clock signal and a first input bit signal having a first input bit state, the first latch is being configured to:
generate a first output bit signal;
sample the first input bit state to set a first output bit state of the first output bit signal based on the first input bit state in response to the first pulsed clock signal being in one of the set of clock states; and
hold the first output bit state while the first pulsed clock signal is in an other one of the set of clock states;

a second latch configured to receive the second pulsed clock signal and the first input bit signal, the second latch is being configured to:
generate a second output bit signal;
sample the first input bit state to set a second output bit state of the second output bit signal based on the first input bit state in response to the second pulsed clock signal being in one of the set of clock states; and
hold the second output bit state while the second pulsed clock signal is in an other one of the set of clock states; and

a third latch configured to receive the third pulsed clock signal and the first input bit signal, the third latch is being configured to:
generate a third output bit signal;
sample the first input bit state to set a third output bit state of the third output bit signal based on the first input bit state in response to the third pulsed clock signal being in one of the set of clock states; and
hold the third output bit state while the third pulsed clock signal is in an other one of the set of clock states.
13. The radiation hardened digital circuit of claim 12 further comprising a majority gate configured to receive the first output bit signal, the second output bit signal, and the third output bit signal wherein the majority gate is configured to generate a first resultant output bit signal set to a majority bit state of the first output bit state, the second output bit state, and the third output bit state.
14. The radiation hardened digital circuit of claim 13 further comprising a first delay element configured to receive the global clock signal and generate the first delayed clock signal from the global clock signal.
15. The radiation hardened digital circuit of claim 14 further comprising a second delay element configured to receive the first delayed clock signal and generate the second delayed clock signal from the first delayed clock signal.
16. The radiation hardened digital circuit of claim 15 further comprising a third delay element configured to receive the second delayed clock signal and generate the third delayed clock signal from the second delayed clock signal.
17. The radiation hardened digital circuit of claim 16 wherein the first delay element, the second delay element, and the third delay element are identical.
18. The radiation hardened digital circuit of claim 16 further comprising a global clock tree wherein the first delay element, the first Muller C element, the second Muller C element, the third Muller C element are each configured to receive the global clock signal through the global clock tree.
19. The radiation hardened digital circuit of claim 18 further comprising a global clock circuit coupled to the global clock tree and configured to generate the global clock circuit.
20. The radiation hardened digital circuit of claim 19 wherein the delay network, the first Muller C element, the second Muller C element, the third Muller C element, the first pulsed clock generator, the second pulsed clock generator, the third pulsed clock generator, the first latch, the second latch, the third latch, and the majority gate are each provided in a sequential state circuit.

1. A method for recovering iodine, which comprises:
feeding (a) an iodine-containing solution containing iodine, an iodine compound, or a mixture thereof, and (b) at least one solution selected from the group consisting of a basic alkali metal compound solution and a basic alkaline earth metal compound solution separately to a roasting furnace, without premixing (a) and (b), through a different pipeline and from a different feed opening;
burning a combustible material so as to provide a heat treatment in said roasting furnace; and
absorbing a component obtained by said heat treatment with water or an aqueous solution.
2. The method for recovering iodine according to claim 1, wherein said iodine-containing solution is at least one member selected from the group consisting of an organic iodine-containing solution, an acidic iodine-containing solution, and a basic iodine-containing solution.
3. The method for recovering iodine according to claim 1, wherein said (b) at least one solution selected from the group consisting of the basic alkali metal compound solution and the basic alkaline earth metal compound solution is a solution comprising at least one member selected from the group consisting of sodium hydroxide, potassium hydroxide, sodium carbonate, potassium carbonate, calcium hydroxide and barium hydroxide.
4. The method for recovering iodine according to claim 1, which comprises controlling amounts of the basic iodine-containing solution or (b) at least one solution selected from the group consisting of the basic alkali metal compound solution and the basic alkaline earth metal compound solution as an alkaline component to be fed to the roasting furnace so that pH of the aqueous solution absorbing the component obtained by the heat treatment becomes 4 or more.
5. The method for recovering iodine according to claim 1, wherein pH of the aqueous solution absorbing the component obtained by the heat treatment is 4 or more.
6. The method for recovering iodine according to claim 1, wherein one member selected from the group consisting of heavy oil, light oil, kerosene, naphtha, natural gas, liquefied petroleum gas, methanol and a mixture thereof is fed as a combustion fuel for the roasting furnace.
7. The method for recovering iodine according to claim 1, wherein both of the combustion and the iodine recovery are continuously carried out by removing some parts of said aqueous solution to outside of the system, while shortage of said aqueous solution is offset by adding fresh water instead in order to maintain specific gravity of the aqueous solution in a range from 1.0 to 1.3.
8. The method for recovering iodine according to claim 1, wherein at least one iodine-containing solution and further (b) at least one solution selected from the group consisting of the basic alkali metal compound solution and the basic alkaline earth metal compound solution, if necessary, are fed to the roasting furnace, which is maintained at a temperature of 800\xb0 C. or higher by combusting the combustion fuel.
9. The method for recovering iodine according to claim 1, wherein by the heat treatment in the roasting furnace, an iodine component is immobilized to a stable iodine salt with the alkali metal or the alkaline earth metal in at least one solution selected from the group consisting of the basic alkali metal compound solution, the basic alkaline earth metal compound solution and the basic iodine-containing solution.
10. The method for recovering iodine according to claim 1, wherein (1) a fractionally recovered organic iodine-containing solution, (2) a fractionally recovered acidic iodine-containing solution, (3) a fractionally recovered basic iodine-containing solution, and (4) at least one solution selected from the group consisting of the basic alkali metal compound solution and the basic alkaline earth metal compound solution are each fed in a mist state by spraying using spraying air, combustion air, or a mixture thereof into the roasting furnace.
11. The method for recovering iodine according to claim 1, wherein said iodine-containing solution is in a liquid state as it is when the iodine-containing material containing iodine or iodine compound is in a state of solution, and in a dissolved state in a solvent when the iodine-containing material containing iodine or iodine compound is in a state of solid.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for drive management and data placement in an archival storage system which includes a set of drives, said method comprising:
mapping a plurality of redundant data stripes onto the set of drives;
selecting a first active data stripe from the plurality of redundant data stripes, the first active data stripe being located on a first subset of the set of drives;
placing the first subset into a first power state;
placing a second subset of the set of drives into a second power state, the second power state being a lower power state than the first power state; and
writing a first set of data to the first active data stripe, when the first active data stripe contains an amount of data that is smaller than a maximum data capacity value of the first active data stripe, selecting a second active data stripe from the plurality of redundant data stripes, the second active data stripe being located on a third subset of the set of drives, the third subset including at least one drive of the second subset, wherein the selected second active data stripe is selected via implementation of an algorithm, and is selected based upon degree of overlap between the second active data stripe and the first active data stripe for promoting increased power efficiency of the archival storage system.
2. A method as claimed in claim 1, further comprising:
placing the at least one drive of the second subset into the first power state.
3. A method as claimed in claim 2, further comprising:
reserving a cache area on the third subset.
4. A method as claimed in claim 3, further comprising:
providing a copy of a portion of the first set of data of the first active data stripe to the cache area on the third subset.
5. A method as claimed in claim 4, further comprising:
placing at least one drive of the first subset into the second power state.
6. A method as claimed in claim 5, further comprising:
writing a second set of data to the second active data stripe.
7. A method as claimed in claim 6, further comprising:
receiving a read request, the read request requesting data segments included in the copy of the data portion stored in the cache.
8. A method as claimed in claim 7, further comprising:
retrieving the requested data segments from the copy of the data portion stored in the cache area and providing the retrieved requested data segments responsive to said read request via transmission over a network.
9. A method as claimed in claim 1, wherein the selected second active data stripe is selected via implementation of Controlled Replication Under Scalable Hashing.
10. An archival storage system, comprising:
a set of disk drives;
means for mapping a plurality of redundant data stripes onto the set of drives;
means for selecting a first active data stripe from the plurality of redundant data stripes, the first active data stripe being located on a first subset of the set of drives;
means for placing the first subset into a first power state;
means for placing a second subset of the set of drives into a second power state, the second power state being a lower power state than the first power state;
means for writing data to the first active data stripe on the first subset; and
when at least a portion of the data has been written to the first active data stripe and the portion of the data is smaller than a maximum data capacity value of the first active data stripe, implementing Controlled Replication Under Scalable Hashing to select a second active data stripe from the plurality of redundant data stripes, the second active data stripe being located on a third subset of the set of drives, the third subset including at least one drive of the second subset, wherein the system implements Massive Array of Independent Disks techniques for drive management and implements Controlled Replication Under Scalable Hashing for data placement.