1. The method for repairing a damaged area on a surface of a vinylplastic panel comprising the steps of:
cleaning the surface;
identifying gross surface imperfections that extend outward from the outer surface;
melting the gross surface imperfections such that high points are reduced and low points are filled;
sanding the surface of the damaged area such that the damaged area is lower that the original surface;
cleaning the surface of the sanded damaged area;
filling the damaged area;
sanding the filled damaged area;
cleaning the surface of the damaged area;
allowing the damaged area to dry;
sealing the surface of the damaged area;
filling in minor imperfections in the surface of the damaged area;
sanding the sealed damaged area;
cleaning the damaged area; and
painting the damaged area such that the color and texture of the painted damaged area match the original color and texture of the plasticvinyl panel.
2. The method of claim 1 wherein the low points are filled with molten plastic material from the panel.
3. The method of claim 1 wherein when the surface of the damaged area is sanded such that it is lower that the original surface, the abrasive used for the sanding is 220-grit or finer.
4. The method of claim 3 wherein a dual-oscillating sander is used for sanding the surface of the damaged area.
5. The method of claim 1 wherein the surface of the damaged area is cleaned using 2000-grit wet sanding abrasive.
6. The method of claim 5 wherein the surface of the damaged area is cleaned using the equivalent of a 2000-grit wet sanding abrasive.
7. The method of claim 1 wherein the damaged area is filled using a urethane based polyester spot putty and the putty is allowed to cure before the filled damaged area is sanded.
8. The method of claim 1 wherein the filled damaged area is sanded first with a 220-grit abrasive and then finish sanded with a 320 grit abrasive.
9. The method of claim 8 where a dual-oscillating sander is used for sanding the filled damaged area.
10. The method of claim 1 wherein the surface of the damaged area is sealed by applying a first coat of non-lacquer based primer and the minor surface imperfections are filled by applying a second coat of the primer.
11. The method of claim 1 wherein the sealed damaged area is sanded with a 600-grit abrasive.
12. The method of claim 11 where a dual-oscillating sander is used for sanding the sealed damaged area.
13. The method of claim 1 wherein the damaged area is painted with a urethane based vinyl resin that is tinted to match the original color of the vinylplastic panel.
14. The method of claim 13 wherein the amount of tint in the vinyl resin does not exceed ten grams of tint for every twenty-four grams of resin.
15. The method of claim 13 wherein the damaged area is painted with a first medium-wet coat of paint, then a second medium wet coat that is over-sprayed to blend the texture of the paint with the original texture of the vinylplastic panel; and
sufficient subsequent coats of paint such that the color and texture of the painted damaged area match the original color and texture of the plasticvinyl panel.
16. The method of claim 13 wherein the vinyl resin is applied using a high pressure low volume spray gun having a one millimeter tip, wherein the spray gun is pneumatic and the air pressure for operating the spay gun can be adjusted.
17. The method of claim 16 wherein the vinyl resin is applied using an air pressure less than thirty pounds per square inch for the spray gun.
18. The method of claim 16 wherein the distance between the spray gun and the vinylplastic panel during application of the resin is at least eight inches.
19. The method of claim 16 wherein the distance between the spray gun and the vinylplastic panel during application of the resin is greater than eight inches.
20. The method for repairing a damaged area on a surface of a vinylplastic bumper of a motor vehicle comprising the steps of:
cleaning the surface;
identifying gross surface imperfections that extend outward from the outer surface;
melting the gross surface imperfections such that high points are reduced and low points are filled with molten material from the bumper;
sanding the surface of the damaged area using an abrasive that is no coarser than 220-grit such that the damaged area is lower that the original surface;
cleaning the surface of the sanded damaged area by wet sanding it with a 2000-grit abrasive;
filling the damaged area using a non-lacquer based putty;
allowing the putty to cure;
sanding the filled damaged area are using an abrasive that is no coarser than 220-grit such that the damaged area is level with the remainder of the bumper;
sanding the filled damaged area are using an abrasive that is no coarser than 320-grit such that the damaged area is relatively smooth;
cleaning the surface of the damaged area;
allowing the damaged area to dry;
sealing the surface of the damaged area with a first thin coat of non-lacquer based primer that is applied with a pneumatic spray gun;
filling in minor imperfections in the surface of the damaged area with a second coat of primer that is thicker than the first thin coat of primer and is also applied with a pneumatic spray gun;
allowing the primed area to dry
sanding the sealed damaged area using an abrasive that is no coarser than 600-grit such that the damaged area is relatively smooth;
cleaning the damaged area;
painting the damaged area by applying a first medium-wet coat of a urethane based vinyl resin that is tinted to match the color of the vinylplastic bumper
using a high pressure low volume pneumatic spray gun having a spray nozzle no smaller than one millimeter and wherein the air pressure for operating the spray gun can be adjusted;
applying a second medium-wet coat of the urethane based vinyl resin that is over sprayed such that the texture of the paint is blended with the original texture of the vinylplastic bumper; and
applying sufficient subsequent coats of the urethane based vinyl resin such that the color and texture of the painted damaged area match the original color and texture of the plasticvinyl panel.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. For use in a programmable logic device having a plurality of specialized processing blocks, each of said specialized processing blocks having at least four n-by-n multipliers arranged in four-multiplier units, a method of performing a signed 3n-by-3n multiplication operation, said method comprising:
performing a 2n-by-2n multiplication using four of said n-by-n multipliers in a first of said four-multiplier units;
performing an n-by-n multiplication using one of said n-by-n multipliers in a second of said four-multiplier units; and
performing first and second 2n-by-n multiplications in a third of said four-multiplier units, using two of said n-by-n multipliers for each of said 2n-by-n multiplications; wherein:
in each of said multiplications, multiplicands representing n most significant bits are treated as signed operands and multiplicands representing n least significant bits are forced to be unsigned; said method further comprising:
shifting a second partial product of each of said 2n-by-n multiplications to align it with a first partial product of each of said 2n-by-n multiplications for addition within said third four-multiplier unit; and
adding results of said multiplications from said first, second and third four-multiplier units.
2. The method of claim 1 wherein said adding comprises adding said results in general-purpose programmable logic of said programmable logic device.
3. The method of claim 2 wherein:
said performing first and second 2n-by-n multiplications comprises, for each respective one of said first and second 2n-by-n multiplications:
performing a respective most significant bit multiplication using one said multiplier in said third four-multiplier unit to form a respective most significant bit partial product, and
performing a respective least significant bit multiplication using another said multiplier in said third four-multiplier unit to form a respective least significant bit partial product;
said shifting comprises shifting each respective most significant bit partial product to the left without shifting either respective least significant bit partial product; and
said addition within said third four-multiplier unit excludes further shifting of partial products.
4. The method of claim 3 further comprising selecting control signals to perform said shifting and said addition without further shifting.
5. The method of claim 1 wherein each said specialized processing block comprises two said four-multiplier units.
6. A programmable logic device having a plurality of specialized processing blocks, each of said specialized processing blocks having at least four n-by-n multipliers arranged in four-multiplier units, said programmable logic device being configured to perform a signed 3n-by-3n multiplication operation and comprising:
four of said n-by-n multipliers in a first of said four-multiplier units configured to perform a 2n-by-2n multiplication;
one of said n-by-n multipliers in a second of said four-multiplier units configured to perform an n-by-n multiplication;
a third of said four-multiplier units configured to perform first and second 2n-by-n multiplications, using two of said n-by-n multipliers for each of said 2n-by-n multiplications;
circuitry at multiplicand inputs of at least one of said multipliers for selectably forcing at least one of said inputs to be unsigned;
a shifter configured to shift a second partial product of each of said 2n-by-n multiplications to align it with a first partial product of each of said 2n-by-n multiplications for addition within said third four-multiplier unit; and
circuitry configured to add results of said multiplications from said first, second and third four-multiplier units.
7. The configured programmable logic device of claim 6 wherein said adding comprises adding said results in general-purpose programmable logic of said programmable logic device.
8. The configured programmable logic device of claim 7 wherein:
said programmable logic device is configured to perform said first and second 2n-by-n multiplications by, for each respective one of said first and second 2n-by-n multiplications:
performing a respective most significant bit multiplication using one said multiplier in said third four-multiplier unit to form a respective most significant bit partial product, and
performing a respective least significant bit multiplication using another said multiplier in said third four-multiplier unit to form a respective least significant bit partial product;
said programmable logic device is configured to shift each respective most significant bit partial product to the left without shifting either respective least significant bit partial product; and
said circuitry configured to add excludes further shifting of partial products.
9. The configured programmable logic device of claim 8 further comprising selectors responsive to selection control signals to perform said shifting and said addition without further shifting.
10. The configured programmable logic device of claim 6 wherein each said specialized processing block comprises two said four-multiplier units.
11. The configured programmable logic device of claim 10 wherein said circuitry configured to add is located substantially within one said specialized processing block.
12. The configured programmable logic device of claim 6 wherein said circuitry for selectably forcing at least one of said inputs to be unsigned comprises a multiplexer at said multiplicand input, said multiplexer controllably selecting, for input to a sign control input associated with said multiplicand input, between a first signal forcing said multiplicand input to be unsigned, and a second signal representing sign information for said multiplicand input.
13. The configured programmable logic device of claim 6 wherein said circuitry for selectably forcing at least one of said inputs to be unsigned comprises one said multiplexer at at least one multiplicand input of each said multiplier.
14. The configured programmable logic device of claim 13 wherein said circuitry for selectably forcing at least one of said inputs to be unsigned comprises one said multiplexer at each multiplicand input of each said multiplier.
15. A data storage medium encoded with machine-executable instructions for performing a method of programmably configuring a programmable logic device to perform a signed 3n-by-3n multiplication operation, wherein said programmable logic device has a plurality of specialized processing blocks, each of said specialized processing blocks having at least four n-by-n multipliers arranged in four-multiplier units, said instructions comprising:
instructions for configuring four of said n-by-n multipliers in a first of said four-multiplier units to perform a 2n-by-2n multiplication;
instructions for configuring one of said n-by-n multipliers in a second of said four-multiplier units to perform an n-by-n multiplication;
instructions for configuring a third of said four-multiplier units to perform first and second 2n-by-n multiplications, using two of said n-by-n multipliers for each of said 2n-by-n multiplications;
instructions for configuring multiplicand inputs in any of said multiplications to be selectably treatable as signed operands or unsigned operands;
instructions for configuring a shifter to shift a second partial product of each of said 2n-by-n multiplications to align it with a first partial product of each of said 2n-by-n multiplications for addition within said third four-multiplier unit; and
instructions for configuring circuitry to add results of said multiplications from said first, second and third four-multiplier units.
16. The data storage medium of claim 15 wherein said instructions for configuring circuitry to add comprise instructions for configuring general-purpose programmable logic of said programmable logic device to add said results.
17. The data storage medium of claim 16 comprising:
instructions to configure said programmable logic device to perform said first and second 2n-by-n multiplications including, for each respective one of said first and second 2n-by-n multiplications:
instructions to configure said programmable logic device to perform a respective most significant bit multiplication using one said multiplier in said third four-multiplier unit to form a respective most significant bit partial product, and
instructions to configure said programmable logic device to perform a respective least significant bit multiplication using another said multiplier in said third four-multiplier unit to form a respective least significant bit partial product; and
instructions to configure said programmable logic device to perform to shift each respective most significant bit partial product to the left without shifting either respective least significant bit partial product; wherein:
said instructions to configure said circuitry to add excludes further shifting of partial products.
18. The data storage medium of claim 17 wherein said instructions further comprise instructions to configure selectors responsive to selection control signals to perform said shifting and said addition without further shifting.
19. The data storage medium of claim 15 wherein said instructions are for configuring a programmable logic device wherein each said specialized processing block comprises two said four-multiplier units.
20. The data storage medium of claim 19 wherein said instructions configure said circuitry to add substantially within one said specialized processing block.
21. The data storage medium of claim 15 wherein said instructions for configuring multiplicand inputs in any of said multiplications to be selectably treatable as signed operands or unsigned operands include instructions for configuring a respective multiplexer at each respective said multiplicand input, each said respective multiplexer being configured to controllably select, for input to a sign control input associated with said respective multiplicand input, between a first signal forcing said multiplicand input to be unsigned, and a second signal representing sign information for said multiplicand input.