All The Claims

1. A silicon-on-insulator metal oxide semiconductor device comprising:
an ultrathin silicon layer on a sapphire substrate;
at least one P-channel MOS transistor formed in the ultrathin silicon layer;
N-type impurity implanted within the ultrathin silicon layer and the sapphire substrate such that peak N-type impurity concentration in the sapphire substrate is at least 10 times greater than peak impurity concentration in the ultrathin silicon layer.
2. The device of claim 1,
wherein the N-type impurity implanted within the sapphire substrate has a peak concentration disposed at least 0.05 microns from a silicon-sapphire back interface.
3. The device of claim 1,
wherein the peak N-type impurity concentration within the sapphire substrate is approximately 1.0\xd71019 ionscm2.
4. A silicon-on-insulator metal oxide semiconductor device comprising:
an ultrathin silicon layer on a sapphire substrate;
at least one P-channel MOS transistor formed in the ultrathin silicon layer;
N-type impurity implanted within the sapphire substrate such that peak N-type impurity concentration within the sapphire substrate is disposed at least 0.05 microns from a silicon-sapphire back interface.
5. The device of claim 4,
wherein the N-type impurity implanted within the sapphire substrate has a peak impurity concentration disposed at least 0.10 microns from a silicon-sapphire back interface.
6. The device of claim 4,
wherein the peak N-type impurity concentration within the sapphire substrate is approximately 1.0\xd71019 ionscm2.
7. A silicon-on-insulator metal oxide semiconductor device comprising:
an ultrathin silicon layer on a sapphire substrate;
at least one P-channel MOS transistor formed in the ultrathin silicon layer;
N-type impurity implanted within the ultrathin silicon layer and the sapphire substrate such that peak N-type impurity concentration of approximately 1.0\xd71019 ionscm2in the sapphire layer, which is at least 10 times greater than peak impurity concentration in the ultrathin silicon layer and which is disposed at least 0.05 microns from a silicon-sapphire back interface.
8. A silicon-on-insulator metal oxide semiconductor device comprising:
an ultrathin silicon layer on a sapphire substrate;
at least one P-channel MOS transistor formed in the ultrathin silicon layer;
wherein the ultrathin silicon layer is characterized by a retrograde N-type dopant concentration profile in the P-channel region;
wherein the sapphire substrate is characterized by a retrograde N-type dopant concentration in the sapphire substrate opposite the P-channel region; and
wherein peak N-type dopant concentration is at least 10 times higher in the sapphire substrate than peak N-type dopant concentration in the P-channel region.
9. The device of claim 8 further including:
an interface region in which the ultrathin silicon layer adjoins the sapphire substrate;
wherein the retrograde N-type dopant concentration profile in the P-channel region the retrograde N-type dopant concentration profile in the sapphire substrate opposite the P-channel region together form a retrograde N-type dopant concentration profile across the P-channel region, the interface region and the sapphire substrate opposite the P-channel region.
10. The device of claim 8,
an interface region in which the ultrathin silicon layer adjoins the sapphire substrate;
wherein the retrograde N-type dopant concentration in the sapphire substrate increases with increasing distance from the interface region up to a peak concentration region and trails off after the peak concentration region, with increasing distance from the interface region.
11. A silicon-on-insulator metal oxide semiconductor device comprising:
an ultrathin silicon layer on a sapphire substrate;
at least one P-channel MOS transistor formed in the ultrathin silicon layer;
wherein the ultrathin silicon layer is characterized by a retrograde N-type dopant concentration profile in the P-channel region;
wherein the sapphire substrate is characterized by a retrograde N-type dopant concentration in the sapphire substrate opposite the P-channel region; and
wherein peak N-type dopant concentration is in the sapphire substrate and is disposed at least 0.05 microns from a silicon-sapphire back interface.
12. The device of claim 11 further including:
an interface region in which the ultrathin silicon layer adjoins the sapphire substrate;
wherein the retrograde N-type dopant concentration profile in the P-channel region the retrograde N-type dopant concentration profile in the sapphire substrate opposite the P-channel region together form a retrograde N-type dopant concentration profile across the P-channel region, the interface region and the sapphire substrate opposite the P-channel region.
13. The device of claim 11,
an interface region in which the ultrathin silicon layer adjoins the sapphire substrate;
wherein the retrograde N-type dopant concentration in the sapphire substrate increases with increasing distance from the interface region up to a peak concentration region and trails off after the peak concentration region, with increasing distance from the interface region.
14. The device of claim 1 further including:
an N-type threshold voltage setting implant in the P-channel region.
15. The device of claim 1 further including:
an interface region in which the ultrathin silicon layer adjoins the sapphire substrate;
wherein the retrograde N-type dopant concentration profile in the P-channel region is substantially continuous with the retrograde N-type dopant concentration profile in the sapphire substrate opposite the P-channel region so as to form a substantially continuous N-type dopant concentration profile across the P-channel region, the interface region and the sapphire substrate opposite the P-channel region;
wherein the retrograde N-type dopant concentration in the sapphire substrate increases with increasing distance from the interface region up to a peak concentration region, which is at prescribed distance from the interface region, and trails off after the peak concentration region, with increasing distance from the interface region; and
wherein the prescribed distance is selected to be far enough from the interface region that radiation-induced charge that may become trapped does not produce an inversion region near the interface region.
16. A device according to claim 1 or 4,
wherein the N-channel dopant is selected from the group consisting of phosphorous, arsenic and antimony.
17. A device according to claim 1 or 4 further including:
an N-channel device interconnected with the P-channel device to from a CMOS device.
18. The device of claim 1 or 4,
wherein respective source and drain regions of the P-channel device extend to a silicon-sapphire interface.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A system that facilitates augmenting reality, comprising:
a processor;
a memory;
an information gathering component stored in the memory and executed by the processor having a reality monitor component that gathers real-world data for at least one real-world object and a query component stored in the memory and executed by the processor that establishes a query based at least in part on context-related information for the real-world data, the query providing access to virtual-world data supplied by one or more remote sources; and
an interface component stored in the memory and executed by the processor and configured to receive at least a portion of the real-world data and the virtual-world data from the information gathering component, the interface component having a consolidation component that aggregates the received real-world and virtual-world data, the interface component establishes, in real-time, an augmented-reality experience in which at least a portion of the received real-world data is overlaid with at least a portion of the received virtual-world data.
2. The system of claim 1, the aggregated data includes virtual data related to a plurality of objects viewed by a user.
3. The system of claim 2, the aggregated data includes contextual data related to a subset of the plurality of objects.
4. The system of claim 3, the contextual data includes one of activity context data, user context data or environment context data.
5. The system of claim 1, the reality monitor component employs a sensor component to gather the context-related information.
6. The system of claim 5, the sensor component is at least one of an environmental or physiological sensor.
7. The system of claim 1, the consolidation component further comprising:
an analysis component that analyzes the real-world data and the virtual-world data; and
an aggregation component that combines the real-world data with a subset of the virtual-world data based upon contextual data.
8. The system of claim 1, further comprising a rendering component that personalizes the augmented-reality experience based upon one of user preference, user policy, or context.
9. The system of claim 8, further comprising a configuration component that organizes the augmented-reality experience based upon at least one of user preference, user policy, or user context.
10. The system of claim 8, further comprising a filter component that filters virtual data for inclusion within the augmented-reality experience based upon at least one of user preference, user policy, or user context.
11. The system of claim 1, further comprising a machine learning and reasoning component that employs at least one of a probabilistic and a statistical-based analysis that infers an action that a user desires to be automatically performed.
12. A computer-implemented method of augmenting reality, comprising:
monitoring a plurality of real-world objects;
gathering virtual information related to at least one of the plurality of real-world objects, the virtual information supplied by one or more remote sources in response to at least one query and separate from the real-world objects;
implementing a machine learning and reasoning component that employs at least one of a probabilistic and a statistical-based analysis that infers an action that a user desires to be automatically performed; and
augmenting reality via aggregating the virtual information with the at least one of the plurality of real-world objects in accordance with the inferred action.
13. The method of claim 12, further comprising rendering the augmented reality to a user based upon one of a context, policy or preference.
14. The method of claim 13, wherein the context is at least one of activity context, user context or environment context.
15. The method of claim 12, further comprising:
filtering the augmented reality based upon a context; and
rendering the filtered augmented reality.
16. A computer-executable system comprising:
means for machine learning and reasoning to infer an action that a user desires to be automatically performed;
means for monitoring contextual objects related to a user;
means for gathering virtual objects, the virtual objects provided from one or more remote sources in response to at least one query and obtained separately from the contextual objects;
means for aggregating the virtual objects with a subset of the contextual objects; and
means for rendering the aggregation to a user in accordance with the inferred action.
17. The computer-executable system of claim 16, further comprising means for gathering the virtual objects.

1. A method of packaging and mounting a quartz SAW sensor having at least two SAW devices electrically connected to each other on to a shaft, comprising the steps of:
providing a glass cover wafer having a diameter substantially the same as said quartz SAW sensor;
adding a glass frit paste having a desired pattern on said glass cover wafer to form a pattern of glass frit spacers and thereafter pre-consolidating said glass frit paste, said glass frit spacers having a TCE substantially the same as said glass cover wafer;
aligning of said glass cover wafer on said SAW sensor and making direct contact there between to thereby isolate said glass cover wafer and said SAW sensor by said glass frit spacers, said glass frit spacers further isolating said at least two SAW devices;
consolidating said glass frit paste at a temperature below the Curie temperature of said quartz SAW sensor to form consolidated solid glass material;
slicing said glass cover wafer to expose said at least two SAW devices for making electrical contact therewith;
thereafter directly attaching the back of said quartz SAW sensor to a shaft by applying a gel phase of a glass frit composition to a place on said shaft and consolidating said gel phase to a cured glass frit, said glass frit composition having a TCE bridging the TCE of said shaft and the TCE of said back of said quartz SAW sensor; and
bonding said back of said quartz SAW sensor to said glass frit composition.
2. The method of claim 1, wherein said glass frit composition has a TCE intermediate of the TCE of said shaft and the TCE of said quartz sensor back.
3. The method of claim 1, wherein said glass frit composition when consolidated to a glass is from about 30 to 50 micrometers in thickness and said desired pattern is applied by direct printing.
4. The method of claim 1, wherein said glass frit composition comprises a first composition applied directly to said shaft and having a TCE near said TCE of said shaft and a second composition applied to said first composition and having a TCE near said TCE of said quartz sensor back, said quartz sensor back being applied to said second composition.
5. The method of claim 4, wherein said first composition of said glass frit is a metal-like glass frit layer formed from a mixture of metal oxide powder and silica powder.
6. The method of claim 5, wherein said second composition of said glass frit is a silica glass frit having a TCE substantially equal to the average TCE of said quartz sensor back.
7. A quartz SAW sensor having at least two SAW devices electrically connected to each other in a hermetic package and mounted on to a shaft, comprising:
a quartz SAW sensor;
a glass cover wafer having a diameter substantially the same as said quartz SAW sensor;
a glass frit paste having a desired pattern placed on said glass cover wafer to form a pattern of glass frit spacers, said glass frit spacers having a TCE substantially the same as said glass cover wafer;
said glass cover wafer being aligned on said SAW sensor and making direct contact there between after first pre-conditioning said glass frit paste to thereby isolate said glass cover wafer and said SAW sensor by said glass frit spacers, said glass frit spacers further isolating said at least two SAW devices;
said glass frit paste having been consolidated at a temperature below the Curie temperature of said quartz SAW sensor to form consolidated solid glass material;
said at least two SAW devices being exposed for making electrical contact therewith;
the back of said quartz SAW sensor being attached to a shaft by applying a gel phase of a glass frit composition to a place on said shaft and consolidating said gel phase to a cured glass frit, said glass frit composition having a TCE bridging the TCE of said shaft and the TCE of said back of said quartz SAW sensor; and
said back of said quartz SAW sensor being bonded to said glass frit composition.
8. The device of claim 7, wherein said glass frit composition has a TCE intermediate of the TCE of said shaft and the TCE of said quartz sensor back.
9. The device of claim 7, wherein said glass frit composition when consolidated to a glass is from about 30 to 50 micrometers in thickness.
10. The device of claim 7, wherein said glass frit composition comprises a first composition applied directly to said shaft and having a TCE near said TCE of said shaft and a second composition applied to said first composition and having a TCE near said TCE of said quartz sensor back, said quartz sensor back being applied to said second composition.
11. The device of claim 10, wherein said first composition of said glass frit is a metal-like glass frit layer formed from a mixture of metal oxide powder and silica powder.
12. The device of claim 11, wherein said second composition of said glass frit is a silica glass frit having a TCE substantially equal to the average TCE of said quartz sensor back.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A clock signal generating system for generating an output clock signal comprising:
a phase locked loop (PLL) circuit which requires a reference clock signal of at least a predetermined first frequency, an output of the PLL circuit being coupled to generate the output clock signal; and
a clock signal multiplication circuit having:
an oscillator;
a counter circuit that is clocked by an oscillator clock signal produced by the oscillator and that is coupled to receive a first clock signal of a second frequency that is substantially lower than the first frequency, wherein the counter circuit samples its contents in response to the first clock signal;
a clock filter and clock period estimator circuit that is coupled to receive the sampled contents of the counter circuit;
a first delta-sigma modulator that is coupled to receive an estimate which is representative of the period of the first clock signal multiplied by a ratio of the first frequency to the second frequency, and which is produced by the clock filter and clock period estimator circuit for producing an integer representation of the estimate;
a memory for receiving a predetermined number of the integer representations; and
a first divider circuit coupled to divide the oscillator clock signal by the predetermined number of the integer representations to generate a second clock signal which has a frequency at least as high as the first frequency, wherein the output clock signal is phase-locked with respect to the first clock signal, and wherein a reference clock input of the PLL circuit is coupled to receive the second clock signal.
2. The clock signal generating system of claim 1, wherein the clock signal multiplication circuit further comprises set up logic for providing a shift factor for the clock filter and clock period estimator circuit and a PLL multiplier factor for the PLL circuit in response to the sampled contents.
3. The clock signal generating system of claim 1, wherein the memory further comprises a first in, first out (FIFO) circuit coupled between an output of the first delta-sigma modulator and a divide input of the first divider circuit.
4. The clock signal generating system of claim 1, wherein the clock filter and clock period estimator circuit further comprises low pass filtering and period estimating circuitry.
5. The clock signal generating system of claim 2, wherein the clock filter and clock period estimator circuit further comprises:
a right-shift circuit having input coupled to receive the shift factor, and an output on which the estimate is produced; and
a left-shift circuit which has an input coupled to receive the estimate, another input coupled to receive the shift factor, and an output coupled by an accumulator circuit to a digital summer which also receives the sampled contents.
6. The clock signal generating system of claim 5, wherein the first delta sigma modulator performs 2S operations on the estimate, wherein S is the shift factor.
7. The clock signal generating system of claim 1, wherein the oscillator is a free-running oscillator.
8. The clock signal generating system of claim 1, wherein the clock signal multiplication circuit further comprises calibration circuitry for initially calibrating the oscillator to a predetermined frequency and then allowing the oscillator to run freely.
9. The clock signal generating system of claim 8, wherein the first delta sigma modulator has an architecture which ensures that the second clock signal is phase-locked with respect to the first clock signal.
10. The clock signal generating system of claim 2, wherein the clock signal multiplication circuit further comprises a second clock divider having an input coupled to an output of the PLL circuit and an output on which the output clock signal is produced.
11. The clock signal generating system of claim 1, wherein the oscillator is a programmable ring oscillator which receives a first control value that sets a nominal frequency of the oscillator clock signal which, after being divided by the first divider circuit, can be tolerated by the PLL circuit.
12. The clock signal generating system of claim 11, the clock signal multiplication circuit further comprises a second delta-sigma modulator which operates on a second control value to produce a digital value which is provided as a frequency multiplier factor input to the clock filter and clock period estimator circuit.
13. The clock signal generating system of claim 12, wherein the first delta sigma modulator further comprises an accumulator having an input coupled to an output of a quantizer which generates the integer representations, another input coupled to an accumulator reset signal, and an output which produces an estimate of a period of the first clock signal, the estimate of the period of the first clock signal being applied to a phase feedback accumulator input of the clock filter and clock period estimator circuit.
14. An apparatus comprising:
a clock signal multiplication circuit having:
an oscillator that generates an oscillator signal;
a counter circuit that is clocked by the oscillator signal and that receives a reference clock signal;
a filter and estimator circuit that is coupled to the counter circuit;
a delta-sigma modulator that is coupled to the filter and estimator circuit, wherein the delta-sigma modulator produces a plurality of integer representations of an estimate of the period of the reference clock signal multiplied by a ratio of the frequency of the reference clock signal to a predetermined frequency;
a memory that is coupled to the delta-sigma modulator that stores the integer representations; and
a divider that divides the oscillator signal by the integer representations; and

a PLL having a reference input that is coupled to the divider, wherein the predetermined frequency is a lower threshold frequency for the operation of the PLL.
15. The apparatus of claim 14, wherein the divider further comprises a first divider, and wherein apparatus further comprises a second divider that is coupled to the PLL.
16. The apparatus of claim 15, wherein the a clock signal multiplication circuit further comprises:
set up logic that provides shift factor to the a filter and estimator circuit and the delta-sigma modulator and that provides a multiplier factor to the PLL and the second divider; and
calibration logic that is coupled to the oscillator.
17. The apparatus of claim 15, wherein the memory is a FIFO memory.
18. A method comprising:
producing an estimate that is representative of a period of a first clock signal multiplied by a ratio of a predetermined frequency to a frequency of the first clock signal;
producing a plurality of integer representations of the estimate with a sigma-delta modulator;
storing the integer representations in a memory;
dividing an oscillator clock signal by each integer representation from the memory to generate a pulse which lasts during a number of cycles of the oscillator clock signal equal to the value of that integer representation so as to generate the second clock signal;
receiving the second clock signal at a reference clock input of a PLL, wherein the predetermined frequency is a lower threshold frequency for the operation of the PLL; and
generating an output clock signal with the PLL, wherein the output clock signal is phase-locked with respect to the first clock signal.
19. The method of claim 18, wherein the step of producing an estimate further comprises:
sampling the first clock signal with a counter circuit that is clocked by the oscillator clock signal; and
producing the estimate that is representative of a period of a first clock signal multiplied by a ratio of a predetermined frequency to a frequency of the first clock signal base at least in part on the sampling of the first clock signal.
20. The method of claim 19, wherein the method further comprises:
generating a shift factor for the sigma-delta modulator; and
generating a multiplier factor for the PLL.