All The Claims

1. A drying machine comprising:
a drum disposed in a cabinet to receive laundry;
an inlet channel configured to allow external air to be introduced into the drum therethrough;
a heater configured to heat air introduced into the inlet channel;
an outlet channel configured to allow air in the drum to be discharged out of the cabinet therethrough;
a circulating channel connected between the outlet channel and the heater such that at least a portion of air flowing through the outlet channel is introduced into the heater through the circulating channel before being discharged out of the cabinet and circulated into the drum; and
a condenser configured to condense the circulated air such that a humidity of air passing through the circulating channel is decreased, said condenser comprising first channel parts that allow the air introduced into the circulating channel to flow therethrough, and second channel parts that allow external air, necessary to take heat away from the air passing through the first channel parts, to flow therethrough.
2. The machine as set forth in claim 1, wherein the condenser further comprises:
an external air inlet duct that introduces external air from the outside of the cabinet;
an external air fan housing and an external air blowing fan that allows the external air having passed through the external air inlet duct to flow therethrough;
an external air guide duct that guides the external air having passed through the external air fan housing to the second channel parts; and
an external air outlet duct that guides the air having passed through the second channel parts to the outside of the cabinet.
3. A drying machine comprising:
a drum disposed in a cabinet to receive laundry;
an inlet channel configured to allow external air to be introduced into the drum therethrough;
a heater configured to heat air introduced into the inlet channel;
an outlet channel configured to allow air in the drum to be discharged out of the cabinet therethrough;
a circulating channel connected between the outlet channel and the heater such that at least a portion of air flowing through the outlet channel is introduced into the heater through the circulating channel before being discharged out of the cabinet and circulated into the drum; and
a condenser configured to condense the circulated air such that a humidity of air passing through the circulating channel is decreased, said condenser comprising a condensing duct that allows air introduced into the circulating channel to flow therethrough, and a cooling water supplying unit that supplies cooling water to the condensing duct to condense air passing through the condensing duct.
4. The machine as set forth in claim 3, wherein the cooling water supplying unit comprises:
a cooling water valve connected to an external hose that allows cooling water supplied from the external hose to flow therethrough or stopping the cooling water from flowing therethrough; and
a cooling water hose that guides cooling water having passed through the cooling water valve into the condensing duct.
5. The machine as set forth in claim 1, wherein the circulating channel consists of a circulating duct having one end communicating with one side of the outlet channel and the other end disposed in the front of the heater.
6. The machine as set forth in claim 5, wherein the circulating duct comprises:
a first circulating duct disposed between the side of the outlet channel and the condenser that guides the air having passed through the outlet channel to the condenser; and
a second circulating duct that guides the air having passed through the condenser to the heater.
7. The machine as set forth in claim 1, further comprising:
a blowing fan disposed in the outlet channel between a drum-side outlet part that allows air in the drum to flow to the outlet channel therethrough and one end of the circulating channel communicating with the outlet channel,
whereby air is distributed to the outlet channel and the circulating channel based on the exhaust resistance of air at the rear of the outlet channel.
8. The machine as set forth in claim 1, further comprising:
an air flow rate control unit disposed in the outlet channel that controls the flow rate of air passing through the outlet channel or the circulating channel.
9. The machine as set forth in claim 8, wherein the air flow rate control unit comprises:
an airflow rate control valve disposed in the outlet channel between a rear end of the outlet channel and one end of the circulating channel communicating with the outlet channel that controls the flow rate of air discharged through the outlet channel.
10. The machine as set forth in claim 9, wherein the air flow rate control valve comprises:
a plate body rotatably disposed in the outlet channel that opens or closes the outlet channel; and
a solenoid having a shaft for rotating the plate body.
11. The machine as set forth in claim 8, further comprising:
a temperature sensor that measures temperature of air discharged from the drum.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of performing a page mode operation in a semiconductor memory device comprising a plurality of memory cells, the method comprising:
generating a first clock signal upon detecting transition of a first address;
generating a second clock signal upon detecting transition of a second address following generation of the first clock signal;
receiving an internal start address and sequentially generating a plurality of access addresses by generating a current access address equal to the internal start address, wherein the internal start address comprises the first address and the second address, and the second address is a lower bit of the internal start address, and the memory cells in the plurality of memory cells are sequentially accessed by selection using the plurality of access addresses in response to at least the second clock signal; and then,
incrementing the current address in response to at least the second clock signal.
2. The method of claim 1, wherein the lower bit is a least significant bit of a start address corresponding to the internal start address.
3. The method of claim 1, wherein the page mode operation is a page mode read operation.
4. The method of claim 3, further comprising:
outputting data stored in the memory cells accessed by selection using the plurality of access addresses in response to transition of at least the second clock signal.
5. A method of performing a page mode operation in a semiconductor memory device comprising a plurality of memory cells, the method comprising:
generating a first clock signal upon detecting transition of a first address;
generating a second clock signal upon detecting transition of a second address following generation of the first clock signal;
generating a third clock signal before generation of the second clock signal;
receiving an internal start address and incrementing the internal start address to sequentially generate a plurality of access addresses by generating a current access address equal to the internal start address and then incrementing the current access address in response to respective transitions of at least the second and third clock signals;
wherein the internal start address comprises the first address and the second address, and the second address is a lower bit of the internal start address, and
the memory cells in the plurality of memory cells are sequentially accessed by selection using the plurality of access addresses in response to at least the second and third clock signals.
6. The method of claim 5, wherein the lower bit is the least significant bit of a start address corresponding to the internal start address.
7. The method of claim 5, wherein the page mode operation is a page mode read operation.
8. A method of performing a page mode operation in a semiconductor memory device comprising a plurality of memory cells, the method comprising:
receiving a start address and outputting an internal start address comprising a first address and a second address, wherein the second address is a lower bit of the internal start address;
receiving the first address and generating a first clock signal upon detecting transition of the first address;
receiving the second address and generating a second clock signal upon detecting transition of the second address following generation of the first clock signal; and
sequentially providing access addresses to a memory cell array to sequentially access memory cells in the memory cell array,
wherein upon receiving the internal start address, the access addresses are generated by generating a current access address equal to the internal start address and then incrementing the current access address in response to at least the second clock signal.

1. A flat panel display, comprising:
a display screen;
a base configured to support the display screen;
a stand coupled between the display screen and the base, wherein an upper end of the stand is pivotably connected to the display screen, and wherein a lower end of the stand is pivotably connected to the base; and
a clamping device configured to fix the stand with respect to the base when the stand is folded over the base.
2. The flat panel display of claim 1, further comprising a panel hinge coupled between the display screen and the stand to allow the display screen to pivot with respect to the stand.
3. The flat panel display of claim 2, further comprising a base hinge coupled between the stand and the base to allow the stand to pivot with respect to the base.
4. The flat panel display of claim 1, further comprising a base hinge coupled between the stand and the base to allow the stand to pivot with respect to the base.
5. The flat panel display of claim 1, wherein an opening is formed in the base, and wherein the opening is configured to receive the stand when the stand is folded over the base.
6. The flat panel display of claim 5, wherein a depth of the opening is approximately equal to a thickness of the stand.
7. The flat panel display of claim 1, wherein the clamping device comprises:
at least one fixing groove formed on one of the stand and the base; and
at least one fixing protrusion which is movably mounted on the other of the stand and the base, wherein each at least one fixing protrusion is configured to be moved into engagement with a corresponding fixing groove to fix the stand with respect to the base.
8. The flat panel display of claim 7, further comprising an operating unit that is coupled to the at least one fixing protrusion, wherein movement of the operating unit causes the at least one fixing protrusion to be moved into and out of engagement with a corresponding fixing groove.
9. The flat panel display of claim 8, wherein an operating lever of the operating unit protrudes from the flat panel display such that a user can push the operating lever to cause the operating unit to move.
10. The flat panel display of claim 9, wherein the at least one fixing protrusion and the operating unit are movably mounted on the base, wherein a guide groove is formed in the base, and wherein the operating lever protrudes through and is guided by the guide groove.
11. The flat panel display of claim 10, wherein at least one additional guide groove is formed on the operating unit, wherein at least one guide protrusion is, formed on the base, and where each guide protrusion is mounted in a corresponding additional guide groove to guide movement of the operating unit.
12. The flat panel display of claim 10, further comprising a stopper configured to limit movement of the operating unit.
13. The flat panel display of claim 12, wherein the stopper interacts with the operating lever to limit movement of the operating unit.
14. The flat panel display of claim 13, wherein the stopper comprises a leaf spring mounted on the base.
15. The flat panel display of claim 8, further comprising a stopper configured to limit movement of the operating unit.
16. The flat panel display of claim 15, wherein the stopper is configured to hold the operating unit in either a first position wherein the at least one fixing protrusion is not engaged in a corresponding fixing groove or a second position wherein the at least one fixing protrusion is engaged in a corresponding fixing groove.
17. The flat panel display of claim 16, wherein the stopper comprises an elastic member which is configured to be temporarily deformed to allow the operating unit to move between the first and second positions.
18. The flat panel display of claim 17, wherein the stopper comprises a leaf spring.
19. The flat panel display of claim 8, wherein an operating lever of the operating unit protrudes from a lower portion of the base.
20. The flat panel display of claim 8, further comprising:
at least one guide groove formed on one of the operating unit and the base; and
at least one guide protrusion formed on the other of the operating unit and the base, wherein each at least one guide protrusion is received in a corresponding guide groove to guide movement of the operating unit with respect to the base.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A DRAM memory structure, comprising:
a substrate;
a first strip semiconductor material disposed on said substrate and extending along a first direction;
a split gate disposed on said substrate, extending along a second direction and comprising independently a first block and a second block to divide said first strip semiconductor material into a first source terminal, a first drain terminal and a first channel region;
a first dielectric layer at least partially sandwiched between said split gate and said substrate;
a first gate dielectric layer at least partially sandwiched between said split gate and said strip semiconductor material; and
a first capacitor unit electrically connected to said first source terminal.
2. The DRAM memory structure of claim 1, wherein said substrate is a conductive Si substrate, an insulating Si substrate or the combination thereof.
3. The DRAM memory structure of claim 1, wherein said first direction is substantially perpendicular to said second direction.
4. The DRAM memory structure of claim 1, wherein said first direction crosses said second direction but said first direction is substantially not perpendicular to said second direction.
5. The DRAM memory structure of claim 1, wherein said first capacitor unit is disposed on said substrate and comprises said first source terminal serving as a bottom electrode, a second dielectric layer at least partially covering said first source terminal to serve as a capacitor dielectric layer, and a capacitor metal layer at least partially covering said second dielectric layer to serve as a top electrode.
6. The DRAM memory structure of claim 5, wherein said first dielectric layer and said second dielectric layer has one of a same high-k material and different high-k materials.
7. The DRAM memory structure of claim 5, wherein said second dielectric layer covers up to five sides of said first source terminal.
8. The DRAM memory structure of claim 5, wherein said capacitor metal layer completely covers said first source terminal.
9. The DRAM memory structure of claim 1, wherein one of said first block and said second block is a drive gate and the other one is a back gate.
10. The DRAM memory structure of claim 9, further comprising:
a word line electrically connected to said drive gate.
11. The DRAM memory structure of claim 9, further comprising:
a back line electrically connected to said back gate.
12. The DRAM memory structure of claim 1, wherein said first strip semiconductor material is higher than at least one of said first block and said second block.
13. The DRAM memory structure of claim 1, wherein at least one of said first block and said second block is higher than said first strip semiconductor material.
14. The DRAM memory structure of claim 1, wherein said split gate comprises a metal.
15. The DRAM memory structure of claim 1, wherein said first strip semiconductor material, said first source terminal and said first drain terminal are integrally formed.
16. The DRAM memory structure of claim 1, further comprising:
a bit line electrically connected to said first drain terminal.
17. The DRAM memory structure of claim 1, further comprising:
a second strip semiconductor material disposed on said substrate and extending along said first direction, wherein said split gate further comprises a third block so that said second block and said third block together divide said second strip semiconductor material into a second source terminal, a second drain terminal and a second channel region;
a second gate dielectric layer at least partially sandwiched between said split gate and said second strip semiconductor material; and
a second capacitor unit electrically connected to said second source terminal.
18. The DRAM memory structure of claim 17, wherein said second capacitor unit is disposed on said substrate and comprises said second source terminal serving as a bottom electrode, a second dielectric layer at least partially covering said second source terminal to serve as a second capacitor dielectric layer, and a capacitor metal layer at least partially covering said second dielectric layer to serve as a second top electrode, wherein said first source terminal is not in contact with said second source terminal.
19. The DRAM memory structure of claim 17, wherein said first strip semiconductor material, said second strip semiconductor material, said split gate, said first capacitor unit and said second capacitor unit together form a dynamic memory unit.
20. The DRAM memory structure of claim 19, wherein said first capacitor unit and said second capacitor unit together share a capacitor metal layer.
21. The DRAM memory structure of claim 19, wherein said first capacitor unit and said second capacitor unit together share a back gate.