All The Claims

1. A semiconductor memory device comprising:
a first memory block of a first type of memory; and
a second memory block of a second type of memory having a different type from the first type, wherein the first and second memory blocks are integrated in a unitary die;
wherein a first address region of the first memory block and a second address region of the second memory block are included in the same address domain,
wherein each of the first and second memory blocks is accessed by an address signal including an address of the address domain, and
wherein the second memory block is a nonvolatile memory.
2. The device of claim 1, wherein the same address domain refers to a set of consecutive addresses, wherein the addresses of the second address region immediately follow the addresses of the first address region.
3. The device of claim 1, wherein the first and second memory blocks are each driven by different AC parameters.
4. The device of claim 1, wherein the first memory block is configured as a system operating memory.
5. The device of claim 1, wherein the first memory block is a volatile memory.
6. The device of claim 5, wherein the first memory block includes a DRAM.
7. The device of claim 1, wherein the second memory block is configured as a memory for storing data.
8. The device of claim 1, wherein the nonvolatile memory includes one of a flash memory device, a Ferroelectric Random Access Memory (FeRAM), a Phase-change Random Access Memory (PRAM), and a Magnetic Random Access Memory (MRAM).
9. A computer system comprising:
a semiconductor memory device including a first memory block and a second memory block that has different operational characteristics from the first memory block;
a memory controller configured to access the first and second memory blocks by an address signal; and
a central processing unit configured to, by way of the memory controller, allocate a memory space to the first memory block for system management and allocate a memory space to the second memory block for data storage,
wherein the first and second memory blocks are integrated in a unitary die.
10. The computer system of claim 9, wherein an address region of the semiconductor memory device includes a first address region for accessing the first memory block and a second address region for accessing the second memory block.
11. The computer system of claim 9, wherein the first and second memory blocks are each driven by different AC parameters.
12. The computer system of claim 9, wherein the second memory block is a nonvolatile memory.
13. The computer system of claim 12, wherein the nonvolatile memory includes one of a flash memory device, a Ferroelectric Random Access Memory (FeRAM), a Phase-change Random Access Memory (PRAM), and a Magnetic Random Access Memory (MRAM).
14. A memory access method in a semiconductor memory device that includes a first memory block of a first type of memory on a die and a second memory block of a second type of memory having a different type from the first type on the same die, the memory access method comprising:
accessing a first address region of the first memory block by a first address signal including a first address;
accessing a second address region of the second memory block by a second address signal including a second address, wherein:
the first address and second address are part of the same address domain, and
the second memory block is a nonvolatile memory.
15. The method of claim 14, wherein:
the first memory block is a volatile memory.
16. The method of claim 15, further comprising:
using the first memory block as a memory space for managing a computer system; and
using the second memory block as a memory space for storing data.
17. The method of claim 14, wherein the same address domain includes a set of consecutive addresses, wherein the addresses of the second address region immediately follow the addresses of the first address region.
18. The method of claim 14, further comprising:
applying first AC parameters to the first address region; and
applying second AC parameters to the second address region, the second AC parameters different from the first AC parameters.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A process for preparing a polybromoaryl ether comprising:
(A) adding to a solvent for the polybromoaryl ether a mixture of:
(1) at least one compound of the structure
HO\u2014Ar\u2014X1X2X3X4X5\u2003\u2003(I)
wherein Ar is an aryl group and X1 X2 X3 X4 and X5 are independently selected from the group consisting of hydrogen and bromine, provided that at least one of X1 X2 X3 X4 and X5 is bromine,
(2) at least one alkali or alkaline metal hydroxide, and
(3) at least one polymerization initiator,
wherein said solvent for the polybromoaryl ether is a non-solvent for alkali or alkaline metal bromides;

(B) mixing the materials prepared in (A) to polymerize compound I and form the polybromoaryl ether and at least one alkali or alkaline metal bromide by-product;
(C) quenching the polymerization of compound I; and then
(D) separating the insoluble alkali or alkaline metal bromide by-product using filtration from the soluble polybromoaryl ether.
2. The process of claim 1 wherein said solvent is tetrahydrofuran.
3. The process of claim 1 wherein:
said solvent is from about 100 wt % to 600 wt % tetrahydrofuran as based on compound I;
said alkali metal hydroxide is from about 100 mol % to 120 mol % sodium hydroxide as based on compound I; and
said polymerization initiator is from about 0.1 mol % to 30 mol % benzoyl peroxide as based on compound I.
4. The process of claim 1 wherein from 30.0 mol % to 0.5 mol % of benzoyl peroxide is reacted to result in said polybromoaryl ether having a molecular weight ranging from 4,000 to 62,000 Daltons.
5. The process of claim 1 wherein from 3.0 mol % to 1.0 mol % of benzoyl peroxide is reacted to result in said polybromoaryl ether having a molecular weight ranging from 15,000 to 40,000 Daltons.

What is claimed is:

1. A display device forming a board for mounting a connector which allows inputting of video data thereon and a board for mounting a display control circuit to be connected to the connector thereon on a surf ace of a display module opposite to an observation side, wherein
the board for mounting the connector thereon and the board for mounting the display control circuit thereon are physically separated from each other and, further, an area of the board for mounting the display control circuit thereon is set smaller than an area of the board for mounting the connector thereon.
2. A display device comprising a display panel PNL, another member different from the display panel PNL which is mounted on a back surface of the display panel, and a board for mounting the connector which allows inputting of video data and a display control circuit which is connected to the connecter, wherein
the board for mounting the connector thereon and the board for mounting the display control circuit thereon are physically separated from each other,
the board for mounting the display control circuit thereon is arranged to be brought into contact with a back surface of a region of the display panel PNL except for a display portion, and the board f or mounting the connector is arranged to be brought into contact with a back surface of the another member.
3. A display device according to claim 2, wherein the board for mounting the display control circuit thereon includes a multilayered wiring layer and the number of stacked layers is larger than the number of stacked layers of the board for mounting the connector.
4. A display device according to claim 2, wherein an area of the board for mounting the display control circuit thereon is set smaller than an area of the board for mounting the connector thereon.
5. A display device according to claim 2, wherein signal lines which are formed on the display panel PNL are electrically connected with terminals which are pulled out from the display control circuit on a surface of the board on which the display control circuit is mounted opposite to a mounting surface for the display control circuit.
6. A display device according to claim 5, wherein the surface of the board on which the display control circuit is mounted opposite to the mounting surface for the display control circuit faces a surface of the display panel PNL opposite to a surface on which the signal lines are mounted in an opposed manner, and the signal lines of the display panel PNL and terminals of the board for mounting the display control circuit are electrically connected with each other by way of a flexible printed circuit board having a conductive layer on one side thereof.
7. A display device according to claim 2, wherein first terminals which are arranged in parallel to each other are formed on the display panel PNL on a surface opposite to the board for mounting the display control circuit, second terminals which are arranged in parallel to each other are formed on a surface of the board for mounting the display control circuit thereon opposite to the display panel PNL, and the first terminals and the second terminals which correspond to each other are electrically connected with each other by way of respective conductive portions formed in the inside of a clip which is mounted in a state that the clip clamps side surface portions of the boards which mount the display panel PNL and the display control circuit thereon.
8. A display device according to claim 2, wherein first terminals which are arranged parallel to each other are formed on the display panel PNL on a surface opposite to the board for mounting the display control circuit, second terminals which are arranged parallel to each other are formed on a surface of the board for mounting the display control circuit thereon opposite to the display panel PNL, and the first terminals and the second terminals which correspond to each other are electrically connected with each other by way of a flexible printed circuit board which is arranged at side surface portions of the boards which mount the display panel PNL and the display control circuit thereon.
9. A display device according to claim 2, wherein the display control circuit board is arranged along a side on which a scanning signal drive circuit of the display panel PNL is arranged, the board for mounting the connector thereon extends toward another end side while setting a portion thereof which is connected with the display control circuit board as one end thereof, the connector is arranged such that the direction that terminals thereof are arranged is substantially aligned with the extending direction of the board, and a width of the connector in the direction that the terminals are arranged in parallel is set larger than a width of the connector in the direction which crosses the extending direction of the board.
10. A display device according to claim 2, wherein the board for mounting the connector thereon is replaced with a member which pulls out a bundle of cables from the connector and at least fixing of the connector to the display panel PNL is performed using an adhesive tape.
11. A display device according to claim 2, wherein a fuse for preventing the generation of an eddy current to the display control circuit board is mounted on the board for mounting the connector thereon.
12. A display device according to claim 2, wherein a data storage medium is mounted on the board for mounting the display control circuit thereon.
13. A display device according to claim 2, wherein a data storage medium is mounted on the board for mounting the connector thereon.
14. A display device according to claim 12, wherein a first data storage medium is mounted on the board for mounting the connector thereon, a second data storage medium is mounted on the board for mounting the display control circuit thereon, information to be supplied to the outside is set in the first data storage medium, and information to be supplied to the inside is set in the second data storage medium.
15. A display device according to claim 12, wherein the display device includes a DA converter which generates gray scale voltages based on information stored in the data storage medium.
16. A display device according to claim 15, wherein the DA converter is incorporated into a video signal drive circuit.
17. A display device according to claim 15, wherein the DA converter is incorporated into the display control circuit.
18. A display device having boards which mount a connector for allowing inputting of video data and a display control circuit which is connected to the connector thereon, wherein
the board for mounting the connector thereon and the board for mounting the display control circuit thereon are physically separated from each other and, further, the board for mounting the display control circuit thereon is arranged on a back surface of a display drive circuit which is mounted on a display panel PNL,
the display drive circuit is constituted of a plurality of semiconductor devices, and
power source is supplied to the respective semiconductor devices from the board for mounting the display control circuit thereon and, further, the number of power source supply portions and the corresponding number of semiconductor devices are set equal in a state that other semiconductor devices are not interposed in a path from a power source supply portion to the respective semiconductor devices.
19. A display device according to claim 18, wherein the power source supply portions to the display drive circuit are provided in plural numbers, and the semiconductor devices which are arranged between one power source supply portion and another power source supply portion are provided in plural numbers.
20. A display device according to claim 19, wherein the number of semiconductor devices arranged between one power source supply portion and another power source supply portion is 2.
21. A display device according to claim 19, wherein the number of power source supply portions to the display drive circuit is the odd number and one of the power source supply portions is positioned outside one end of the display drive circuit which is constituted of a plurality of semiconductor devices.
22. A display device according to claim 21, wherein the number of semiconductor devices is 3 and the number of power source supply portions is 2.
23. A display device according to claim 21, wherein the power source supply portions which are positioned outside one end of the display drive circuit are positioned at a side of the board on which the display drive circuit is formed which extends beyond another board which faces the board on which the display drive circuit is formed.
24. A display device having boards which mount a connector for allowing inputting of video data and a display control circuit which is connected to the connector thereon, wherein
the board for mounting the connector thereon and the board for mounting the display control circuit thereon are physically separated from each other and, further, the board for mounting the display control circuit is arranged such that one side thereof with respect to an imaginary line extending in the longitudinal direction is positioned on a back surface of a display panel PNL and another side with respect to the imaginary line is exposed from the display panel PNL, and
notches are formed in a side of the portion of the display control circuit board which is exposed from the display panel PNL, the notches are cut out along the direction orthogonal to the side, and end sides of the notches are aligned with the imaginary line.
25. A display device according to claim 24, wherein the display device includes at least a frame which houses the display panel PNL and the board for mounting the display control circuit thereon, and a member which fixes the frame with screws, and distal end portions of the screws which penetrate the frame are positioned in the inside of the notches formed in the display control circuit board.
26. A display device according to claim 24, wherein the notches are formed in plural numbers.
27. A display device having boards which mount a connector for allowing inputting of video data and a display control circuit which is connected to the connector thereon, wherein
the board for mounting the connector thereon and the board for mounting the display control circuit thereon are physically separated from each other and, further, the board for mounting the display control circuit is arranged such that one side thereof with respect to an imaginary line extending in the longitudinal direction is positioned on a back surface of a display panel PNL and another side with respect to the imaginary line is exposed from the display panel PNL, and
a mark is formed on a surface of the display panel PNL such that the mark is aligned with a portion of a side of the board for mounting the display control circuit which is positioned on a back surface of the display panel PNL.
28. A display device according to claim 27, wherein the mark is formed in the vicinity of a flexible printed circuit board which establishes an electrical connection between the board for mounting the display control circuit and the display panel PNL.
29. A display device according to claim 28, wherein the display control circuit is provided with a positioning notches in the vicinity of the flexible printed circuit board.
30. A display device having boards which mount a connector for allowing inputting of video data and a display control circuit which is connected to the connector thereon, wherein
the board for mounting the connector thereon and the board for mounting the display control circuit thereon are physically separated from each other and, the board for mounting the display control circuit is positioned on a back surface of the display panel PNL,
a first mark is formed on a region of the display panel PNL which the display control circuit board faces in an opposed manner, and a second mark is formed on a region of the display control circuit board which the display panel PNL faces in an opposed manner, and
the first mark and the second mark are constituted as marks for positioning the display control circuit board with respect to the display panel PNL.
31. A manufacturing method of a display device which includes at least a display panel PNL and a board which mounts a connector for allowing inputting of video data and a display control circuit which is connected to the connector thereon, wherein
the board for mounting the connector thereon and the board for mounting the display control circuit are physically separated from each other,
the board for mounting the display control circuit is arranged on a back surface of the display panel PNL at a region except for a display part, and
the method includes a step in which after the board for mounting the display control circuit is arranged on the back surface of the display panel PNL, an inspection is performed by driving the display device based on the board for mounting the display control circuit thereon.
32. A manufacturing method of a display device which includes at least a display panel PNL and a board which mounts a connector for allowing inputting of video data and a display control circuit which is connected to the connector thereon, wherein
the board for mounting the connector thereon and the board for mounting the display control circuit are physically separated from each other,
the board for mounting the display control circuit is arranged on a back surface of the display panel PNL at a region except for a display part, and
the method includes a step in which after the board for mounting the display control circuit is arranged on the back surface of the display panel PNL, an inspection is performed by driving the display device based on the board for mounting the display control circuit thereon, and a step in which the board for mounting the connector thereon is mounted.
33. A manufacturing method of a display device according to claim 31, wherein the display device is a notebook type personal computer.
34. A manufacturing method of a display device according to claim 31, wherein the display device is a monitor.
35. A manufacturing method of a display device according to claim 31, wherein the display device is a television receiver set.
36. A manufacturing method of a display device according to claim 32, wherein the display device is a notebook type personal computer.
37. A manufacturing method of a display device according to claim 32, wherein the display device is a monitor.
38. A manufacturing method of a display device according to claim 32, wherein the display device is a television receiver set.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of software assisted shader merging for a graphics pipeline, comprising:
accessing a first shader program in memory;
generating a register packet for configuring a graphics module within the graphics pipeline, wherein the register packet comprises an address intended for a target graphics module and a first shader instruction generated from the first shader program;
upon receipt of the register packet by the target graphics module, loading the first shader instruction into an instruction table of the target graphics module at a first location indicated by an offset register associated with the target graphics module, wherein the graphics pipeline comprises the instruction table;
accessing a second shader program in memory;
generating a second shader instruction from the second shader program; and
loading the second shader instruction into the instruction table at a second location indicated by the offset register, wherein the first shader instruction is in the instruction table when the second shader instruction is loaded into the instruction table.
2. The method of claim 1, further comprising:
updating the offset register to indicate the second location.
3. The method of claim 2, wherein the second location comprises an available location within the instruction table.
4. The method of claim 1, wherein the first shader program does not include an explicit instruction table offset.
5. The method of claim 1, wherein accessing the first shader program comprises performing a direct memory access (DMA) transfer of an instruction block associated with the first shader program.
6. The method of claim 1, further comprising:
accessing a modified second shader program in memory;
generating a modified second shader instruction from the modified second shader program; and
loading the modified second shader instruction into the instruction table at the second location, without reloading the first shader instruction.
7. The method of claim 6, further comprising:
configuring a program sequencer to control the graphics pipeline.
8. The method of claim 7, wherein configuring the program sequencer comprises loading a plurality of command instructions into a command table associated with the program sequencer.
9. The method of claim 7, further comprising:
reconfiguring the program sequencer, to preserve an execution order of the first shader instruction and the modified second shader instruction.
10. The method of claim 6, wherein the loading of the modified second shader instruction into the instruction table at the second location is performed without reloading a third shader instruction generated from the second shader program.
11. A graphics processing unit (GPU) for loading a shader program, comprising:
an integrated circuit die comprising a plurality of stages of the GPU;
a memory interface for interfacing with a graphics memory; and
a host interface for interfacing with a computer system, wherein the plurality of stages comprises a graphics pipeline configured to:
access a first shader program in memory;
generate a register packet for configuring a graphics module within the graphics pipeline, wherein the register packet comprises an address intended for a target graphics module and a first shader instruction generated from the first shader program;
upon receipt of the register packet by the target graphics module, load the first shader instruction into an instruction table of the target graphics module at a first location indicated by an offset register associated with the target graphics module, wherein a stage of the plurality of stages of the GPU comprises the instruction table;
access a second shader program in memory;
generate a second shader instruction from the second shader program; and
load a second shader instruction into the instruction table at a second location indicated by the offset register, wherein the graphics pipeline is operable to load the second shader instruction into the instruction table when the first shader instruction is in the instruction table.
12. The GPU of claim 11, wherein the graphics pipeline comprises a program sequencer configured to control the graphics pipeline.
13. The GPU of claim 12, wherein the program sequencer is configured by loading a plurality of command instructions into a command table associated with the program sequencer.
14. The GPU of claim 12, wherein the graphics pipeline is further configured to:
access a modified second shader program in memory;
generate a modified second shader instruction from the modified second shader program; and
load the modified second shader instruction into the instruction table at the second location, without reloading the first shader instruction.
15. The GPU of claim 14, wherein the program sequencer is reconfigured to preserve an execution order of the first shader instruction and the modified second shader instruction.
16. The GPU of claims 11, wherein the first shader program does not include an explicit address.
17. A handheld computer system device, comprising:
a system memory;
a central processing unit (CPU) coupled to the system memory; and
a graphics processing unit (GPU) communicatively coupled to the CPU, wherein the GPU includes a graphics pipeline for executing a shader program, and wherein the graphics pipeline is configured to:
access a first shader program in memory;
generate a register packet for configuring a graphics module within the graphics pipeline, wherein the register packet comprises an address intended for a target graphics module and a first shader instruction generated from the first shader program;
upon receipt of the register packet by the target graphics module, load the first shader instruction into an instruction table of the target graphics module at a first location indicated by an offset register associated with the target graphics module, wherein the graphics pipeline comprises the instruction table;
access a second shader program in memory;
generate a second shader instruction from the second shader program; and
load a second shader instruction into the instruction table at a second location indicated by the offset register, wherein the graphics pipeline is operable to load the second shader instruction into the instruction table when the first shader instruction is in the instruction table.
18. The handheld computer system device of claim 17, wherein the first shader programs stored in memory does not include an explicit instruction table offset.
19. The handheld computer system device of claim 17, wherein the graphics pipeline is further configured to:
access a modified second shader program in memory;
generate a modified second shader instruction from the modified second shader program; and
load the modified second shader instruction into the instruction table at the second location, without reloading the first shader instruction.
20. The handheld computer system device of claim 19, wherein the graphics pipeline is further configured to preserve an execution order of the first shader instruction and the modified second shader instruction.