All The Claims

1. A method comprising observing an analog position signal of a control object in relation to positional indicia, recalling a previously stored runout correction value associated with the positional indicia, and calculating a corrected position signal for the control object in relation to a nonlinear combination of the position signal and the runout correction value.
2. The method of claim 1 wherein the corrected position signal is an analog signal.
3. The method of claim 2 further comprising demodulating the corrected position error signal to obtain a digital position error signal and moving the control object in relation to the position error signal.
4. The method of claim 3 wherein the positional indicia are characterized by servo dibit patterns on a storage medium.
5. The method of claim 4 wherein the control object is characterized as a transducer of a data storage device and the corrected position signal is in relation to an ideal position of the transducer with respect to a data track of the storage medium.
6. The method of claim 5 performed by executing computer instructions that are stored in memory.
7. The method of claim 1 wherein the calculating step is characterized by analytical regression of a nonlinear function in terms of the position signal and the runout correction value.
8. The method of claim 7 wherein the nonlinear function is characterized by the relationship:
ABcor=\u03b11ABm+\u03b12C+\u03b13C|ABm\u2212\u03b14C|
9. The method of claim 7 wherein the nonlinear function is characterized by the relationship:
AB
cor

=
a
\ue89e
\ue89e
0
\ue89e
(
AB
m

S

)

4
+

a
\ue89e
\ue89e
1
\ue89e
(
AB
m

S

)

3
+

a
\ue89e
\ue89e
2
\ue89e
(
AB
m

S

)

2
+

a
\ue89e
\ue89e
3
\ue89e

(
AB
m

S

)
+

a
\ue89e
\ue89e
4
where:
S=scaling factor (increments)
a0=b00C2+b10C+b20
a1=b01C2+b11C+b21
a2=b02C2+b12C+b22
a3=b03C2+b13C+b23
a4=b04C2+b14C+b24
10. An apparatus comprising:
a control object; and
a servo circuit configured to position the control object in response to a corrected position signal that is generated in relation to a nonlinear combination of an analog position signal of the control object in relation to positional indicia and a runout correction value associated with the positional indicia.
11. The apparatus of claim 10 wherein the corrected position signal is an analog signal.
12. The apparatus of claim 11 wherein the servo circuit comprises a demodulator that configures the corrected position error signal as a digital position error signal
13. The apparatus of claim 12 wherein the servo circuit comprises a servo controller that moves the control object in relation to the position error signal.
14. The apparatus of claim 13 wherein the positional indicia are characterized by servo dibit patterns on a storage medium.
15. The apparatus of claim 14 wherein the control object is characterized as a transducer of a data storage device and the corrected position signal is in relation to an ideal position of the transducer with respect to a data track of the storage medium.
16. The apparatus of claim 15 comprising computer instructions that are stored in memory and executed to control operations of the servo circuit.
17. The apparatus of claim 10 wherein the servo circuit calculates the corrected position signal in relation to an analytical regression of a nonlinear function in terms of the position signal and the runout correction value.
18. The apparatus of claim 17 wherein the nonlinear function is characterized by the relationship:
ABcor=\u03b11ABm+\u03b12C+\u03b13C|ABm\u2212\u03b14C|
19. The method of claim 17 wherein the nonlinear function is characterized by the relationship:
AB
cor

=
a
\ue89e
\ue89e
0
\ue89e
(
AB
m

S

)

4
+

a
\ue89e
\ue89e
1
\ue89e
(
AB
m

S

)

3
+

a
\ue89e
\ue89e
2
\ue89e
(
AB
m

S

)

2
+

a
\ue89e
\ue89e
3
\ue89e

(
AB
m

S

)
+

a
\ue89e
\ue89e
4
where:
S=scaling factor (increments)
a0=b00C2+b10C+b20
a1=b01C2+b11C+b21
a2=b02C2+b12C+b22
a3=b03C2+b13C+b23
a4=b04C2+b14C+b24
20. An apparatus comprising:
a control object; and
means for positioning the control object in response to a nonlinear combination of an observed position of the control object with respect to positional indicia and a previously stored runout correction value associated with the positional indicia.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A filter assembly for use in filtering stormwater, comprising:
a bottom including a boss that includes a rib extending laterally along an inner surface of the boss, the rib including a locking portion that mates with a corresponding locking portion on a peripheral surface of a connection to an outlet conduit for securing the bottom to the connection thereby inhibiting rotation of the bottom relative to the outlet conduit;
a center tube secured to the bottom using a locking mechanism that inhibits relative movement between the bottom and the center tube, the center tube being in communication with an opening in the bottom;
a hood secured to the center tube; and
a filter medium located between the hood and the center tube.
2. The filter assembly of claim 1, wherein the hood and center tube include corresponding interlocking structure that inhibit rotation of the hood relative to the center tube with the hood secured to the center tube.
3. The filter assembly of claim 1 further comprising an outer screen secured to the bottom at a bottom portion of the outer screen to inhibit relative movement between the outer screen and the bottom.
4. The filter assembly of claim 3, wherein the outer screen is secured to the bottom using a fastener that is inserted through a peripheral wall of the bottom, through the outer screen and into the bottom.
5. The filter assembly of claim 1 further comprising a top ring that receives an upper edge of an outer screen within a groove, the outer screen located between the hood and the filter medium.
6. The filter assembly of claim 5, wherein the top ring is secured to the outer screen with a fastener inserted through an outer portion of the top ring, through the outer screen and into an inner portion of the top ring.
7. The filter assembly of claim 1 further comprising an inner drainage space cap that is connected to an upper extending end of the center tube that extends beyond an opening in the hood.
8. The filter assembly of claim 7, wherein the inner drainage space cap includes a gasket, the gasket engaging the hood forming an air-tight seal therebetween.
9. The filter assembly of claim 8, wherein the inner drainage space cap includes a check valve that is configured to permit air to escape but not enter a drainage space within the center tube such that a siphon can be established during operation.
10. The filter assembly of claim 1, wherein a height of the filter media is more than about 20 inches.
11. The filter assembly of claim 1, wherein the hood has a top having a series of ribs extending radially between a periphery of the top and a center of the top.
12. The filter assembly of claim 1, wherein the hood includes ribs extending outwardly from an outer periphery of the hood, the ribs being configured to maintain some spacing between stacked hoods.
13. A method of assembling a filter assembly for use in filtering stormwater, the method comprising:
securing a center tube to a bottom using a locking mechanism inhibiting relative movement between the bottom and the center tube, the center tube being in communication with an opening in the bottom;
securing a hood to the center tube inhibiting relative movement between the center tube and the hood;
providing a filter media between the hood and the center tube; and
applying a rotational force to the assembly which causes the center tube and bottom to rotate during installation.
14. The method of claim 13 further comprising securing an outer screen to the bottom at a bottom portion of the outer screen to inhibit relative movement between the outer screen and the bottom, the outer screen positioned between the hood and the filter media.
15. The method of claim 14, wherein the step of securing the outer screen to the bottom comprises inserting a fastener through a peripheral wall of the bottom, through the outer screen and into the bottom.
16. The method of claim 14, wherein the step of locating the outer screen on the bottom comprises positioning the bottom portion of the outer screen within a gap formed between the radially extending rib and the peripheral outer wall.
17. The method of claim 14 further comprising placing an upper edge of the outer screen within a top ring having a groove sized to receive the upper edge of the outer screen.
18. The method of claim 17 further comprising securing the outer screen to the top ring by inserting a fastener through an outer portion of the top ring, through the outer screen and into an inner portion of the top ring.
19. The method of claim 14 further comprising connecting an inner drainage space cap onto an upper extending end of the center tube that extends beyond an opening in the hood, the inner drainage space cap including a rim having a gasket, the gasket engaging the hood forming an air-tight seal therebetween.
20. The method of claim 19, wherein the inner drainage space cap includes a check valve that is configured to permit air to escape but not enter a drainage space within the center tube such that a siphon can be established during operation.
21. The method of claim 13 further comprising securing the bottom onto an outlet conduit connection by rotating the hood, center tube and bottom together, the bottom including a boss that includes a tab portion that mates with a corresponding recess portion on a peripheral surface of the outlet conduit connection for securing the bottom to the outlet conduit connection thereby inhibiting rotation of the bottom relative to the outlet conduit connection and providing positive feedback that the bottom is secured to the outlet conduit connection.
22. A stormwater treatment system for use in filtering stormwater, comprising:
an outlet conduit connection that connects to a filter conduit for use in delivering filtered stormwater toward an outlet of the stormwater treatment system, the outlet conduit connection comprising a locking portion on a peripheral surface of the outlet conduit connection; and
a filter assembly comprising
a bottom including a boss that includes a rib extending laterally along an inner surface of the boss, the rib including a locking portion that mates with the snap lock portion on the peripheral surface of the outlet conduit connection for securing the bottom to the outlet conduit connection thereby inhibiting rotation of the bottom relative to the outlet conduit connection;
a center tube secured to the bottom using a locking mechanism that inhibits relative movement between the bottom and the center tube, the center tube being in communication with an opening in the bottom and the outlet conduit connection;
a hood secured to the center tube; and
a filter media between the hood and the center tube.
23. The stormwater treatment system of claim 22, wherein the outlet conduit connection includes an outwardly extend rib that mates with a bottom of the bottom.
24. The stormwater treatment system of claim 22 further comprising a outlet conduit connection mount located between the outlet conduit connection and filter conduit.
25. A filter assembly for use in filtering stormwater, comprising:
a housing structure;
a drainage space within the housing structure; and
a filter medium between the drainage space and housing structure;
wherein the housing structure includes a lower portion with a mount opening for mating with an outlet conduit connection, the mount opening including a pair of circumferentially extending and diametrically opposed ribs extending radially inwardly.
26. The filter assembly of claim 25, wherein each rib includes a locking tab at one end thereof, the locking tab formed by a raised protrusion of the upper surface of the rib.

1. A storage system management apparatus for managing a storage system, the storage system including a pool comprising storage tiers with respectively different performances, and a virtual logical volume formed by logical storage areas, to be provided to a host computer, and configured to allocate a logical storage area to an instructed prescribed storage tier of the storage tiers, the storage system management apparatus comprising:
a non-transient memory storing a storage management program, and
a processing unit configured to execute the storage management program to:
(1) collect prescribed information from the storage system;
(2) produce an evaluation of an access load for each of the logical storage areas based on the prescribed information;
(3) calculate allocation time information, which is a ratio between a time at which each of the logical storage areas is allocated to a highest performance storage tier and a prescribed allocation reference period;
(4) determine a storage tier for each of the logical storage areas based on the access load of the logical storage areas and the allocation time information; and
(5) provide a reallocation instruction to the storage system based on a result of the determining of the storage tier.
2. The storage system management apparatus according to claim 1, wherein the processing unit is further configured to execute the storage management program to:
select a monitoring mode from a plurality of monitoring modes; and
processing the evaluation of the access load based on the selected monitoring mode.
3. The storage system management apparatus according to claim 2, wherein the selection of the monitoring mode is processed based on the allocation time information.
4. The storage system management apparatus according to claim 3, wherein the selection of the monitoring mode is processed by comparing the allocation time information and preconfigured monitoring mode selection reference information.
5. The storage system management apparatus according to claim 4, wherein the selection of the monitoring mode comprises:
for each of the logical storage areas, selecting a candidate for the monitoring mode; and
selecting a most numerous monitoring mode from the candidates, as the selected monitoring mode.
6. The storage system management apparatus according to claim 4, wherein the selection of the monitoring mode comprises:
for each of the logical storage areas, selecting a candidate of the monitoring mode;
selecting a monitoring mode from candidates differing from a current monitoring mode, as the selected monitoring mode.
7. The storage system management apparatus according to claim 4, wherein the processing unit is further configured to execute the storage management program to:
(6) select a user-selected monitoring mode as the selected monitoring mode.
8. The storage system management apparatus according to claim 7, wherein the processing unit is further configured to execute the storage management program to:
(7) display the access load, the allocation time information, and the result of the determination in a setting screen for selection by a user.
9. The storage system monitoring apparatus according to claim 4, wherein the processing unit is further configured to execute the storage management program to:
(8) in the setting screen, accept the prescribed allocation reference period.
10. The storage system management apparatus according to claim 2, wherein the monitoring mode is selected for each of the virtual logical volumes.
11. The storage system management apparatus according to claim 2, wherein the selection of the monitoring mode is processed based on a type of an application program executed by the host computer.
12. The storage system monitoring apparatus according to claim 1, wherein:
the monitoring modes include at least a first monitoring mode and a second monitoring mode,
a second monitoring period of the second monitoring mode is set so as to be longer than a first monitoring period of the first monitoring mode, and
the evaluation is processed based on a number of access requests issued from the host computer to the virtual logical volume within a selected period which is the first monitoring period or the second monitoring period.
13. A computer system comprising:
a host computer;
a storage system which includes a pool comprising storage tiers with respectively different performances, and a virtual logical volume formed by logical storage areas, to be provided to a host computer, and which is configured to allocate a logical storage area to an instructed prescribed storage tier of the storage tiers; and
a storage system management apparatus configured to
(1) collect prescribed information from the storage system;
(2) produce an evaluation of an access load for each of the logical storage areas based on the prescribed information;
(3) calculate allocation time information, which is a ratio between a time at which each of the logical storage areas is allocated to a highest performance storage tier and a prescribed allocation reference period;
(4) determine a storage tier for each of the logical storage areas based on the access load of the logical storage areas and the allocation time information; and
(5) provide a reallocation instruction to the storage system based on a result of the determination.
14. The computer system according to claim 13, wherein the storage system management apparatus is configured to:
select a monitoring mode from a plurality of monitoring modes; and
process the evaluation based on the selected monitoring mode.
15. The computer system according to claim 14, wherein the selection of the monitoring mode is processed based on the allocation time information.
16. The storage system management apparatus according to claim 15, wherein the selection of the monitoring mode is processed by comparing the allocation time information and preconfigured monitoring mode selection reference information.
17. The storage system management apparatus according to claim 16, wherein the selection of the monitoring mode is processed by:
for each of the logical storage areas, selecting a candidate of the monitoring mode;
selecting a most numerous monitoring mode from candidates for the monitoring mode as the selected monitoring mode.
18. The storage system management apparatus according to claim 16, wherein the selection of the monitoring mode is processed by:
for each of the logical storage areas, selecting a candidate of the monitoring mode;
selecting the monitoring mode from candidates differing from a current monitoring mode, as the selected monitoring mode.
19. A storage system monitoring apparatus according to claim 16, wherein the processing unit is further configured to:
(8) in the setting screen, accept the prescribed allocation reference period.
20. The storage system management apparatus according to claim 14, wherein the selection of the monitoring mode is processed based on a type of an application program executed by the host computer.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. For use in a computer system comprising a plurality of master agents, a memory controller comprising:
a bus interface capable of being coupled to an internal bus of said computer system;
a memory interface capable of being coupled to a main memory of said computer system; and
a plurality of pre-fetch queues, wherein each pre-fetch queue is coupled to said bus interface to receive data from said bus interface, and wherein each pre-fetch queue is coupled to said memory interface to send data to said memory interface;
wherein said bus interface, upon identifying a pre-fetch request, is further capable of selecting a pre-fetch queue of said plurality of pre-fetch queues using a selection algorithm; and
wherein said bus interface is capable of sending said pre-fetch request to the selected pre-fetch queue.
2. A memory controller as claimed in claim 1 wherein each of said plurality of pre-fetch queues is assigned to a corresponding master agent of said plurality of master agents of said computer system.
3. A memory controller as claimed in claim 1 further comprising:
a write queue coupled to said bus interface and to said memory interface; and
a read line coupled to said bus interface and to said memory interface.
4. A memory controller as claimed in claim 3 wherein said bus interface is capable of receiving through said internal bus a memory request from a bus master associated with a master agent; and
wherein said bus interface is capable of determining whether said memory request is one of: a memory read request, a memory write request, or a pre-fetch request.
5. A memory controller as claimed in claim 4 wherein said bus interface, upon identifying a memory read request, is capable of determining if a pre-fetch flag is set in said memory read request, and in response to determining that said pre-fetch flag is set, is capable of sending said memory read request to a pre-fetch queue as a pre-fetch request.
6. A memory controller as claimed in claim 4 wherein said bus interface, upon identifying a memory read request, is capable of determining whether data requested by said memory read request is located in a pre-fetch queue of said plurality of pre-fetch queues, and in response to determining that said requested data is located in said pre-fetch queue, is capable of retrieving said requested data from said pre-fetch queue.
7. A memory controller as claimed in claim 6 wherein said bus interface, in response to determining that said requested data is not located in said pre-fetch queue, is capable of sending said memory read request to said memory interface; and
wherein said memory interface is capable of retrieving said requested data from said main memory.
8. A memory controller as claimed in claim 1 wherein said selected pre-fetch queue is capable of sending said pre-fetch request to said memory interface;
wherein said memory interface is capable of retrieving from said main memory data requested by said pre-fetch request; and
wherein said memory interface is capable of sending said data to said selected pre-fetch queue that requested said data.
9. A memory controller as claimed in claim 1 wherein said selection algorithm comprises:
selecting a pre-fetch queue that contains requested data from said plurality of pre-fetch queues;
selecting an empty pre-fetch queue if none of said plurality of pre-fetch queues contains said requested data;
selecting a pre-fetch queue that has gone the longest time without being accessed if there are no empty pre-fetch queues; and
discarding data from a pre-fetch queue that is selected.
10. A memory controller as claimed in claim 1 wherein one of said plurality of pre-fetch queues is dynamically assigned to one of a plurality of master agents of said computer system when a number of master agents of said computer system is greater than a number of pre-fetch queues in said memory controller.
11. A memory controller as claimed in claim 10 further comprising:
a write queue coupled to said bus interface and to said memory interface; and
a read line coupled to said bus interface and to said memory interface.
12. A memory controller as claimed in claim 11 wherein said bus interface is capable of receiving through said internal bus a memory request from a bus master associated with a master agent; and
wherein said bus interface is capable of determining whether said memory request is one of: a memory read request or a memory write request.
13. A memory controller as claimed in claim 12 wherein said bus interface, upon identifying a memory read request, is capable of determining if whether data requested by said memory read request is located in a pre-fetch queue of said plurality of pre-fetch queues, and in response to determining that said requested data is located in said pre-fetch queue, is capable of retrieving said requested data from said pre-fetch queue.
14. A memory controller as claimed in claim 13 wherein said bus interface, in response to determining that said requested data is not located in said pre-fetch queue, is capable of sending said memory read request to said memory interface; and
wherein said memory interface is capable of retrieving said requested data from said main memory.
15. A memory controller as claimed in claim 12 wherein said bus interface is capable of determining if a pre-fetch flag of a current memory read request is set, and in response to determining that said pre-fetch flag is set, is capable of sending said current memory read request to a current pre-fetch queue with a next address.
16. A memory controller as claimed in claim 14 wherein said bus interface is capable of determining if a pre-fetch flag of a current memory read request is set, and wherein said bus interface is capable of sending to said pre-fetch queue selected by said selection algorithm said current memory read request with a next address.
17. A memory controller as claimed in claim 12 wherein said memory interface in response to determining that there is a memory read request on said read line, is capable of determining whether there is data in said write queue that has a same address as said memory read request.
18. A memory controller as claimed in claim 17 wherein said memory interface in response to determining that there is data in said write queue that has a same address as said memory read request, is capable of writing said data in said write queue to said main memory, and
wherein said memory interface in response to determining that there is no data in said write queue that has a same address as said memory read request, is capable of accessing said main memory to obtain data to complete said memory read request.
19. A memory controller as claimed in claim 12 wherein said memory interface in response to determining that there is no memory read request on said read line, is capable of determining whether said write queue is empty; and
wherein in response to determining that said write queue is not empty, said memory interface is capable of writing data in said write queue to said main memory.
20. A memory controller as claimed in claim 19 wherein said memory interface in response to determining that said write queue is empty, is capable of determining whether there is a pending pre-fetch request in said plurality of pre-fetch queues; and
wherein said memory interface in response to determining that there is a pending pre-fetch request, is capable of determining whether there is a pre-fetch request located in a currently opened page of said main memory.
21. A memory controller as claimed in claim 20 wherein said memory interface in response to determining that there is a pre-fetch request located in a currently opened page of said main memory, is capable of accessing said main memory to obtain data to send to a matched pre-fetch queue; and
wherein said memory interface in response to determining that there is no pre-fetch request located in a currently opened page of said main memory, is capable of randomly selecting a pre-fetch queue and accessing said main memory to obtain data to send to said randomly selected pre-fetch queue.
22. A method for providing a memory controller in a computer system comprising a plurality of master agents, said method comprising:
providing a bus interface that is capable of being coupled to an internal bus;
providing a memory interface that is capable of being coupled to a main memory;
providing a plurality of pre-fetch queues, wherein each pre-fetch queue is coupled to said bus interface to receive data from said bus interface, and wherein each pre-fetch queue is coupled to said memory interface to send data to said memory interface;
receiving a memory request at the bus interface:
when said memory request is determined to be a pre-fetch request:
selecting a pre-fetch queue of said plurality of pre-fetch queues using a selection algorithm; and
sending said pre-fetch request to the selected pre-fetch queue.
23. A method as claimed in claim 22 further comprising:
assigning each of said plurality of pre-fetch queues to one master agent of said plurality of master agents of said computer system.
24. A method as claimed in claim 22 further comprising:
providing a write queue coupled to said bus interface and to said memory interface; and
providing a read line coupled to said bus interface and Co said memory interface.
25. A method as claimed in claim 22 further comprising:
when said memory request is determined to be a memory read request:
determining in said bus interface whether a pre-fetch flag is set in said memory read request;
in response to determining that said pre-fetch flag is set, sending said pre-fetch request to a pre-fetch queue as a pre-fetch request.
26. A method as claimed in claim 22 further comprising:
when said memory request is determined to be a memory read request:
determining in said bus interface whether data requested by said memory read request is located in a pre-fetch queue of said plurality of pre-fetch queues; and
in response to determining that said requested data is located in said pre-fetch queue, retrieving said requested data from said pre-fetch queue.
27. A method as claimed in claim 26 further comprising:
in response to determining that said requested data is not located in said pre-fetch queue, sending said memory read request to said memory interface; and
retrieving said requested data into said memory interface from said main memory.
28. A method as claimed in claim 22 further comprising:
when said memory request is determined to be a pre-fetch request:
sending said pre-fetch request from said selected pre-fetch queue to said memory interface;
retrieving in said memory interface from said main memory data requested by said pre-fetch request; and
sending said data from said memory interface to said selected pre-fetch queue that requested said data.
29. A method as claimed in claim 22 wherein said selection algorithm comprises:
selecting a pre-fetch queue that contains requested data from said plurality of pre-fetch queues;
selecting an empty pre-fetch queue if none of said plurality of pre-fetch queues contains said requested data;
selecting a pre-fetch queue that has gone the longest time without being accessed if there are no empty pre-fetch queues; and
discarding data from a pre-fetch queue that is selected.
30. A method as claimed in claim 22 further comprising:
determining in said bus interface that said memory request is a memory write request;
sending said memory write request from said bus interface to a write queue;
sending said memory write request from said write queue to said memory interface; and
sending said write request from said memory interface to said main memory.
31. A method as claimed in claim 22 further comprising:
dynamically assigning one of said plurality of pre-fetch queues to one of a plurality of master agents of said computer system when a number of master agents of said computer system is greater than a number of pre-fetch queues in said memory controller.
32. A method as claimed in claim 31 further comprising:
providing a write queue coupled to said bus interface and to said memory interface; and
providing a read line coupled to said bus interface and to said memory interface.
33. A method as claimed in claim 32 further comprising:
receiving in said bus interface through said internal bus a memory request from a bus master associated with a master agent; and
determining in said bus interface whether said memory request is one of: a memory read request and a memory write request.
34. A method as claimed in claim 33 further comprising:
determining in said bus interface whether data requested by said memory read request is located in a pre-fetch queue of said plurality of pre-fetch queues; and
in response to determining that said requested data is located in said pre-fetch queue, retrieving said requested data from said pre-fetch queue.
35. A method as claimed in claim 34 further comprising:
in response to determining that said requested data is not located in said pre-fetch queue, sending said memory read request to said memory interface; and
retrieving said requested data into said memory interface from said main memory.
36. A method as claimed in claim 33 further comprising:
determining in said bus interface whether a pre-fetch flag of a current memory read request is set; and
in response to determining that said pre-fetch flag is set, sending said current memory read request to a current pre-fetch queue with a next address.
37. A method as claimed in claim 35 further comprising:
determining in said bus interface whether a pre-fetch flag of a current memory read request is set;
in response to determining that said pre-fetch flag is set, selecting a pre-fetch queue of said plurality of pre-fetch queues using a selection algorithm; and
sending to said pre-fetch queue selected by said selection algorithm said current memory read request with a next address.
38. A method as claimed in claim 33 further comprising:
in response to determining in said memory interface that there is a memory read request on said read line, determining whether there is data in said write queue that has a same address as said memory read request.
39. A method as claimed in claim 38 further comprising:
in response to determining in said memory interface that there is data in said write queue that has a same address as said memory read request, writing said data in said write queue to said main memory; and
in response to determining in said memory interface that there is no data in said write queue that has a same address as said memory read request, accessing said main memory to obtain data to complete said memory read request.
40. A method as claimed in claim 33 further comprising:
in response to determining in said memory interface that there is no memory read request on said read line, determining whether said write queue is empty; and
in response to determining in said memory interface that said write queue is not empty, writing data in said write queue to said main memory.
41. A method as claimed in claim 40 further comprising:
in response to determining in said memory interface Chat said write queue is empty, determining whether there is a pending pre-fetch request in said plurality of pre-fetch queues; and
in response to determining in said memory interface that there is a pending pre-fetch request, determining whether there is a pre-fetch request located in a currently opened page of said main memory.
42. A method as claimed in claim 41 further comprising:
in response to determining in said memory interface that there is a pre-fetch request located in a currently opened page of said main memory, accessing said main memory to obtain data to send to a matched pre-fetch queue; and
in response to determining in said memory interface that there is no pre-fetch request located in a currently opened page of said main memory, randomly selecting a pre-fetch queue; and
accessing said main memory to obtain data to send to said randomly selected pre-fetch queue.
43. A memory controller comprising:
a bus interface capable of being coupled to an internal bus of said computer system;
a memory interface capable of being coupled to a main memory of said computer system; and
a plurality of pre-fetch queues, wherein each pre-fetch queue is coupled to said bus interface to receive data from said bus interface, and wherein each pre-fetch queue is coupled to said memory interface to send data to said memory interface;
wherein said bus interface, upon identifying a memory read request, is capable of determining if a pre-fetch flag is set in said memory read request, and in response to determining that said pre-fetch flag is set, is capable of sending said memory read request to a pre-fetch queue as a pre-fetch request.