All The Claims

1. A waterproof plug for a waterproof connector, comprising;
a body portion, which has a substantially cylindrical shape, and has a first end and a second end which is opposite side of the first end; and
an enlarged portion, which is formed on the first end of the body portion in coaxial relation thereto,
wherein a slanting face is formed on an outer face of the enlarged portion so that the enlarged portion decreases in a diameter from a side of the second end toward a side of the first end.
2. A waterproof plug for a waterproof connector including a housing and an elastic plug, the housing having a receiving chamber for receiving a terminal connected to a cable, an opening, a communication portion through which the opening and the receiving chamber communicate with each other, and a slanting portion formed between the communication portion and the receiving chamber, and the elastic plug having a through hole for being passed through the cable and the elastic plug being press-fitted in the communication portion, the waterproof plug, comprising:
a body portion, which has a substantially cylindrical shape, and has a first end and a second end which is opposite side of the first end; and
an enlarged portion, which is formed on the first end of the body portion in coaxial relation thereto,
wherein a slanting face is formed on an outer face of the enlarged portion so as to correspond to the slanting portion so that the enlarged portion decreases in a diameter from a side of the second end toward a side of the first end;
wherein instead of the cable, the body portion is fitted in the through hole of the elastic plug; and
wherein the slanting face of the enlarged portion is bring into contact with the slanting portion of the housing when the elastic plug is press-fitted in the communication portion of the housing.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A random signal generator circuit comprising:
a thermal noise generator circuit;
a self-biased inverter circuit having an input coupled to the thermal noise generator circuit and to a feedback resistor coupled to an output of the self-biased inverter circuit, the self-biased inverter circuit configured to produce a sensed noise signal at the output responsive to thermal noise generated by the thermal noise generator circuit; and
an amplifier circuit coupled to the output of the self-biased inverter circuit and configured to amplify the sensed noise signal to produce a saturated random signal.
2. The random signal generator circuit of claim 1, wherein the amplifier circuit comprises:
a first amplifier circuit coupled to the output of the self-biased inverter circuit and configured to amplify the sensed noise signal to produce an amplified noise signal; and
a second amplifier circuit AC coupled to the first amplifier circuit and configured to produce the saturated random signal responsive to the amplified noise signal.
3. The random signal generator circuit of claim 2, wherein the first amplifier circuit comprises an inverter circuit.
4. The random signal generator circuit of claim 3, wherein the first amplifier circuit comprises a plurality of cascaded inverter circuits.
5. The random signal generator circuit of claim 2, wherein the second amplifier circuit comprises a cascade combination of a self-biased inverter circuit and at least one inverter circuit.
6. The random signal generator circuit of claim 2, wherein the second amplifier circuit comprises a plurality of AC coupled amplifier circuits.
7. The random signal generator circuit of claim 6, wherein each of the plurality of AC coupled amplifier circuits comprises a cascade combination of a self-biased inverter circuit and at least one inverter circuit.
8. The random signal generator circuit of claim 2, wherein a gain of the first amplifier circuit is substantially greater than a gain of the self-biased inverter circuit, and wherein a gain of the second amplifier circuit is substantially greater than the gain of the first amplifier circuit.
9. The random signal generator circuit of claim 2:
wherein the self-biased inverter circuit comprises a self-biased CMOS inverter circuit:
wherein the first amplifier circuit comprises a CMOS inverter circuit or a plurality of cascaded CMOS inverter circuits; and
wherein the second amplifier circuit comprises a cascade combination of a self-biased CMOS inverter circuit and at least one CMOS inverter circuit.
10. The random signal generator circuit of claim 1, wherein the thermal noise generator circuit comprises a thermal noise generating resistor coupled to the input of the self-biased inverter circuit.
11. The random signal generator circuit of claim 10, wherein the thermal noise generator circuit comprises a series combination of a resistor and a capacitor coupled between the input of the self-biased inverter circuit and a signal ground node.
12. The random signal generator circuit of claim 1, further comprising a sampler coupled to the amplifier circuit and configured to produce a random digital signal from the saturated random signal responsive to a clock signal.
13. The random signal generator circuit of claim 12, wherein the sampler comprises a flip-flop.
14. A random number generator circuit including the random signal generator circuit of claim 1.
15. A random signal generator circuit comprising:
a thermal noise generator circuit;
a first single-ended amplifier circuit coupled to the thermal noise generator circuit and configured to sense and amplify a noise signal thereof to produce an amplified noise signal; and
a second single-ended amplifier circuit AC coupled to the first single-ended amplifier circuit and configured to produce a saturated random signal responsive to the amplified noise signal.
16. The random signal generator circuit of claim 15, wherein the first single-ended amplifier circuit comprises:
a self-biased inverter circuit having an input coupled to the thermal noise generator circuit and configured to produce a sensed noise signal at an output thereof responsive to thermal noise generated by the thermal noise generator circuit; and
at least one inverter circuit coupled to the output of the self-biased inverter circuit and configured to generate the amplified noise signal from the sensed noise signal.
17. The random signal generator circuit of claim 15, wherein the second single-ended amplifier circuit comprises a cascade combination of a self-biased inverter circuit and at least one inverter circuit.
18. The random signal generator circuit of claim 15, wherein the second single-ended amplifier circuit comprises a plurality of AC coupled amplifier circuits.
19. The random signal generator circuit of claim 18, wherein each of the plurality of AC coupled amplifier circuits comprises a cascade combination of a self-biased inverter circuit and at least one inverter circuit.
20. The random signal generator circuit of claim 15, wherein the thermal noise generator circuit comprises a resistor and wherein the first single-ended amplifier circuit is configured to generate the amplified noise signal responsive to a thermal noise voltage developed across the resistor.
21. The random signal generator circuit of claim 15, wherein the thermal noise generator circuit comprises a series combination of a resistor and a capacitor coupled between the input of the first single-ended amplifier circuit and a signal ground node.
22. The random signal generator circuit of claim 15, further comprising a sampler configured to generate a random digital signal from the saturated random signal.
23. A random number generator circuit including the random signal generator circuit of claim 1.
24. A method comprising:
coupling a thermal noise generator circuit to an input of a self-biased inverter circuit to generate a sensed noise signal at an output thereof,
applying the sensed noise signal to a first amplifier circuit to produce an unsaturated amplified noise signal; and
AC coupling the unsaturated noise signal to a second amplifier circuit to produce a saturated random signal.
25. The method of claim 24, wherein the first amplifier circuit comprises an inverter circuit.
26. The method of claim 25, wherein the first amplifier circuit comprises a plurality of cascaded inverter circuits.
27. The method of claim 24, wherein the second amplifier circuit comprises a cascade combination of a self-biased inverter circuit and at least one inverter circuit.
28. The method of claim 24, wherein the second amplifier circuit comprises a plurality of AC coupled amplifier circuits.
29. The method of claim 28, wherein each of the plurality of AC coupled amplifier circuits comprises a cascade combination of a self-biased inverter circuit and at least one inverter circuit.
30. The method of claim 24, wherein coupling a thermal noise generator circuit to an input of a self-biased inverter circuit to generate a sensed noise signal at an output thereof comprises generating the sensed noise signal responsive to a thermal noise voltage developed across a resistor of the thermal noise generator circuit.
31. The method of claim 30, wherein the thermal noise generator circuit comprises a series combination of a resistor and a capacitor coupled between the input of the self-biased inverter circuit and a signal ground node.
32. The method of claim 24, wherein a gain of the first amplifier circuit is substantially greater than a gain of the self-biased inverter circuit, and wherein a gain of the second amplifier circuit is substantially greater than the gain of the first amplifier circuit.
33. The method of claim 24:
wherein the self-biased inverter circuit comprises a self-biased CMOS inverter circuit:
wherein the first amplifier circuit comprises a CMOS inverter circuit or a plurality of cascaded CMOS inverter circuits; and
wherein the second amplifier circuit comprises a cascade combination of a self-biased CMOS inverter circuit and at least one CMOS inverter circuit.
34. The method of claim 24, further comprising generating a random digital signal from the saturated random signal.
35. The method of claim 34, wherein generating a random digital signal from the saturated random signal comprises sampling the saturated random signal responsive to a clock signal to produce the random digital signal.
36. The method of claim 35, wherein sampling the saturated random signal responsive to a clock signal to produce the random digital signal comprises sampling the saturated random signal using a flip-flop.
37. The method of claim 34, further comprising generating a random number from the random digital signal.

1. A memory cell for a first bit line, a second bit line, a word line and a power voltage, the memory cell comprising:
a first PMOS transistor comprising a first gate, a first drain, and a first source coupled to the power voltage;
a first NMOS transistor comprising a second gate coupled to the first gate, a second drain coupled to the first drain, and a second source coupled to a ground voltage, wherein the connection point of the first drain and the second drain is a first terminal;
a second PMOS transistor comprising a third gate coupled to the first terminal, a third drain coupled to the first gate, and a third source coupled to the power voltage;
a second NMOS transistor comprising a fourth gate coupled to the first terminal, a fourth drain coupled to the third drain, and a fourth source coupled to the ground voltage, wherein the connection point of the third drain and the fourth drain is a second terminal;
a first switch coupled between the first bit line and the first terminal, switched according to a voltage level of the word line;
a second switch coupled between the second bit line and the second terminal, switched according to the voltage level of the word line; and
a latch circuit having a power terminal directly connected to the power voltage, and coupled between the first terminal and the second terminal to preserve the voltage levels respectively of the first terminal and the second terminal.
2. The memory cell as claimed in claim 1, wherein the latch circuit comprises:
a third PMOS transistor comprising a fifth gate coupled to the second terminal, a fifth drain coupled to the first terminal, and a fifth source coupled to the power voltage; and
a fourth PMOS transistor comprising a sixth gate coupled to the first terminal, a sixth drain coupled to the second terminal, and a sixth source coupled to the power voltage.
3. The memory cell as claimed in claim 2, wherein each of the first NMOS transistor, the first PMOS transistor, the second PMOS transistor, and the second PMOS transistor comprises a first gate oxide layer and a first threshold voltage.
4. The memory cell as claimed in claim 3, wherein each of the third PMOS transistor and the fourth PMOS transistor comprises a second gate oxide layer thicker than the first gate oxide layer.
5. The memory cell as claimed in claim 3, wherein each of the third PMOS transistor and the fourth PMOS transistor comprises a second threshold voltage higher than the first threshold voltage.
6. A circuit for power management of a memory cell comprising a first terminal, a second terminal and a power input terminal, and switching between normal and standby modes according to a power control signal, the circuit for power management comprising:
a first power switch coupled between a power voltage, the power control signal and the memory cell, wherein the first power switch is turned off to disconnect the power voltage and the memory cell when the power control signal is at a predetermined level, such that the memory cell operates in standby mode, wherein the memory cell is coupled between a first bit line, a second bit line and a word line; and
a latch circuit coupled between the power voltage, the first terminal and the second terminal to preserve the voltage levels respectively of the first terminal and the second terminal when the memory cell operates in the standby mode, wherein the latch circuit comprises:
a third PMOS transistor comprising a fifth gate coupled to the second terminal, a fifth drain coupled to the first terminal, and a fifth source coupled to the power voltage; and
a fourth PMOS transistor comprising a sixth gate coupled to the first terminal, a sixth drain coupled to the second terminal, and a sixth source coupled to the power voltage.
7. The circuit for power management as claimed in claim 6, wherein the memory comprising:
a first PMOS transistor comprising a first gate, a first drain, and a first source coupled to the power voltage;
a first NMOS transistor comprising a second gate coupled to the first gate, a second drain coupled to the first drain, and a second source coupled to a ground voltage, wherein the connection point of the first drain and the second drain is the first terminal;
a second PMOS transistor comprising a third gate coupled to the first terminal, a third drain coupled to the first gate, and a third source coupled to the power voltage;
a second NMOS transistor comprising a fourth gate coupled to the first terminal, a fourth drain coupled to the third drain, and a fourth source coupled to the ground voltage, wherein the connection point of the third drain and the fourth drain is the second terminal;
a first switch coupled between the first bit line and the first terminal, switched according to a voltage level of the word line; and
a second switch coupled between the second bit line and the second terminal, switched according to the voltage level of the word line.
8. The circuit for power management as claimed in claim 6, wherein the first power switch is a fifth PMOS transistor having a seventh gate coupled to the power control signal.
9. The circuit for power management as claimed in claim 8, wherein the predetermined level is a low logic level.
10. The circuit for power management as claimed in claim 9, further comprising a second power switch coupled between the second source, the fourth source and the ground voltage, wherein the second power switch is turned off when the power control signal is at the predetermined level.
11. The circuit for power management as claimed in claim 10, wherein the second switch is a third NMOS transistor having an eighth gate coupled to a reverse power control signal.
12. The circuit for power management as claimed in claim 11, further comprising an inverter coupled between the seventh gate and the eighth gate.
13. The circuit for power management as claimed in claim 10, wherein each of the first NMOS transistor, the first PMOS transistor, the second PMOS transistor, and the second PMOS transistor comprises a first gate oxide layer and a first threshold voltage.
14. The circuit for power management as claimed in claim 13, wherein each of the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor and the third NMOS transistor comprises a second gate oxide layer thicker than the first gate oxide layer.
15. The circuit for power management as claimed in claim 13, wherein each of the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor and the third NMOS transistor comprises a second threshold voltage higher than the first threshold voltage.
16. The circuit for power management as claimed in claim 10, wherein a plurality of memory cells is coupled between the first power switch and the second power switch.
17. The circuit for power management as claimed in claim 6, wherein the first power switch is coupled to a plurality of memory cells.
18. The circuit for power management as claimed in claim 6, wherein the memory cell is a static random access memory.
19. A power management circuit, comprising:
a memory cell coupled between a first bit line, a second bit line and a word line, the memory cell comprising:
a first PMOS transistor comprising a first gate, a first drain, and a first source;
a first NMOS transistor comprising a second gate coupled to the first gate, a second drain coupled to the first drain, and a second source, wherein the connection point of the first drain and the second drain is a first terminal;
a second PMOS transistor comprising a third gate coupled to the first terminal, a third drain coupled to the first gate, and a third source coupled to the first source;
a second NMOS transistor comprising a fourth gate coupled to the first terminal, a fourth drain coupled to the third drain, and a fourth source coupled to the second source, wherein the connection point of the third drain and the fourth drain is a second terminal;
a first switch coupled between the first bit line and the first terminal, switched according to a voltage level of the word line; and
a second switch coupled between the second bit line and the second terminal, switched according to the voltage level of the word line, wherein the memory cell switches between normal and standby modes according to a power control signal;

a first power switch coupled between a power voltage, the power control signal and a connection point of the first source and the third source, wherein the first power switch is turned off to disconnect the power voltage and the memory cell when the power control signal is at a predetermined level, such that the memory cell operates in standby mode; and
a latch circuit having a power terminal directly connected to the power voltage, and coupled between the first terminal and the second terminal to preserve the voltage levels respectively of the first terminal and the second terminal when the memory cell operates in the standby mode.
20. The power management circuit as claimed in claim 19, wherein the latch circuit comprises:
a third PMOS transistor comprising a fifth gate coupled to the second terminal, a fifth drain coupled to the first terminal, and a fifth source coupled to the power voltage; and
a fourth PMOS transistor comprising a sixth gate coupled to the first terminal, a sixth drain coupled to the second terminal, and a sixth source coupled to the power voltage.
21. The power management circuit as claimed in claim 20, wherein the first power switch is a fifth PMOS transistor having a seventh gate coupled to the power control signal.
22. The power management circuit as claimed in claim 21, wherein the predetermined level is a low logic level.
23. The power management circuit as claimed in claim 22, further comprising a second power switch coupled between the second source, the fourth source and the ground voltage, wherein the second power switch is turned off when the power control signal is at the predetermined level.
24. The power management circuit as claimed in claim 23, wherein the second switch is a third NMOS transistor having an eighth gate coupled to a reverse power control signal.
25. The power management circuit as claimed in claim 24, further comprising an inverter coupled between the seventh gate and the eighth gate.
26. The power management circuit as claimed in claim 24, wherein each of the first NMOS transistor, the first PMOS transistor, the second PMOS transistor, and the second PMOS transistor comprises a first gate oxide layer and a first threshold voltage.
27. The power management circuit as claimed in claim 26, wherein each of the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor and the third NMOS transistor comprises a second gate oxide layer thicker than the first gate oxide layer.
28. The circuit for power management as claimed in claim 26, wherein each of the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor and the third NMOS transistor comprises a second threshold voltage higher than the first threshold voltage.
29. The power management circuit as claimed in claim 19, wherein the memory cell is a static random access memory.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. A method for producing a colloidal dispersion of nanoparticles of at least one conductive material in a dense fluid medium, the method comprising the steps of:
(a) providing a reaction vessel for containing the dense fluid medium;
(b) charging the dense fluid medium into the reaction vessel;
(c) providing a rotatable first electrode comprising a first conductive material, the first electrode immersed within the dense fluid medium;
(d) providing a static second electrode comprising a second conductive material, the second electrode immersed within the dense fluid medium and being near to the first electrode;
(e) rotating the first electrode such that the dense medium is circulated between the first and second electrodes; and
(f) imposing an electric potential between the rotating first electrode and the second electrode to create a discharge zone, the electric potential being sufficiently high to dislocate nanoparticles of at least one of the first conductive material or the second conductive material from the respective electrode.
2. The method of claim 1 including the step of passing a gas through the discharge zone.
3. The method claim 2 wherein the gas is a reactive or inert gas.
4. The method of claim 1 wherein the second electrode is hollow and includes at least one conduit for passage of the dense fluid medium.
5. The method of claim 1 wherein at least one of the first conductive material or the second conductive material comprises an electrical conductor selected from the group consisting of metals, carbon or combinations thereof.
6. The method of claim 1 wherein at least one of the first conductive material or the second conductive material comprises an electrical conductor selected from the group consisting of aluminum, antimony, bismuth, carbon, copper, gold, iron, lead, molybdenum, nickel, platinum, silver, tin, tungsten, zinc, rare earths or combinations thereof.
7. The method of claim 1 wherein at least one of the first conductive material or the second conductive material comprises silver.
8. The method of claim 1 wherein the nanoparticles have an average diameter of less than about 100 nm as determined by scanning electron microscopy.
9. The method of claim 1 wherein the nanoparticles have an average diameter of less than about 50 nm as determined by scanning electron microscopy.
10. The method of claim 1 wherein the nanoparticles have an average diameter of less than about 20 nm as determined by scanning electron microscopy.
11. The method of claim 1 wherein the nanoparticles have an average diameter of less than about 10 nm as determined by scanning electron microscopy.
12. The method of claim 1 wherein the first electrode rotates at a speed of up to about 5000 RPM.
13. The method of claim 12 wherein the first electrode rotates at a speed of at least about 1000 RPM.
14. The method of claim 1 wherein the first electrode and the second electrode each comprise at least one planar surface, wherein the planar surface of the first electrode is substantially parallel to the planar surface of the second electrode.
15. The method of claim 14 wherein the substantially planar parallel surfaces are separated by a gap of about 1 mm.
16. The method of claim 14 wherein the rotating electrode comprises at least one pin made of the first conducting material, the pin projecting from the planar surface of the first electrode towards the planar surface of the second electrode.
17. The method of claim 14 wherein the planar surface of the first electrode and the planar surface of the second electrode are each disk shaped.
18. The method of claim 14 wherein the first electrode comprises multiple pins made of the first conducting material, the pins projecting from the planar surface of the first electrode towards the planar surface of the second electrode.
19. The method of claim 1 8 wherein the pins are arrayed in a spiral pattern.
20. The method of claim 18 wherein the distance between the pins and the second electrode is about 0.5 mm.
21. The method of claim 1 wherein the electric potential is about 200 DCV.
22. The method of claim 1 wherein the conductive material of both the first electrode and the second electrode comprises silver, the nanoparticles have an average diameter of less than about 20 nm as determined by scanning electron microscopy, the first electrode and the second electrode each comprise at least one planar surface, wherein the planar surface of the first electrode is substantially parallel to the planar surface of the second electrode, the first electrode comprises multiple pins made of the first conducting material, the pins projecting from the planar surface of the first electrode towards the planar surface of the second electrode, wherein the pins are arrayed in a spiral pattern.
23. The method of claim 1 wherein the dense medium comprises water with bacteria therein and the method is carried out for a time sufficient to kill the bacteria.
24. The colloidal dispersion of nanoparticles of at least one conductive material other than silver in a fluid medium produced by the method of claim 1.
25. A colloidal dispersion of nanoparticles of at least one conductive material in a fluid medium, wherein the conductive material comprises an electrical conductor selected from the group consisting of aluminum, antimony, bismuth, carbon, copper, gold, iron, lead, molybdenum, nickel, platinum, silver, tin, tungsten, zinc or combinations thereof.
26. The colloidal dispersion of claim 25 wherein the nanoparticles have a diameter of less than about 100 nm.
27. The colloidal dispersion of claim 25 wherein the nanoparticles have a diameter of less than about 20 nm.
28. The colloidal dispersion of claim 25 wherein the nanoparticles have a diameter of less than about 10 nm.
29. A colloidal dispersion of nanoparticles of silver wherein (i) the nanoparticles have an average particle size less than about 10 nm; (ii) the colloidal dispersion has a silver concentration of less than 3 ppm; and (iii) a 200:1 dilution of the colloidal dispersion is at least 98% effective in killing salmonella typhimurium and Etrobacter agglomerans.
30. A dense phase plasma discharge apparatus comprising:
(a) a chamber forming a reaction vessel for a dense medium;
(b) a first electrode mounted for rotation about an axis in the chamber having an end piece of conductive material with a planar surface and a plurality of pins in an array projecting from the planar surface;
(c) a second electrode mounted in the chamber and having an end piece of conductive material with a planar surface;
the planar surfaces of the end pieces of the first and second electrodes separated from each other by a gap.
31. The apparatus of claim 30 wherein the end pieces of the first and second electrodes including the pins on the one end piece are formed of silver.
32. The apparatus of claim 30 including a motor coupled to the first electrode to selectively drive the first electrode in rotation.
33. The apparatus of claim 31 wherein the motor is coupled to the first electrode by a magnetic coupling system.
34. The apparatus of claim 30 wherein the pins are formed in the end piece of the first electrode in a spiral array.
35. The apparatus of claim 34 wherein the electrode end piece having the pins therein has a cylindrically-shaped, disc cross-section end piece terminated in a ceramic holder in which the pins are mounted.
36. The apparatus of claim 30 wherein the pins in the pin array are formed of silver.
37. The apparatus of claim 30 wherein the first electrode mounted for rotation is an upper electrode, and wherein the second electrode is a lower electrode and has channels therein for recirculation of the reaction media in the reaction vessel.
38. The apparatus of claim 30 wherein the distance between the pins and the planar surface of the end piece of the second electrode is about 0.5 mm or less.
39. A method of producing colloidal silver comprising:
(a) providing a dense medium plasma discharge apparatus comprising:
(1) a chamber forming a reaction vessel for a dense medium;
(2) a first electrode mounted for rotation about an axis in the chamber having an end piece of conductive material with a planar surface and a plurality of pins in an array projecting from the planar surface;
(3) a second electrode mounted in the chamber and having an end piece of conductive material with a planar surface;

the planar surfaces of the end pieces of the first and second electrodes separated from each other by a gap, and wherein the end pieces of the first and second electrodes are formed of silver;
(b) immersing the first and second electrodes in a dense medium;
(c) rotating the first electrode with respect to the second electrode; and
(d) imposing an electrical potential between the first electrode and the second electrode to create a discharge zone, the electrical potential being sufficiently high to dislocate nanoparticles of silver from the first and second electrodes.
40. The method of claim 39 including the step of passing a gas through the discharge zone.
41. The method of claim 39 wherein the gas is a reactive or inert gas.
42. The method of claim 39 wherein the dense medium comprises water with bacteria therein and the method is carried out for a time sufficient to kill the bacteria.
43. The method of claim 39 wherein the dense medium comprises water and further including the step of adding the dense medium produced by the method of claim 39 to water contaminated with bacteria to kill the bacteria.