All The Claims

1. A computer implemented method for managing user session load in a network of servers, the method comprising the steps of:
assigning a plurality of servers as primary host servers;
assigning to each one of the primary host servers an equal portion of the user session load;
assigning each one of the primary host servers as a backup server for a rest of the primary host servers, such that each primary host server simultaneously functions as both a primary host server maintaining current session information for its assigned session load and as a backup server for each of said rest of the primary host servers, maintaining current session information for the session loads of each of said rest of the primary host servers;
as user session information for each user session is received, maintaining user session information for each user session on both the primary host servers to which that user session is assigned and on each of said backup servers for that primary host server, such that both said primary host servers and said backup servers simultaneously store and maintain current user session information; and
responsive to one of the primary host servers failing, distributing the user session load of the failed primary host server equally on said rest of the primary host servers, which, in their simultaneous capacity as backup servers, have already stored current user session information for the session load of the failed primary host server.
2. A computer implemented method for managing user session load in a network of servers, the method comprising the steps of:
assigning a plurality of servers as primary host servers;
assigning to each one of the primary host servers a portion of the user session load;
assigning each one of the primary host servers as a backup server for a plurality of a rest of the primary host servers, such that each primary host server simultaneously functions as both a primary host server maintaining current session information for its assigned session load and as a backup server for the plurality of the rest of the primary host servers, maintaining current session information for the session loads of each of the plurality of the rest of the primary host servers;
as user session information for each user session is received, maintaining user session information for each user session on both the primary host servers to which that user session is assigned and on each of said backup servers for that primary host server, such that both said primary host servers and said backup servers simultaneously store and maintain current user session information; and
responsive to one of the primary host servers failing, distributing the user session load of the failed primary host server on the plurality of the rest of the primary host servers, which, in their simultaneous capacity as corresponding backup servers, have already stored current user session information for the session load of the failed primary host server.
3. The method of claim 2, wherein the step of assigning to each one of the primary host servers includes assigning to each one of the primary host servers an equal portion of the user session load.
4. The method of claim 2, wherein the step of assigning each one of the primary host servers as a backup server includes assigning each one of the primary host servers as a backup server for the rest of the primary host servers.
5. The method of claim 2, wherein the distributing step includes distributing the corresponding portion of the user session load equally on the backup servers, which maintain current user session information.
6. A computer system for managing user session load in a network of servers, the computer system comprising:
means for assigning a plurality of servers as primary host servers;
means for assigning to each one of the primary host servers an equal portion of the user session load;
means for assigning each one of the primary host servers as a backup server for a rest of the primary host servers, such that each primary host server simultaneously functions as both a primary host server maintaining current session information for its assigned session load and as a backup server for each of said rest of the primary host servers, maintaining current session information for the session loads of each of said rest of the primary host servers;
means for maintaining user session information for each user session is received, maintaining user session information for each user session on both the primary host servers to which that user session is assigned and on each of said backup servers for that primary host server, such that both said primary host servers and said backup servers simultaneously store and maintain current user session information; and
means for, responsive to one of the primary host servers failing, distributing the user session load of the failed primary host server equally on said rest of the primary host servers, which, in their simultaneous capacity as backup servers, have already stored current user session information for the session load of the failed primary host server.
7. At least one computer readable medium containing a computer program product for managing user session load in a network of servers, the computer program product comprising:
program code for assigning a plurality of servers as primary host servers;
assigning to each one of the primary host servers an equal portion of the user session load;
program code for assigning each one of the primary host servers as a backup server for a rest of the primary host servers, such that each primary host server simultaneously functions as both a primary host server maintaining current session information for its assigned session load and as a backup server for each of said rest of the primary host servers, maintaining current session information for the session loads of each of said rest of the primary host servers;
program code for, as user session information for each user session is received, maintaining user session information for each user session on both the primary host servers to which that user session is assigned and on each of said backup servers for that primary host server, such that both said primary host servers and said backup servers simultaneously store and maintain current user session information; and
program code for, responsive to one of the primary host servers failing, distributing the user session load of the failed primary host server equally on said rest of other primary host servers, which, in their simultaneous capacity as backup servers, have already stored current user session information for the session load of the failed primary host server.
8. An apparatus for managing user session load in a network comprising:
a database for maintaining user session information; and
a processor configured for:
assigning a plurality of servers as primary host servers;
assigning to each one of the primary host servers an equal portion of the user session load;
assigning each one of the primary host servers as a backup server for a rest of the primary host servers, such that each primary host servers simultaneously functions as both a primary host server maintaining current session information for its assigned session load and as a backup server for each of said rest of the primary host servers, maintaining current session information for the session loads of each of said rest of the primary host servers;
as user session information for each user session is received, maintaining user session information for each user session on both the primary host servers to which that user session is assigned and on each of said backup servers for that primary host server, such that both said primary host servers and said backup servers simultaneously store and maintain current user session information; and
responsive to one of the primary host servers failing, distributing the user session load of the failed primary host server equally on said rest of the primary host servers, which, in their simultaneous capacity as backup servers, have already stored current user session information for the session load of the failed primary host server.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A disk array device comprising:
a storage unit;
a controller for controlling storage of data into said storage unit;
a power unit for supplying power to each section;
a fan for air cooling an interior of a housing;
a backboard for connecting each section, the storage unit being connected to one surface of the backboard through a connector;
a cooling function of allowing cooling air to flow into the housing by an operation of said fan and exhausting the cooling air from the housing via a region to which said storage unit is installed and a vent hole provided in said backboard; and
a shutter having a mechanism which corresponds to the vent hole of said backboard and in which an open area rate of said vent hole is adjusted by opening in accordance with mounting of said storage unit and closing in accordance with unmounting thereof.
2. The disk array device according to claim 1,
wherein said housing has a construction in which a region where a plurality of said storage units are mounted in a row is arranged on one side of the housing through the backboard in-between and said fan and said power unit arranged on the other side, and
has a vent passage in which said cooling air flows by an operation of said fan from a side of a surface on which said storage unit of the housing is mounted and is exhausted from a side of a surface mounted on said fan and said power unit of the housing.
3. The disk array device according to claim 1,
wherein said vent hole is provided in units of a mounting location of said storage unit and said shutter is provided in units of said vent hole.
4. The disk array device according to claim 1,
wherein said shutter has such a construction as to keep part of a region of said vent hole open with said shutter being closed to the maximum under an unmounted condition of said storage unit, and, by the construction of said shutter, volumes of the cooling air at a mounted section of said storage unit and that of at an unmounted section are adjusted so as to be almost the same.
5. The disk array device according to claim 1,
wherein said shutter has a construction in which an area closing said vent hole is designed in such a manner that a volume of the cooling air at a mounted section of said storage unit is greater than that at an unmounted section.
6. The disk array device according to claim 1,
wherein said shutter has a mechanism of being openedclosed like a door and of being open-pushed by a convex structure provided on a side of a backboard connection surface of said storage unit when said storage unit is mounted.
7. The disk array device according to claim 1,
wherein said shutter is arranged and formed to guide flow of the cooling air in accordance with arrangement of a cooled object portion before and after said vent hole.
8. The disk array device according to claim 1,
wherein said shutter has a mechanism of being opened by such motion that a convex structure provided on a surface of said backboard, on which said storage unit is mounted, is pressed by said storage unit when said storage unit is mounted.
9. The disk array device according to claim 1,
wherein said shutter has such a vent-passage configuration as to be provided to a support structure provided behind said backboard in the housing and to seal a region from the vent hole of said backboard to the shutter provided to said support structure.
10. The disk array device according to claim 1,
wherein said shutter has such a mechanism as to be provided to a guide portion for mounting said storage unit in a region located on a side on which said storage unit is mounted in the housing and to open by insertion of said storage unit and close by its removal.
11. The disk array device according to claim 1, further comprising:
a rectifying means being so that, at a boundary portion between a mounted section and an unmounted section of said storage unit in the housing, a region of the vent passage corresponding to a mounting position of said storage unit is formed into a conduit construction independent from an adjacent region.
12. The disk array device according to claim 1,
wherein said shutter is provided so as to correspond to both the vent hole corresponding to mounting and cooling of said storage unit and other vent hole other than it on said backboard, and
a volume of the cooling air at said other vent hole is controlled by opening and closing said shutter in accordance with a mounting condition of said storage unit.
13. A disk array device comprising:
a storage unit;
a controller for controlling storage of data into said storage unit;
a power unit for supplying power to each section;
a fan for air cooling an interior of a housing;
a backboard for connecting each section, the storage unit being connected to one surface of the backboard through a connector;
a cooling function of allowing cooling air to flow into the housing by an operation of said fan and exhausting the cooling air from the housing via a region to which said storage unit is installed and a vent hole provided in said backboard;
a shutter having a mechanism which corresponds to the vent hole of said backboard and in which an open area rate of said vent hole is adjusted by opening in accordance with mounting of said storage unit and closing in accordance with unmounting thereof; and
a control means for adjusting a volume of said cooling air by controlling the open area rate of said vent hole in accordance with judgment of a device condition related to cooling.
14. The disk array device according to claim 13,
wherein said control means controls the open area rate of said vent hole in combination with control of a fan rotating speed using said fan based on the judgment of the device condition related to said cooling.
15. The disk array device according to claim 13,
wherein said shutter is provided so as to correspond to both the vent hole corresponding to mounting and cooling of said storage unit and other vent hole other than it on said backboard, and
a volume of the cooling air at said other vent hole is controlled by opening and closing said shutter in accordance with the judgment of the device condition.
16. The disk array device according to claim 13,
wherein said control means comprises:
a shutter openingclosing section located near said backboard and carrying out an operation of adjusting the openingclosing of said shutter;
a processing section for controlling an operation of said shutter openingclosing section in accordance with the judgment of said device condition.
17. The disk array device according to claim 16,
wherein said power unit has said processing section and judges a power condition in the housing, as the device condition related to the cooling.
18. The disk array device according to claim 16,
wherein said control unit has said processing section and judges a device load condition and a condition related to mounting and operating of said storage unit, as the device condition related to said cooling.
19. The disk array device according to claim 16,
wherein said shutter has a mechanism for making openingclosing operations on a back side of said backboard, and
said shutter openingclosing section has a slide portion for making a slide operation in parallel to a surface of said backboard, and has a mechanism for opening and closing said shutter by contact of said slide portion with said shutter located on a back surface side of said backboard.
20. The disk array device according to claim 16,
wherein said power unit includes: a fan on a back surface side of the housing; said shutter openingclosing section on a connection surface side of the backboard; and a circuit for controlling an operation of said fan and said shutter openingclosing section by a control signal as said processing section.

1. A semiconductor device comprising:
a first nitride semiconductor layer;
a second nitride semiconductor layer formed on the first nitride semiconductor layer and having such a composition as to generate a 2-dimensional electron gas layer in an upper portion of the first nitride semiconductor layer; and
an ohmic electrode formed selectively on the second nitride semiconductor layer, wherein the second nitride semiconductor layer includes a contact area having at least one inclined surface which is inclined toward an upper surface of the first nitride semiconductor layer and defining a depressed cross-sectional configuration and
the ohmic electrode is formed on the contact area.
2. The semiconductor device of claim 1, wherein a lowermost portion of the contact area is positioned at a distance of not less than 1 nm and not more than 1 \u03bcm from the 2-dimensional electron gas layer.
3. The semiconductor device of claim 1, wherein a bottom portion of the contact area is formed with a striped pattern which is projecting and depressed in cross section with a periodicity of not less than 1 nm and not more than 1 \u03bcm.
4. The semiconductor device of claim 1, wherein the ohmic electrode is formed to cover at least one of the inclined surface of the contact area.
5. The semiconductor device of claim 1, wherein the ohmic electrode is composed of one layer made of a metal selected from the group consisting of titanium, strontium, aluminum, niobium, vanadium, zirconium, hafnium, chromium, tungsten, molybdenum, rhodium, rhenium, cobalt, and lanthanum, of at least two layers each made of a metal selected from the group, of an alloy layer containing at least two metals selected from the group, or of a conductive compound containing at least one metal selected from the group and oxygen, nitrogen, or boron.
6. The semiconductor device of claim 1, wherein
a general formula of a material composing the first nitride semiconductor layer is AlxInyGa1-x-yN (where x and y satisfy 0\u2266x\u22661, 0\u2266y\u22661, and 0\u2266x+y\u22661),
a general formula of a material composing the second nitride semiconductor layer is AluInvGa1-u-vN (where u and v satisfy 0\u2266u\u22661, 0\u2266v\u22661, and 0\u2266u+v\u22661), and
a composition of the second nitride semiconductor layer and a composition of the first nitride semiconductor layer are such that u representing an Al ratio is larger than x representing an Al ratio and v representing an In ratio is smaller than y representing an In ratio.
7. A semiconductor device comprising:
a first nitride semiconductor layer;
a second nitride semiconductor layer formed on the first nitride semiconductor layer and having such a composition as to generate a 2-dimensional electron gas layer in an upper portion of the first nitride semiconductor layer; and
an ohmic electrode formed selectively on the second nitride semiconductor layer, wherein the second nitride semiconductor layer has a contact area defining a depressed cross-sectional configuration,
the contact area has a bottom portion containing an impurity having a conductivity introduced therein and a sidewall composed of an insulating film on an inner wall surface thereof, and
the ohmic electrode is formed to cover an inner side of the contact area including the sidewall.
8. The semiconductor device of claim 7, wherein the ohmic electrode is composed of one layer made of a metal selected from the group consisting of titanium, strontium, aluminum, niobium, vanadium, zirconium, hafnium, chromium, tungsten, molybdenum, rhodium, rhenium, cobalt, and lanthanum, of at least two layers each made of a metal selected from the group, of an alloy layer containing at least two metals selected from the group, or of a conductive compound containing at least one metal selected from the group and oxygen, nitrogen, or boron.
9. The semiconductor device of claim 7, wherein
a general formula of a material composing the first nitride semiconductor layer is AlxInyGa1-x-yN (where x and y satisfy 0\u2266x\u22661, 0\u2266y\u22661, and 0\u2266x+y\u22661),
a general formula of a material composing the second nitride semiconductor layer is AluInvGa1-u-vN (where u and v satisfy 0\u2266u\u22661, 0\u2266v\u22661, and 0\u2266u+v\u22661), and
a composition of the second nitride semiconductor layer and a composition of the first nitride semiconductor layer are such that u representing an Al ratio is larger than x representing an Al ratio and v representing an In ratio is smaller than y representing an In ratio.
10. A semiconductor device comprising:
a first nitride semiconductor layer;
a second nitride semiconductor layer formed on the first nitride semiconductor layer and having such a composition as to generate a 2-dimensional electron gas layer in an upper portion of the first nitride semiconductor layer;
a third nitride semiconductor layer formed on the second nitride semiconductor layer and smaller in band gap energy than the second nitride semiconductor layer; and
an ohmic electrode formed selectively on the third nitride semiconductor layer, wherein
the third nitride semiconductor layer includes a contact area having at least one inclined surface which is inclined toward an upper surface of the second nitride semiconductor layer and defining a depressed cross-sectional configuration and
the ohmic electrode is formed on the contact area.
11. The semiconductor device of claim 10, wherein the ohmic electrode is composed of one layer made of a metal selected from the group consisting of titanium, strontium, aluminum, niobium, vanadium, zirconium, hafnium, chromium, tungsten, molybdenum, rhodium, rhenium, cobalt, and lanthanum, of at least two layers each made of a metal selected from the group, of an alloy layer containing at least two metals selected from the group, or of a conductive compound containing at least one metal selected from the group and oxygen, nitrogen, or boron.
12. The semiconductor device of claim 10, wherein
a general formula of a material composing the first nitride semiconductor layer is AlxInyGa1-x-yN (where x and y satisfy 0\u2266x\u22661, 0\u2266y\u22661, and 0\u2266x+y\u22661),
a general formula of a material composing the second nitride semiconductor layer is AluInvGa1-u-vN (where u and v satisfy 0\u2266u\u22661, 0\u2266v\u22661, and 0\u2266u+v\u22661), and
a composition of the second nitride semiconductor layer and a composition of the first nitride semiconductor layer are such that u representing an Al ratio is larger than x representing an Al ratio and v representing an In ratio is smaller than y representing an In ratio.
13. The semiconductor device of claim 10, wherein
a general formula of a material composing the first nitride semiconductor layer is AlxInyGa1-x-yN (where x and y satisfy 0\u2266x\u22661, 0\u2266y\u22661, and 0\u2266x+y\u22661),
a general formula of a material composing the second nitride semiconductor layer is AluInvGa1-u-vN (where u and v satisfy 0\u2266u\u22661, 0\u2266v\u22661, and 0\u2266u+v\u22661),
a general formula of a material composing the third nitride semiconductor layer is AllInmGa1-l-mN (where l and m satisfy 0\u2266l\u22661, 0\u2266m\u22661, and 0\u2266l+m\u22661),
a composition of the second nitride semiconductor layer and a composition of the first nitride semiconductor layer are such that u representing an Al ratio is larger than x representing an Al ratio and v representing an In ratio is smaller than y representing an In ratio, and
a composition of the third nitride semiconductor layer and the composition of the second nitride semiconductor layer are such that 1 representing an Al ratio is smaller than u representing the Al ratio.
14. The semiconductor device of claim 1, wherein
the second nitride semiconductor layer includes two contact areas,
a gate electrode is formed on the second nitride semiconductor layer,
the gate electrode is between the one contact area and the other contact area, and
depths of the inclined surfaces of the two contact areas become shallower with approach toward the gate electrode.
15. The semiconductor device of claim 1, wherein the depressed cross-sectional configuration of the contact area is V-shaped.
16. The semiconductor device of claim 10, wherein the inclined surface of the contact area reaches into the second nitride semiconductor layer.
17. The semiconductor device of claim 16, wherein the ohmic electrode is formed to cover both the inclined surface of the third nitride semiconductor layer and the inclined surface of the second nitride semiconductor layer.
18. The semiconductor device of claim 10, wherein
the third nitride semiconductor layer includes two contact areas,
a gate electrode is formed on the third nitride semiconductor layer,
the gate electrode is between the one contact area and the other contact area, and
depths of the inclined surfaces of the two contact areas become shallower with approach toward the gate electrode.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A converter, comprising:
a comparator having a first input operable to receive a first signal, a second input operable to receive a second signal, and an output;
a switch for sinking a portion of said first signal, wherein said switch is responsive to said output; and
an integrator including a capacitor connected between said first input and a ground, wherein said first signal is a voltage developed by said integrator when a current proportional to the absolute temperature is applied thereto.
2. The converter of claim 1 wherein said second signal is a reference signal.
3. The converter of claim 1 wherein said second signal is inversely proportional to the absolute temperature.
4. The converter of claim 1 wherein said switch is a transistor.
5. A converter, comprising:
a comparator having a first input operable to receive a first signal a second input operable to receive a second signal, and an output;
a switch responsive to said output for sinking a portion of said first signal, and wherein said portion of said first signal that is sunk by said switch is equal to a current that is inversely proportional to the absolute temperature; and
an integrator connected to said first input, wherein said first signal is a voltage developed by said integrator when a current proportional to the absolute temperature is applied thereto.
6. A temperature measurement system, comprising:
a temperature sensor;
a converter responsive to said temperature sensor, said converter comprising:
a comparator having a first input operable to receive a first signal from the sensor, a second input operable to receive a second signal from the sensor, and an output;
a switch for sinking a portion of said first signal, wherein said switch is responsive to said output; and
an integrator including a capacitor connected between said first input and a ground, wherein said first signal is a voltage developed by said integrator when a current proportional to the absolute temperature is applied thereto; and

a counter, responsive to said output, for producing an output signal.
7. The temperature measurement system of claim 6 wherein said second signal is a reference signal.
8. The temperature measurement system of claim 6 wherein said second signal is inversely proportional to the absolute temperature.
9. The temperature measurement system of claim 6 further comprising a plurality of temperature sensors and a multiplexer, said multiplexer operable to receive a signal from each of said plurality of temperature sensors and to conduct, to said converter, the signal from a selected one of said plurality of temperature sensors.
10. The temperature measurement system of claim 6 wherein said temperature sensor includes a vertical bipolar transistor, a lateral bipolar transistor, or a CMOS transistor.
11. The temperature measurement system of claim 6 wherein said switch is a transistor.
12. The temperature measurement system of claim 6 further comprising a controller for regulating the operation of said counter.
13. The temperature measurement system of claim 12 wherein said controller further regulates one of said converter or said temperature sensor.
14. A temperature measurement system, comprising:
a temperature sensor;
a converter responsive to said temperature sensor, said converter comprising:
a comparator having a first input operable to receive a first signal from the sensor, a second input operable to receive a second signal from the sensor, and an output;
a switch responsive to said output for sinking a portion of said first signal, and wherein said portion of said first signal that is sunk by said switch is equal to a current that is inversely proportional to the absolute temperature; and
an integrator connected to said first input, wherein said first signal is a voltage developed by said integrator when a current proportional to the absolute temperature is applied thereto; and

a counter, responsive to said output, for producing an output signal.
15. A memory system, comprising: a memory module; a temperature measurement module; and a memory controller for communicating with said memory module and said temperature module via a system bus, wherein said temperature measurement module comprises:
at least one temperature sensor;
a converter responsive to said at least one temperature sensor, wherein said converter comprises:
a comparator having a first input operable to receive a first signal from the sensor, a second input operable to receive a second signal from the sensor, and an output;
a switch for sinking a portion of said first signal, wherein said switch is responsive to said output; and
an integrator including a capacitor connected between said first input and a ground, wherein said first signal is a voltage developed by said integrator when a current proportional to the absolute temperature is applied thereto; and

a counter, responsive to said output, for producing an output signal.
16. The memory system of claim 15 wherein said second signal is a reference signal.
17. The memory system of claim 15 wherein said second signal is inversely proportional to the absolute temperature.
18. The memory system of claim 15 wherein said memory module is a dual-inline-memory-module having one or more synchronous dynamic random access memory devices.
19. The memory system of claim 15 wherein said temperature measurement module further comprises a plurality of temperature sensors and a multiplexer, said multiplexer operable to receive a signal from each of said plurality of temperature sensors and to conduct, to said converter, the signal from a selected one of said plurality of temperature sensors.
20. The memory system of claim 15 wherein said temperature sensor includes a vertical bipolar transistor, a lateral bipolar transistor, or a CMOS transistor.
21. The memory system of claim 15 wherein said switch is a transistor.
22. The memory system of claim 15 wherein said temperature measurement module further comprises a controller for regulating the operation of said counter.
23. The memory system of claim 22 wherein said controller further regulates one of said converter or said at least one temperature sensor.
24. A memory system, comprising: a memory module; a temperature measurement module; and a memory controller for communicating with said memory module and said temperature module via a system bus, wherein said temperature measurement module comprises:
at least one temperature sensor;
a converter responsive to said at least one temperature sensor, wherein said converter comprises:
a comparator having a first input operable to receive a first signal from the sensor, a second input operable to receive a second signal from the sensor, and an output;
a switch for responsive to said output for sinking a portion of said first signal, and wherein said portion of said first signal that is sunk by said switch is equal to a current that is inversely proportional to the absolute temperature; and
an integrator connected to said first input, wherein said first signal is a voltage developed by said integrator when a current proportional to the absolute temperature is applied thereto; and

a counter, responsive to said output, for producing an output signal.