All The Claims

1. An intermediate electrical connector comprising:
a circuit board having a plurality of contact portions arranged on opposed edges thereof to which two connectors are attached in opposed directions, respectively, and a pair of supported portions provided at ends thereof in an arrangement direction of said contact portions; and
a guide member holding said circuit board and guiding said connectors to a position for connection with said circuit board, said guide member having a support portion being brought into contact with an face of said circuit board and positioning said circuit board at a predetermined position and a pair of columns each having a holding portion provided at a position corresponding to that of said supported portion, wherein at least one of said supported portions has an asymmetric shape in said opposed direction and said arrangement direction of said contact portions and at least one of said holding portions has a corresponding shape for receiving said asymmetric shape of said supported portion.
2. The intermediate electrical connector according to claim 1, wherein said supported portion of said circuit board has a raised portion extending asymmetrically and said corresponding shape of said holding portion has a stepped section which abuts against an end surface of said raised portion.
3. The intermediate electrical connector according to claim 1, wherein said supported portion of said circuit board has a hole or a cut-off portion at an asymmetric position therein and said corresponding shape of said holding portion has a projection which is plugged into said hole or said cut-off portion.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of fabricating a semiconductor device, the method comprising:
providing a substrate having a top surface and a bottom surface opposite to each other;
forming an epitaxial layer on the top surface of the substrate;
forming a lower pad contacting the top surface of the substrate;
forming a semiconductor chip on the epitaxial layer, the semiconductor chip including a first electrode, a second electrode, and a third electrode;
forming a lower via-hole penetrating the substrate, the lower via-hole exposing the lower pad; and
forming a lower metal layer covering the bottom surface of the substrate, the lower metal layer extending into the lower via-hole and contacting the lower metal layer,
wherein forming the lower pad comprises:
removing a portion of the epitaxial layer to expose the top surface of the substrate; and
forming the lower pad directly on the exposed top surface of the substrate.
2. The method of claim 1, further comprising:
forming an insulating layer exposing the first electrode on the semiconductor chip;
forming an upper metal layer contacting the first electrode on the insulating layer;
forming a supporting substrate having an upper via-hole on the upper metal layer; and
forming an upper pad extending into the upper via-hole on the supporting substrate,
wherein the upper pad is electrically connected to the first electrode through the upper metal layer.
3. The method of claim 1, wherein forming the lower via-hole comprises:
polishing the bottom surface of the substrate; and
selectively etching the polished bottom surface of the substrate to form the lower via-hole exposing the lower pad.
4. The method of claim 1, wherein the lower pad is disposed between the substrate and the second electrode; and
wherein the lower pad vertically overlaps with the second electrode.
5. The method of claim 1, wherein one of the first and second electrodes is a source electrode;
wherein the other of the first and second electrodes is a drain electrode; and
wherein the third electrode is a gate electrode.
6. The method of claim 1, wherein one of the first and second electrodes is an emitter electrode;
wherein the other of the first and second electrodes is a collector electrode; and
wherein the third electrode is a base electrode.
7. A semiconductor device comprising:
a substrate having a top surface and a bottom surface opposite to each other, the substrate having a lower via-hole, and the lower via-hole penetrating the substrate;
an epitaxial layer disposed on the top surface of the substrate, the epitaxial layer having an opening;
a lower pad disposed in the opening;
a semiconductor chip disposed on the epitaxial layer, the semiconductor chip including a first electrode, a second electrode, and a third electrode; and
a lower metal layer covering the top surface of the substrate, the lower metal layer connected to the lower pad through the lower via-hole,
wherein the opening exposes the top surface of the substrate.
8. The semiconductor device of claim 7, wherein the lower pad comprises:
a first surface connected to the second electrode;
a second surface opposite to the first surface; and
a sidewall linking the first surface and the second surface,
wherein the sidewall of the lower pad is in contact with the epitaxial layer.
9. The semiconductor device of claim 7, further comprising:
an insulating layer disposed on the semiconductor chip and exposing the first electrode;
an upper metal layer covering the insulating layer and connected to the first electrode;
a supporting substrate disposed on the upper metal layer and having an upper via-hole; and
an upper pad disposed on the supporting substrate and extending into the upper via-hole,
wherein the upper via-hole exposes the upper metal layer.
10. The semiconductor device of claim 7, wherein the first electrode is a drain electrode;
wherein the second electrode is a source electrode; and
wherein the third electrode is a gate electrode.
11. A semiconductor device comprising:
a substrate having a top surface and a bottom surface opposite to each other;
a semiconductor chip disposed on the top surface of the substrate, the semiconductor chip including a first electrode, a second electrode, and a third electrode;
an upper metal layer disposed on the semiconductor chip, the upper metal layer electrically connected to the first electrode;
a supporting substrate disposed on the upper metal layer;
an upper pad disposed on the supporting substrate, the upper pad electrically connected to the upper metal layer;
a lower pad disposed between the substrate and the second electrode; and
a lower metal layer covering the bottom surface of the substrate,
wherein the substrate has a lower via-hole exposing the lower pad; and
wherein the lower metal layer extends into the lower via-hole to be in contact with the lower pad.
12. The semiconductor device of claim 11, further comprising:
a buffer layer and a channel layer sequentially stacked on the top surface of the substrate.
13. The semiconductor device of claim 12, wherein the lower pad comprises:
a first surface contacting the second electrode;
a second surface spaced apart from the first surface and contacting the top surface of the substrate; and
a sidewall linking the first and second surfaces,
wherein the sidewall of the lower pad is in contact with the buffer layer and the channel layer.
14. The semiconductor device of claim 11, wherein the upper metal layer includes a first upper metal layer contacting the first electrode and a second upper metal layer contacting the second electrode; and
wherein the first upper metal layer is spaced apart from the second upper metal layer.
15. The semiconductor device of claim 11, wherein the upper pad is vertically spaced apart from the first electrode.
16. The semiconductor device of claim 11, wherein one of the first and second electrodes is a source electrode;
wherein the other of the first and second electrodes is a drain electrode; and
wherein the third electrode is a gate electrode.
17. The semiconductor device of claim 11, wherein the substrate has a thickness of about 10 \u03bcm to about 100 \u03bcm.

What is claimed is:

1. A fixing apparatus, comprising
a first rotating member;
first heating means for heating said first rotating member;
a second rotating member for forming a nip together with said first rotating member;
wherein a recording material bearing an unfixed image thereon is nipped and conveyed at said nip in such a manner that the unfixed image is in contact with said first rotating member, and the unfixed image is fixed by heating on the recording material,
voltage applying means for applying voltage to create potential difference between said first rotating member and said second rotating member; and
wherein said second rotating member has a conductive parting layer on a surface threreof,
second heating means for heating said second rotating member.
2. A fixing apparatus according to claim 1, wherein said voltage applying means applies a voltage to the surface of said second rotating member.
3. A fixing apparatus according to claim 1, wherein said conductive parting layer of said second rotating member is a fluororesin layer containing a conductive agent.
4. A fixing apparatus according to claim 1, wherein said conductive parting layer of said second rotating member has a surface resistance of 106 or less.
5. A fixing apparatus according to claim 1, wherein said second rotating member has an elastic layer inside said conductive parting layer.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A circuit structure, comprising:
a first circuit board, comprising:
a first ground plane layout, comprising at least one ground plane; and
a second ground plane layout, comprising at least one ground plane, wherein the first ground plane layout is not electrically connected to the second ground plane layout within the first circuit board.
2. The circuit structure of claim 1, wherein the first ground plane layout and the second ground plane layout have no direct contact within the first circuit board.
3. The circuit structure of claim 1, further comprising:
a first circuit component, mounted on the first circuit board and electrically connected to the first ground plane layout; and
a second circuit component, mounted on the first circuit board and electrically connected to the second ground plane layout.
4. The circuit structure of claim 3, wherein the first circuit component is an oscillator.
5. The circuit structure of claim 4, wherein the second circuit component is a signal processor of a global navigation satellite system (GNSS), and the oscillator is for providing an oscillating signal associated with operations of the signal processor.
6. The circuit structure of claim 3, wherein the first ground plane layout comprises a ground plane with a hollow region covered by the first circuit component in a thickness direction of the first circuit board.
7. The circuit structure of claim 3, wherein the first circuit board has at least one layer on which no ground plane overlapped with the first ground plane layout in a thickness direction of the first circuit board is disposed.
8. The circuit structure of claim 7, wherein the first circuit board has no ground plane overlapped with the first ground plane layout in the thickness direction of the first circuit board.
9. The circuit structure of claim 3, wherein within the first circuit board, the first ground plane layout is electrically connected to the first circuit component only.
10. The circuit structure of claim 1, further comprising:
a second circuit board, on which the first circuit board is mounted, the second circuit board comprising:
a third ground plane layout, electrically connected to the first ground plane layout, comprising at least one ground plane; and
a fourth ground plane layout, electrically connected to the second ground plane layout, comprising at least one ground layer, wherein the fourth ground plane layout is not electrically connected to the third ground plane layout within the second circuit board.
11. The circuit structure of claim 10, wherein the first ground plane layout is not overlapped with the fourth ground plane layout in a thickness direction of the first circuit board, and the second ground plane layout is not overlapped with third ground plane layout in the thickness direction of the first circuit board.
12. The circuit structure of claim 10, further comprising:
a first circuit component, mounted on the first circuit board and electrically connected to the first ground plane layout; and
a second circuit component, mounted on the first circuit board and electrically connected to the second ground plane layout.
13. The circuit structure of claim 12, wherein the first circuit component is an oscillator.
14. The circuit structure of claim 13, wherein the second circuit component is a signal processor of a global navigation satellite system (GNSS), and the oscillator is for providing an oscillating signal associated with operations of the signal processor.
15. The circuit structure of claim 10, further comprising:
at least one passive component, mounted on the second circuit board, for electrically connecting the third ground plane layout and the fourth ground plane layout.
16. The circuit structure of claim 15, wherein the third ground plane layout is electrically connected to the fourth ground plane layout through passive component(s) mounted on the second circuit board only.
17. The circuit structure of claim 15, wherein the passive component is a resistor or a low AC impedance inductor.
18. A circuit structure, comprising:
a circuit board, comprising:
a first ground plane layout, comprising at least one ground layer; and
a second ground plane layout, comprising at least one ground layer, wherein the first ground plane layout is not electrically connected to the second ground plane within the circuit board; and

at least a passive component, mounted on the circuit board, for electrically connecting the first ground plane layout to the second ground plane layout.
19. The circuit structure of claim 18, wherein the first ground plane layout is electrically connected to the second ground plane layout through passive component(s) mounted on the circuit board only
20. The circuit structure of claim 18, wherein the passive component is a resistor or a low AC impedance inductor.
21. The circuit structure of claim 18, further comprising:
a first circuit component, mounted on the circuit board and electrically connected to the first ground plane layout; and
a second circuit component, mounted on the circuit board and electrically connected to the second ground plane layout.
22. The circuit structure of claim 21, wherein the first circuit component is an oscillator.
23. The circuit structure of claim 22, wherein the second circuit component is a signal processor of a global navigation satellite system (GNSS), and the oscillator is for providing an oscillating signal associated with operations of the signal processor.
24. The circuit structure of claim 23, wherein the signal processor and the oscillator are mounted at different sides of the circuit board.
25. The circuit structure of claim 21, wherein the first ground plane layout has an inner hollow region covered by the first circuit component in a thickness direction of the circuit board.
26. The circuit structure of claim 21, wherein the circuit board has at least one layer on which no ground plane overlapped with the first ground plane layout in a thickness direction of the circuit board is disposed.
27. The circuit structure of claim 26, wherein the circuit board has no ground plane overlapped with the first ground plane layout in the thickness direction of the circuit board is disposed.