All The Claims

1. A computer program product to facilitate storing data in an operating environment having a plurality of domains, the computer program product comprising:
a non-transitory computer storage medium comprising a relational database for storing data of a plurality of domains as a three-dimensional data structure, the three-dimensional data structure comprising:
multiple columns and multiple rows defining a two-dimensional array of data cells, and at least one column of data cells of the array of data cells comprising a cell depth greater than zero, thereby defining the three-dimensional structure, and wherein the cell depth greater than zero indicates that multiple depth-wise data values are provided for the at least one data cell of the array of data cells, each depth-wise data value being associated with a different domain of the multiple relational domains, and wherein for each data cell of the at least one data cell, one depth-wise data value of the data cell associated with one domain is different from at least one other depth-wise data value of the data cell associated with another domain of the multiple relational domains; and
wherein the three-dimensional data structure further comprises at least one cell of the array of data cells having a depth of zero, meaning that the at least one data cell of zero depth is invariable for the multiple relational domains of the operating environment, and wherein the at least one data cell of zero depth contains an actual valid data value which is common to the multiple relational domains.
2. The computer program product of claim 1, wherein the at least one column of data cells of the array of data comprising a cell depth greater than zero has a depth equal to a number of domains of the plurality of domains.
3. The computer program product of claim 1, wherein the plurality of domains comprise a plurality of clusters of nodes.
4. The computer program product of claim 3, wherein the data comprises configuration information for at least one node of at least one cluster of the plurality of clusters.
5. A computer system for facilitating storing of data in an operating environment having a plurality of domains, said computer system comprising:
a non-transitory computer storage medium comprising a relational database for storing data of a plurality of domains; and
a processor in communication with the non-transitory computer storage medium, wherein data for the plurality of domains is stored in the relational database as a three-dimensional data structure, the three-dimensional data structure comprising:
multiple columns and multiple rows defining a two-dimensional array of data cells, and at least one column of data cells of the array of data cells comprising a cell depth greater than zero, thereby defining the three-dimensional structure, and wherein the cell depth greater than zero indicates that multiple depth-wise data values are provided for the at least one data cell of the array of data cells, each depth-wise data value being associated with a different domain of the multiple relational domains, and wherein for each data cell of the at least one data cell, one depth-wise data value of the data cell associated with one domain is different from at least one other depth-wise data value of the data cell associated with another domain of the multiple relational domains; and
wherein the three-dimensional data structure further comprises at least one cell of the array of data cells having a depth of zero, meaning that the at least one data cell of zero depth is invariable for the multiple relational domains of the operating environment, and wherein the at least one data cell of zero depth contains an actual valid data value which is common to the multiple relational domains.
6. The computer system of claim 5, wherein the processor comprises logic to:
select a column of the three-dimensional data structure from which data is to be read;
determine, for the selected column, whether the selected column has a depth greater than zero;
index into the three-dimensional data structure to the identified domain to read the data value for that domain, in response to the determining indicating the selected column has a depth greater than zero;
read the data value in the selected column, in response to the determining indicating the column does not have a depth greater than zero; and
repeat one or more of the selecting, determining, indexing and reading for zero or more other columns of the three-dimensional data structure.
7. An article of manufacture comprising:
at least one non-transitory computer-readable medium having computer-readable program code logic to facilitate storing data in an operating environment having a plurality of domains, the computer-readable program code logic when executing performing:
storing data for multiple relational domains of a plurality of domains in a relational database as a three-dimensional data structure, said three-dimensional data structure comprising:
multiple columns and multiple rows defining a two-dimensional array of data cells, and at least one column of data cells of the array of data cells comprising a cell depth greater than zero, thereby defining the three-dimensional structure, and wherein the cell depth greater than zero indicates that multiple depth-wise data values are provided for the at least one data cell of the array of data cells, each depth-wise data value being associated with a different domain of the multiple relational domains, and wherein for each data cell of the at least one data cell, one depth-wise data value of the data cell associated with one domain is different from at least one other depth-wise data value of the data cell associated with another domain of the multiple relational domains; and
wherein the three-dimensional data structure further comprises at least one cell of the array of data cells having a depth of zero, meaning that the at least one data cell of zero depth is invariable for the multiple relational domains of the operating environment, and wherein the at least one data cell of zero depth contains an actual valid data value which is common to the multiple relational domains.
8. The article of manufacture of claim 7, further comprising retrieving data from the three-dimensional data structure, the retrieving comprising:
identifying a domain for which data is to be read;
selecting a column of the three-dimensional data structure from which data is to be read;
determining, for the selected column, whether the selected column has a cell depth greater than zero;
indexing into the three-dimensional data structure to a cell depth associated with the identified domain to read the data value for that domain, in response to the determining indicating the selected column has a cell depth greater than zero.
9. The article of manufacture of claim 7, wherein storing data for multiple domains further comprises creating an additional domain in the three-dimensional data structure by increasing cell depth of the at least one data cell of the array of data cells.
10. The article of manufacture of claim 9, wherein creating the additional domain comprises:
selecting a column of the three-dimensional data structure;
determining, for the selected column, whether the selected column has a data cell with a cell depth greater than zero;
increasing cell depth for the three-dimensional data structure within the selected column, in response to the determining indicating that the selected column has a depth greater than zero.
11. The article of manufacture of claim 9, further comprises creating a row for the additional domain.
12. The article of manufacture of claim 11, wherein creating the row comprises:
allocating space in the three-dimensional data structure for an additional row in the multiple columns; and
populating the additional row in the multiple columns with data.
13. The article of manufacture of claim 12, wherein creating the row further comprises:
initially determining whether the additional row already exists in the three-dimensional data structure;
performing the allocating and populating, in response to the determining indicating that the row does not already exist in the three-dimensional data structure.
14. The article of manufacture of claim 11, further comprising writing data to the additional row in the three-dimensional data structure for the additional domain.
15. The article of manufacture of claim 7, wherein each domain comprises a cluster of one or more nodes, and said data comprises configuration information for at least one node of the one or more nodes of the cluster.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of exploiting a subsea hydrocarbon reserve, comprising the steps of drilling a first well (4) from a floating drilling vessel (2), establishing a production riser (10) for transferring production fluid from the first well (4) to the drilling vessel or production fluid reception means (18) closely associated with the vessel, and extracting production fluid from the first well (4) while drilling one or more further wells (20) from the drilling vessel (2), and characterised by the steps of:
(i) processing the production fluid with processing means (24) installed on the drilling vessel (2);
(ii) subsequently installing the processing means (24) on the seabed; and
(iii) carrying out subsea processing of production fluid from the wells (4,4,20) by using the processing means (24).
2. A method as claimed in claim 1, wherein the processing means (24) is in the form of a module for installation as part of a seabed processing system.
3. A method as claimed in claim 1, wherein the processing means (24) separates the production fluid into different components.
4. A method as claimed in claim 1, wherein the production riser (10) is sufficiently flexible to permit local excursions of the drilling vessel (2) while it is drilling a said further well (20).
5. A method as claimed in claim 1, wherein the production riser (10) is of sufficient flexibility and length to permit the drilling vessel (2) to move between appropriate locations for drilling plural further wells (20) in order that output from two or more wells (4,4) can be exploited while well drilling is still in progress.
6. A method as claimed in claim 5, including the step of establishing at least one further well (4) and transferring production fluid from the first well (4) and the at least one further well (4) to the drilling vessel (2) or the production fluid reception means (18) closely associated with the vessel while drilling at least one additional well (20).
7. A method as claimed in claim 6, including conveying the production fluid from the drilling vessel (2) to an off-loading buoy (12) for onward conveyance.
8. A method as claimed in claim 7, wherein said production fluid reception means comprises a floating storage unit (18), and the method includes storing production fluid for a period of time in the buoy (12) while the floating storage unit (18) is removed for replacement by another floating storage unit.
9. A method as claimed in claim 1, including conveying the production fluid from the drilling vessel (2) to a pipeline leading to a remote location via an off-loading buoy (12).
10. A method as claimed in claim 7, wherein production fluid is conveyed from the drilling vessel (2) to the buoy (12) by means of an off-loading hose (16) extending from the drilling vessel (2) to the buoy (12).
11. A method as claimed in claim 10, wherein fluid is conveyed from a said further well (4) by an additional production riser (10) to the drilling vessel (2) or production fluid reception means (18).
12. A method as claimed in claim 11, wherein fluid is conveyed from a said further well (4) by interconnecting said further well (4) with at least one other well (4) so that the combined production flow from a number of wells (4,4) is conveyed via a common production riser (10).
13. A method as claimed in claim 1, wherein fluid is conveyed from a said further well (4) by installing a manifold to which the further well or wells isare attached and the combined production flow is conveyed to the drilling vessel (2) or production fluid reception means (18) via the production riser (10).

1-21. (canceled)
22. A tracking system comprising:
an internal device configured for moving in an internal tract of the body, the internal device comprising an acoustic receiver and an acoustic transmitter,
an external apparatus comprising an acoustic transmitter and a plurality of acoustic receivers,
an external controller for directing transmission of incident acoustic signals by the transmitter of the external apparatus and for monitoring detection of acoustic responses by the receivers,
an internal controller for monitoring detection of said incident signals by the receiver of the internal device and for directing transmission of said acoustic responses by the transmitter of the internal device, and
a data processor for determining time-of-flight data for the acoustic signals, and for generating location data for the internal device according to said time-of-flight data.
23. The tracking system as claimed in claim 22, wherein the internal device controller directs transmission of the response after a pre-set delay from detection of the transmission, whereby the response is a simulated echo.
24. The tracking system as claimed in claim 22, wherein the internal device is a capsule configured for movement in an internal tract.
25. The tracking system as claimed in claim 22, wherein the external apparatus transmitter comprises a piezoelectric crystal.
26. The tracking system as claimed in claim 22, wherein the internal device transmitter and receiver comprise a surface acoustic wave transducer performing both transmitter and receiver functions.
27. The tracking system as claimed in claim 22, wherein the internal device transmitter generates the response signal with a pulse train of frequency different to that of a pulse train of said incident signal.
28. The tracking system as claimed in claim 22, wherein the controllers ignore signals received within a time period after a first signal of a measuring point in order to eliminate reflected signals.
29. The tracking system as claimed in claim 28, wherein the controllers change state to a sleep mode within said time period.
30. The tracking system as claimed in claim 22, wherein the processor determines differences between times-of-flight between the internal device and the receivers and processes said data to perform the tracking computations.
31. The tracking system as claimed in claim 22, wherein the external apparatus comprises a belt supporting the receivers at locations chosen to minimise interference in paths between the internal device and the receivers when the belt is worn around the patient’s torso.
32. The tracking system as claimed in claim 22, whereby the belt is configured to be worn and the transmitters and the receivers operate in a non-invasive manner whereby the tracking system operates in a procedure which is ambulatory.
33. The tracking system as claimed in claim 31, wherein the receivers are located on the belt so that patient bone interference in the path is minimised when the belt is worn around the patient’s torso.
34. The tracking system as claimed in claim 22, wherein the data processor computes internal device location by re-computing a length variable at time intervals in a successive accumulation method.
35. The tracking system as claimed in claim 34, wherein the variable is initialised at a reference position in a reference volume and is re-computed only while the location is with in said reference volume.
36. The tracking system as claimed in claim 34, wherein the variable is initialised at a reference position in a reference volume and is re-computed only while the location is with in said reference volume wherein the reference volume is cylindrical.
37. The tracking system as claimed in claim 22, wherein the data processor compensates for organ densities in the paths between the internal device and the external apparatus receivers.
paths between the internal device and the external apparatus receivers.
38. The tracking system as claimed in claim 22, wherein retrograde peristalsis is accommodated by the processor.
39. The tracking system as claimed in claim 22, wherein the internal device comprises a capsule configured for movement in an internal tract, and the capsule comprises a sensor for internal investigation.
40. The tracking system as claimed in claim 39, wherein the capsule comprises a pressure sensor for measuring internal tract pressure.
41. The tracking system as claimed in claim 22, wherein the internal device comprises a casing which facilitates acoustic transmission and reception compatible with human organs.
42. The tracking system as claimed in claim 39, wherein the internal device comprises a casing which operates as an RF transmitter for a sensor.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A nonvolatile semiconductor memory device comprising:
a memory cell array comprising memory cell units being arranged in an array form, the memory cell units each comprising a plurality of memory cells, a first select gate transistor and a second select gate transistor, the plurality of memory cells being connected in series, the plurality of memory cells being connected between a source of the first select gate transistor and a drain of the second select gate transistor;
a first source line located along a first direction in the memory cell array, the first source line being connected to a source of the second select gate transistor, the first source line being consisted of a first conductive layer;
a word line located along the first direction, a gate electrode of one of the plurality of memory cells being connected to the word line, the word line being consisted of a second conductive layer;
a bit line located along a second direction perpendicular to the first direction, the bit line being connected to a drain of the first select gate transistor, the bit line being consisted of a third conductive layer; and
wherein the first conductive layer is located above the second conductive layer and the first conductive layer is located below the third conductive layer.
2. The nonvolatile semiconductor memory device according to claim 1, wherein the source of the second select gate transistor is connected to the first source line through a first interconnection layer.
3. The nonvolatile semiconductor memory device according to claim 1, wherein a sheet resistance of the first conductive layer is higher than a sheet resistance of the third conductive layer.
4. The nonvolatile semiconductor memory device according to claim 1, wherein a sheet resistance of the first conductive layer is lower than a sheet resistance of the second conductive layer.
5. The nonvolatile semiconductor memory device according to claim 1, further comprising:
a first bit line;
a first word line;
a first memory cell unit connected to both the first bit line and the first word line;
a second memory cell unit connected to the first bit line, the second memory cell unit being not connected to the first word line;
a third memory cell unit connected to the first word line, the third memory cell unit being not connected to the first bit line,
wherein the source of the second select gate transistor included in the first memory cell unit, the source of the second select gate transistor included in the second memory cell unit, and the source of the second select gate transistor included in the third memory cell unit are connected to the same first source line in the memory cell array.
6. The nonvolatile semiconductor memory device according to claim 1, further comprising:
a second source line located along the second direction in the memory cell array, the second source line being consisted of a conductive layer located above the first conductive layer;
wherein the second source line is connected to the first source line in the memory cell array.
7. The nonvolatile semiconductor memory device according to claim 6, wherein the second source line is consisted of the third conductive layer.
8. The nonvolatile semiconductor memory device according to claim 6, wherein the second source line is consisted of a conductive layer located above the third conductive layer.
9. The nonvolatile semiconductor memory device according to claim 6, wherein a sheet resistance of the first conductive layer is higher than a sheet resistance of a conductive layer of which the second source line is consisted.
10. The nonvolatile semiconductor memory device according to claim 6, wherein a sheet resistance of the third conductive layer is higher than a sheet resistance of a conductive layer of which the second source line is consisted.
11. The nonvolatile semiconductor memory device according to claim 6, wherein there are a plurality of the second source lines in the memory cell array, and each of the plurality of the second source lines is connected to a plurality of the first source lines in the memory cell array.
12. The nonvolatile semiconductor memory device according to claim 6, wherein the second source line and the first source line are connected to each other in a shunt area.
13. The nonvolatile semiconductor memory device according to claim 6, wherein there are a plurality of the first source lines in the memory cell array, and each of the plurality of the first source lines is connected to a plurality of the second source lines in the memory cell array.
14. The nonvolatile semiconductor memory device according to claim 1, further comprising:
a first memory cell unit connected to the first source line; and
a first word line connected to the first memory cell unit,
wherein the first source line is located over the first word line.
15. The nonvolatile semiconductor memory device according to claim 14, wherein the first word line is closest to the second select gate transistor included in the first memory cell unit.
16. The nonvolatile semiconductor memory device according to claim 1, wherein a width of the first source line is larger than a width of the word line.
17. The nonvolatile semiconductor memory device according to claim 1, further comprising:
a first memory cell unit connected to the first source line;
a first select gate line which is provided along the first direction, a gate electrode of the first select gate transistor being connected to the first select gate line; and
a second select gate line which is provided along the first direction, a gate electrode of the second select gate transistor being connected to the second select gate line,
wherein the first source line is located over the second select gate line connected to the first memory cell unit.
18. The nonvolatile semiconductor memory device according to claim 1, further comprising:
a first select gate line which is provided along the first direction, a gate electrode of the first select gate transistor being connected to the first select gate line; and
a second select gate line which is provided along the first direction, a gate electrode of the second select gate transistor being connected to the second select gate line,
wherein a width of the first source line is larger than both a width of the first select gate line and a width of the second select gate line.
19. The nonvolatile semiconductor memory device according to claim 1, further comprising:
a first select gate line which is provided along the first direction, a gate electrode of the first select gate transistor being connected to the first select gate line;
a second select gate line which is provided along the first direction, a gate electrode of the second select gate transistor being connected to the second select gate line; and
a first select gate bypass line which is provided along the first direction in the memory cell array, the first select gate bypass line being connected to the first select gate line, the first select gate bypass line being located above both the first select gate line and the word line, the first select gate bypass line being consisted of the first conductive layer.
20. The nonvolatile semiconductor memory device according to claim 19, wherein a width of the first select gate bypass line is larger than both a width of the first select gate line and a width of the word line in the memory cell array, and a width of the first source line is larger than the width of the first select gate bypass line in an area other than a shunt area in the memory cell array; and
wherein the first select gate bypass line is located over the word line, and the first select gate bypass line is closer to the first select gate line than the first source line in the memory cell array.
21. The nonvolatile semiconductor memory device according to claim 19, wherein a sheet resistance of the first conductive layer is lower than a sheet resistance of the second conductive layer.
22. The nonvolatile semiconductor memory device according to claim 19, further comprising:
a second select gate bypass line which is provided along the first direction in the memory cell array, the second select gate bypass line being connected to the second select gate line, the second select gate bypass line being located above any of the first select gate line, the second select gate line and the word line, the second select gate bypass line being consisted of the first conductive layer,
wherein a width of the second select gate bypass line is larger than both a width of the second select gate line and a width of the word line in the memory cell array, and a width of the first source line is larger than the width of the second select gate bypass line in an area other than a shunt area in the memory cell array; and
wherein the second select gate bypass line is located over the word line, and the second select gate bypass line is closer to the first select gate line than the first source line in the memory cell array.
23. A nonvolatile semiconductor memory device comprising:
a memory cell array comprising memory cell units being arranged in an array form, the memory cell units each comprising a plurality of memory cells, a first select gate transistor and a second select gate transistor, the plurality of memory cells being connected in series, the plurality of memory cells being connected between a source of the first select gate transistor and a drain of the second select gate transistor;
a source line connected to a source of the second select gate transistor;
a first source line which is at least a portion of the source line, the first source line located along a first direction in the memory cell array, the first source line being consisted of a first conductive layer;
a word line located along the first direction, a gate electrode of one of the plurality of memory cells being connected to the word line, the word line being consisted of a second conductive layer;
a bit line located along a second direction perpendicular to the first direction, the bit line being connected to a drain of the first select gate transistor, the bit line being consisted of a third conductive layer; and
wherein the first conductive layer is located above the second conductive layer and the first conductive layer is located below the third conductive layer.
24. The nonvolatile semiconductor memory device according to claim 23, wherein the source of the second select gate transistor is connected to the first source line through a first interconnection layer.
25. The nonvolatile semiconductor memory device according to claim 23, wherein a sheet resistance of the first conductive layer is higher than a sheet resistance of the third conductive layer.
26. The nonvolatile semiconductor memory device according to claim 23, wherein a sheet resistance of the first conductive layer is lower than a sheet resistance of the second conductive layer.
27. The nonvolatile semiconductor memory device according to claim 23, further comprising:
a first bit line;
a first word line;
a first memory cell unit connected to both the first bit line and the first word line;
a second memory cell unit connected to the first bit line, the second memory cell unit being not connected to the first word line;
a third memory cell unit connected to the first word line, the third memory cell unit being not connected to the first bit line,
wherein the source of the second select gate transistor included in the first memory cell unit, the source of the second select gate transistor included in the second memory cell unit, and the source of the second select gate transistor included in the third memory cell unit are connected to the same first source line in the memory cell array.
28. The nonvolatile semiconductor memory device according to claim 23, further comprising:
a second source line which is at least a portion of the source line, the second source line located along the second direction in the memory cell array, the second source line being consisted of a conductive layer located above the first conductive layer;
wherein the second source line is connected to the first source line in the memory cell array.
29. The nonvolatile semiconductor memory device according to claim 28, wherein the second source line is consisted of the third conductive layer.
30. The nonvolatile semiconductor memory device according to claim 28, wherein the second source line is consisted of a conductive layer located above the third conductive layer.
31. The nonvolatile semiconductor memory device according to claim 28, wherein a sheet resistance of the first conductive layer is higher than a sheet resistance of a conductive layer of which the second source line is consisted.
32. The nonvolatile semiconductor memory device according to claim 28, wherein a sheet resistance of the third conductive layer is higher than a sheet resistance of a conductive layer of which the second source line is consisted.
33. The nonvolatile semiconductor memory device according to claim 28, wherein the second source line and the first source line are connected to each other in a shunt area.
34. The nonvolatile semiconductor memory device according to claim 28, wherein there are a plurality of the second source lines in the memory cell array, and each of the plurality of the second source lines is connected to a plurality of the first source lines in the memory cell array.
35. The nonvolatile semiconductor memory device according to claim 28, wherein there are a plurality of the first source lines in the memory cell array, and each of the plurality of the first source lines is connected to a plurality of the second source lines in the memory cell array.
36. The nonvolatile semiconductor memory device according to claim 23, further comprising:
a first memory cell unit connected to the first source line; and
a first word line connected to the first memory cell unit,
wherein the first source line is located over the first word line.
37. The nonvolatile semiconductor memory device according to claim 36, wherein the first word line is closest to the second select gate transistor included in the first memory cell unit.
38. The nonvolatile semiconductor memory device according to claim 23, wherein a width of the first source line is larger than a width of the word line.
39. The nonvolatile semiconductor memory device according to claim 23, further comprising:
a first memory cell unit connected to the first source line;
a first select gate line which is provided along the first direction, a gate electrode of the first select gate transistor being connected to the first select gate line; and
a second select gate line which is provided along the first direction, a gate electrode of the second select gate transistor being connected to the second select gate line,
wherein the first source line is located over the second select gate line connected to the first memory cell unit.
40. The nonvolatile semiconductor memory device according to claim 23, further comprising:
a first select gate line which is provided along the first direction, a gate electrode of the first select gate transistor being connected to the first select gate line; and
a second select gate line which is provided along the first direction, a gate electrode of the second select gate transistor being connected to the second select gate line,
wherein a width of the first source line is larger than both a width of the first select gate line and a width of the second select gate line.
41. The nonvolatile semiconductor memory device according to claim 23, further comprising:
a first select gate line which is provided along the first direction, a gate electrode of the first select gate transistor being connected to the first select gate line;
a second select gate line which is provided along the first direction, a gate electrode of the second select gate transistor being connected to the second select gate line; and
a first select gate bypass line which is provided along the first direction in the memory cell array, the first select gate bypass line being connected to the first select gate line, the first select gate bypass line being located above both the first select gate line and the word line, the first select gate bypass line being consisted of the first conductive layer.
42. The nonvolatile semiconductor memory device according to claim 41, wherein a width of the first select gate bypass line is larger than both a width of the first select gate line and a width of the word line in the memory cell array, and a width of the first source line is larger than the width of the first select gate bypass line in an area other than a shunt area in the memory cell array; and
wherein the first select gate bypass line is located over the word line, and the first select gate bypass line is closer to the first select gate line than the first source line in the memory cell array.
43. The nonvolatile semiconductor memory device according to claim 41, wherein a sheet resistance of the first conductive layer is lower than a sheet resistance of the second conductive layer.
44. The nonvolatile semiconductor memory device according to claim 41, further comprising:
a second select gate bypass line which is provided along the first direction in the memory cell array, the second select gate bypass line being connected to the second select gate line, the second select gate bypass line being located above any of the first select gate line, the second select gate line and the word line, the second select gate bypass line being consisted of the first conductive layer,
wherein a width of the second select gate bypass line is larger than both a width of the second select gate line and a width of the word line in the memory cell array, and a width of the first source line is larger than the width of the second select gate bypass line in an area other than a shunt area in the memory cell array; and
wherein the second select gate bypass line is located over the word line, and the second select gate bypass line is closer to the first select gate line than the first source line in the memory cell array.