All The Claims

1. Circuitry for handling a digital signal, said circuitry comprising a high voltage input for receiving a high voltage level and a low voltage input for receiving a low voltage level, said circuitry comprising:
a plurality of devices, said plurality of devices being designed to operate optimally when powered in a native voltage domain, wherein when said low voltage level is equal to a low native voltage level, a high native voltage level is lower than said high voltage level;
a further input for receiving said high native voltage level;
at least some of said plurality of devices of said circuitry being arranged in two sets, each set having at least one device, a first set being arranged in an upper voltage domain having an intermediate low reference voltage level as a low voltage level and said high voltage level as a high voltage level and a second set being arranged in a lower voltage domain having said high native voltage level as a high voltage level and said low voltage level as a low voltage level; wherein
said intermediate low reference voltage level comprises a voltage level generated by subtracting said high native voltage level from said high voltage level, such that said devices of said first and said second set operate at or close to an optimal operating voltage difference.
2. Circuitry according to claim 1, said circuitry further comprising:
a voltage level generator configured to generate said intermediate low reference voltage level, said voltage level generator receiving said high voltage level and said high native voltage level and comprising voltage difference generation means for generating a voltage level equal to the voltage difference between said received high voltage level and said received high native voltage level and outputting said voltage difference as said intermediate low reference voltage level.
3. Input output circuitry comprising circuitry according to claim 1, and a data input for receiving an input digital data signal having an input high voltage level that is lower than said high voltage level and an input low voltage level at said low voltage level and a data output for outputting a digital data signal having said high voltage level and said low voltage level; wherein
said first set of devices comprises a first voltage level shifter powered between said high voltage level and said intermediate low reference voltage level and configured to shift said voltage level of said received input digital data signal from said input high voltage level to said high voltage level and said input low voltage level to said intermediate low reference voltage level; and
said input output circuitry comprises a first switching device configured to connect or isolate said high voltage level and an output, said first switching device being controlled by said signal output by said first voltage level shifter;
said second set of devices comprises a second voltage level shifter powered between said native high voltage level and said low voltage level and configured to shift said high voltage level of said received input digital data signal to said high native voltage level; and
said input output circuitry comprises a second switching device configured to connect or isolate said low voltage level and said output, said second switching devices being controlled by said signal output by said second voltage level shifter.
4. Input output circuitry according to claim 3, wherein said first voltage level shifter comprises a pre-driver powered between said high voltage level and said intermediate low reference voltage level and said second voltage level shifter comprises a pre-driver powered between said high native voltage level and said low voltage level.
5. Input output circuitry according to claim 3, wherein said first switching device comprises a PMOS transistor arranged in series with a further at least one PMOS transistor, said further at least one PMOS transistor being configured to receive said intermediate low reference voltage at its gate.
6. Input output circuitry according to claim 5, wherein said second switching device comprises a NMOS transistors arranged in series with a further at least one NMOS transistor, said further at least one NMOS transistor being configured to receive said high native voltage level at its gate.
7. An integrated circuit comprising:
a plurality of components including at least one core for generating a data signal;
a plurality of voltage rails configured to transmit voltage levels to said plurality of components, said plurality of voltage rails comprising:
a first voltage rail comprising a high voltage rail for transmitting a high voltage level;
a second voltage rail comprising a low voltage rail for transmitting a low voltage level;
a third voltage rail for transmitting an intermediate voltage level that is lower than said high voltage level, said intermediate voltage level being a high voltage level for powering said processor core;

an input output cell for receiving said data signal from said core and for converting a high voltage level of said data signal to a higher voltage level, said input output cell comprising input output circuitry according to claim 3.
8. An integrated circuit according to claim 7, said input output cell further comprising:
a voltage level generator for generating said intermediate low reference voltage level, said voltage level generator receiving said high voltage level and said high native voltage level and comprising voltage difference generation means for generating a voltage level equal to the voltage difference between said received high voltage level and said received high native voltage level and outputting said voltage difference as said intermediate low reference voltage level.
9. An integrated circuit according to claim 8, said integrated circuit further comprising:
a fourth voltage rail for receiving said intermediate low reference voltage level from said voltage level generator of said input output cell and for transmitting said intermediate low reference voltage; said integrated circuit further comprising
a further input output cell comprising circuitry according to claim 3, said further input output cell receiving said intermediate low reference voltage from said fourth voltage rail.
10. A means for handling a digital signal, said means comprising a high voltage input means for receiving a high voltage level and a low voltage input means for receiving a low voltage level, said means for handling data comprising:
a plurality of devices, said plurality of devices being designed to operate optimally powered between a native voltage difference, wherein when said low voltage level is equal to a low native voltage level, a high native voltage level is lower than said high voltage level;
a further input means for receiving said high native voltage level;
a voltage level generator means for generating an intermediate low reference voltage level, said voltage level generator means receiving said high voltage level and said high native voltage level and comprising voltage difference generation means for generating a voltage level equal to the voltage difference between said received high voltage level and said received high native voltage level and outputting said voltage difference as said intermediate low reference voltage level; and
a data input means for receiving an input digital data signal having an input high voltage level that is lower than said high voltage level and an input low voltage level at said low voltage level and a data output means for outputting a digital data signal having said high voltage level and said low voltage level; wherein
at least some of said plurality of devices of said circuitry are arranged in two sets, each set having at least one device, a first set being powered between said high voltage level and said intermediate low reference voltage level and a second set being powered between said high native voltage level and said low voltage level such that said devices of said first and said second set operate at or close to an optimal operating voltage difference.
11. A method for handling a digital signal, using circuitry powered in a high voltage domain between a high voltage level and a low voltage level, said circuitry comprising a plurality of devices, said plurality of devices being designed to operate optimally powered between a native voltage difference, wherein when said low voltage level is equal to a low native voltage level, a high native voltage level is lower than said high voltage level;
said method comprising:
receiving said high voltage level of said high voltage domain;
receiving said high native voltage level;
receiving said low voltage level;
generating an intermediate low reference voltage level by subtracting said high native voltage level from said high voltage level of said high voltage domain;
arranging at least some of said plurality of devices of said circuitry in two sets, each set having at least one device, a first set being arranged to receive said intermediate low reference voltage level as a low voltage level signal and said high voltage level as a high voltage level signal and a second set being arranged to receive said high native voltage level as a high voltage level signal and said low voltage level as a low voltage level signal.
12. A method according to claim 11 further comprising:
receiving an input digital data signal having an input high voltage level that is lower than said high voltage level and an input low voltage level at said low voltage level; and
generating and outputting a digital data signal in said high voltage domain having said high voltage level and said low voltage level; wherein
said step of generating and outputting said digital data signal in said high voltage domain comprises:
level shifting said received input digital data signal using said first set of devices from said input high voltage level to said high voltage level and said input low voltage level to said intermediate low reference voltage level; and
controlling a first switching device using said level shifted input digital data signal to connect or isolate said high voltage level to an output to output a high voltage level in response to said digital input data signal having said input high voltage level; and
level shifting said received input digital data signal using said second set of devices from said input high voltage level to said native high voltage level; and
controlling a second switching device using said level shifted input digital data signal to connect or isolate said low voltage level to an output to output a low voltage level in response to said digital input data signal having said input low voltage level.
The claims below are in addition to those above.
All refrences to claims which appear below refer to the numbering after this setence.

1. A method of forming electronic component packages comprising:
placing a plurality of first electronic components in an array arranged to correspond with locations of second electronic components formed on a wafer, each of said first electronic components including first bond pads, and each of said second electronic components including second bond pads;
encapsulating said array in a mold material to form a panel of said first electronic components, wherein said first bond pads are concealed by at least one of said wafer and a portion of said panel;
bonding a bottom side of said wafer to an outer surface of said panel to form a stacked wafer structure of said first and second electronic components;
following said bonding operation, removing a material section from said at least one of said wafer and said portion of said panel of said first electronic components to expose said first bond pads;
forming electrical interconnects between said first and second bond pads; and
dicing said stacked wafer structure to produce said electronic component packages.
2. A method as claimed in claim 1 wherein said wafer is a first wafer, and said method comprises dicing a second wafer, said second wafer including a plurality of said first electronic components, said dicing operation producing said first electronic components for placement in said array.
3. A method of forming electronic component packages comprising:
placing a plurality of first electronic components in an array arranged to correspond with locations of second electronic components formed on a first wafer;
encapsulating said array in a mold material to form a panel of said first electronic components;
bonding a bottom side of said wafer to an outer surface of said panel to form a stacked wafer structure of said first and second electronic components; and
dicing said stacked wafer structure to produce said electronic component packages, wherein said method further comprises:
dicing a second wafer, said second wafer including a plurality of said first electronic components, and wherein said second wafer comprises a wafer structure that includes said first electronic components arranged in pairs in said wafer structure, each of said first electronic components having first bond pads, wherein said first bond pads of a first one of said first electronic components are adjacent to said first bond pads of a second one of said second electronic components in each of said pairs of said first electronic components, and said dicing said second wafer comprises producing said first electronic components in the form of said pairs of said first electronic components for placement in said array.
4. A method as claimed in claim 2 wherein:
said second wafer comprises a sensor wafer structure that includes a sensor wafer and a cap wafer, wherein each of said first electronic components includes a sensor die having a sensor located on said sensor wafer, a first inner surface of said cap wafer is coupled to a second inner surface of said sensor wafer, a first one of said cap wafer and said sensor wafer includes a substrate portion with said first bond pads being located on a corresponding one of said first and second inner surfaces, and a second one of said cap wafer and said sensor wafer conceals said substrate portion; and
said dicing said second wafer includes dicing said sensor wafer structure to produce singulated ones of said sensor dies for placement in said array.
5. A method as claimed in claim 4 wherein sensor wafer structure further includes seal members extending between said sensor wafer and said cap wafer, at least a portion of said seal members being positioned between said first bond pads and saw lines of said sensor wafer structure, said seal members shielding said first bond pads from contaminants when said sensor wafer structure is diced along said saw lines.
6. A method as claimed in claim 1 wherein a second surface area of each of said second electronic components is greater than a first surface area of each of said first electronic components, and said placing operation comprises distributing said first electronic components in said array to align said first electronic components with said second electronic components.
7. A method as claimed in claim 1 wherein said wafer includes bump pads formed on a top side, and said method further comprises forming conductive elements on said bump pads prior to said dicing operation.
8. (canceled)
9. A method as claimed in claim 1 wherein:
a second wafer comprises a sensor wafer structure that includes a sensor wafer and a cap wafer, wherein each of said first electronic components includes a sensor die having a sensor located on said sensor wafer, a first inner surface of said cap wafer is coupled to a second inner surface of said sensor wafer, a first one of said cap wafer and said sensor wafer includes a substrate portion having said first bond pads formed on a corresponding one of said first and second inner surfaces, and a second one of said cap wafer and said sensor wafer conceals said substrate portion; and
said removing operation comprises removing first material from said wafer of said stacked wafer structure and removing second material coincident with said first material from said second one of said sensor wafer and said cap wafer to expose said substrate portion having said first bond pads.
10. A method as claimed in claim 1 wherein said electrical interconnects are formed before said dicing operation.
11. A method as claimed in claim 1 further comprising:
applying a packaging material over said top side of said wafer to encapsulate said second electronic components and said electrical interconnects; and
performing said dicing operation following said applying operation.
12. A method as claimed in claim 1 wherein said panel exhibits a first thickness that is greater than a second thickness of said first electronic components, and said method further comprises:
thinning a back side of said panel to reduce said first thickness to approximately said second thickness; and
performing said dicing operation following said thinning operation.
13-15. (canceled)
16. A method of forming sensor packages comprising:
dicing a sensor wafer to produce sensor elements, said sensor wafer including a plurality of sensor dies, each of said sensor elements including at least one of said sensor dies and first bond pads;
placing said sensor elements in an array arranged to correspond with locations of controller dies in a controller wafer, said controller wafer having a top side and a bottom side opposing said top side, said top side including said controller dies, each of said controller dies including second bond pads, a first surface area of each of said controller dies being greater than a second surface area of each of said sensor dies, and said placing operation includes distributing said sensor elements in said array to align said sensor dies with said controller dies;
encapsulating said array in a mold material to form a panel of said sensor elements, wherein said first bond pads are concealed by at least one of said controller wafer and a portion of said panel;
bonding said bottom side of said controller wafer to an outer surface of said panel to form a stacked wafer structure of said controller dies and said sensor elements;
following said bonding operation, removing a material section from said at least one of said controller wafer and said portion of said panel of said stacked wafer structure to expose said first bond pads;
forming electrical interconnects between said first and second bond pads; and
dicing said stacked wafer structure to produce said sensor packages.
17. A method as claimed in claim 16 wherein:
said sensor wafer comprises a sensor wafer structure that includes said sensor dies arranged in pairs in said sensor wafer structure, wherein said first bond pads of a first sensor die are adjacent to said first bond pads of a second sensor die in each of said pairs of said sensor dies; and
said dicing said sensor wafer comprises producing said sensor elements in the form of said pairs of said sensor dies for placement in said array.
18. A method as claimed in claim 16 wherein:
said sensor wafer comprises a sensor wafer structure that includes said sensor wafer and a cap wafer, a first inner surface of said cap wafer is coupled to a second inner surface of said sensor wafer, a first one of said cap wafer and said sensor wafer includes a substrate portion with said first bond pads being formed on a corresponding one of said first and second inner surfaces, and a second one of said cap wafer and said sensor wafer conceals said substrate portion, and seal members extend between said sensor wafer and said cap wafer, at least a portion of said seal members being positioned between said first bond pads and saw lines of said sensor wafer structure; and
said dicing said sensor wafer includes dicing said sensor wafer structure to produce said sensor elements in the form of singulated ones of said sensor dies for placement in said array, said seal members shielding said first bond pads from contaminants when said sensor wafer structure is diced along said saw lines.
19. (canceled)
20. A method as claimed in claim 16 wherein said removing operation comprises removing first material from said controller wafer of said stacked wafer structure and removing second material coincident with said first material from said second one of said sensor wafer and said cap wafer to expose said substrate portion having said first bond pads.
21. A method of forming electronic component packages comprising:
dicing a first wafer to produce first electronic components, said first wafer including a plurality of said first electronic components, each of said first electronic components including first bond pads;
placing said first electronic components in an array arranged to correspond with locations of second electronic components formed on a second wafer, each of said second electronic components including second bond pads;
encapsulating said array in a mold material to form a panel of said first electronic components;
bonding a bottom side of said second wafer to an outer surface of said panel to form a stacked wafer structure of said first and second electronic components, said first bond pads being concealed by at least one of said wafer and a portion of said panel;
following said bonding operation, removing a material section from said at least one of said wafer and said portion of said panel of said first electronic components to expose said first bond pads;
forming electrical interconnects between said first and second bond pads; and
dicing said stacked wafer structure to produce said electronic component packages.
22. A method as claimed in claim 21 wherein:
said first wafer comprises a sensor wafer structure that includes a sensor wafer and a cap wafer, wherein each of said first electronic components includes a sensor die having a sensor located on said sensor wafer, a first inner surface of said cap wafer is coupled to a second inner surface of said sensor wafer, a first one of said cap wafer and said sensor wafer includes a substrate portion having said first bond pads formed on a corresponding one of said first and second inner surfaces, and a second one of said cap wafer and said sensor wafer conceals said substrate portion; and
said removing operation comprises removing first material from said sensor wafer of said stacked wafer structure and removing second material coincident with said first material from said second one of said sensor wafer and said cap wafer to expose said substrate portion having said first bond pads.
23. A method as claimed in claim 21 wherein said forming said electrical interconnects is performed prior to said dicing operation, and said method further comprises:
applying a packaging material over said top side of said second wafer to encapsulate said second electronic components and said electrical interconnects; and
performing said dicing operation following said applying operation.

What is claimed is:

1. A method for forming a spacer in a semiconductor device having a trench for formation of a gate electrode, the device comprising a pad oxide formed adjacent the trench, and a pad nitride on top of the pad oxide, the method comprising:
depositing a first conductive material onto a gate oxide layer formed within the trench and atop the pad nitride;
depositing a second conductive material atop the first conductive material;
planarizing the first and second conductive material to a level coplanar with the pad nitride;
removing the pad nitride;
etching the first conductive material to a predetermined depth within the trench to form a divot; and
forming an integrated spacer within the divot.
2. The method as in claim 1 wherein the trench is formed within a silicon substrate.
3. The method as in claim 1 wherein the first conductive material is comprised of polysilicon.
4. The method as in claim 1 wherein the first conductive material comprises polysilicon-germanium.
5. The method as in claim 1 wherein the conductive material has a thickness of about 200 to about 1000 angstroms.
6. The method as in claim 1 wherein the step of depositing the first and second conductive material and liner layer comprises chemical vapor deposition.
7. The method as in claim 1 wherein the step of planarizing the pad nitride comprises chemical mechanical polishing.
8. The method as in claim 1 wherein the step of planarizing the pad nitride comprises reactive ion etching.
9. The method as in claim 1 wherein the step of etching the first conductive material is accomplished by a process chosen from the group consisting of reactive ion etching, wet etch, and plasma etch.
10. The method as in claim 1 wherein the etching back of the liner layer is accomplished by a process chosen from the group consisting of reactive ion etching, wet etch, and plasma etch.
11. The method as in claim 10 wherein the wet etch utilizes NH4OH.
12. The method as in claim 1 wherein the conductive material is about 600 angstroms thick.
13. The method as in claim 1 wherein the first conductive material comprises tungsten or a tungsten alloy.
14. The method as in claim 1 wherein the step of etching the first conductive material to a predetermined depth within the trench is performed after the step of planarizing the first and second conductive material and before the step of removing the pad nitride.
15. The method as in claim 1 wherein the semiconductor device is a Dynamic Random Memory Access device.
16. A method of forming a memory device having a vertical array transistor whereby a gate electrode is formed within a trench, the transistor comprising a pad oxide formed adjacent the trench, and having a pad nitride on top of the pad oxide, the method comprising:
depositing a first conductive material onto a gate oxide layer formed within the trench and atop the pad nitride;
depositing a second conductive material onto the first conductive material to form the gate electrode, the second conductive material having selective etch properties relative the first conductive material;
planarizing the first and second conductive material to a level coplanar with a top surface of the pad nitride;
removing the pad nitride;
etching the first conductive material to a predetermined depth within the trench to form a divot; and
depositing a liner layer within the divot, whereby a spacer is formed within the divot;
depositing a second liner layer;
depositing an array top oxide on top of the second liner layer;
planarizing the array top oxide to a level coplanar to the top of the second liner layer;
removing the second liner layer;
forming gate conductors atop the polysilicon gate electrode and the array top oxide; and
forming sidewall spacers at each side of the gate conductors.
17. The method of claim 16 wherein the memory device is Dynamic Random Access Memory device.
18. The method of claim 16 wherein the first conductive material comprises polysilicon and the second conductive material comprises polysilicon-germanium.
19. The method of claim 16 wherein the second liner layer is comprised of silicon nitride.
20. A vertical gate transistor comprising:
a trench formed in a top surface of a substrate;
a gate oxide formed along a sidewall of the trench;
a gate electrode formed within the trench and extending above the top surface of the substrate, the gate electrode comprising a first material being relatively non-reactive to a first etchant substantially surrounded by a second material being relatively reactive to said first etchant;
a divot formed within the second material extending a predetermined distance below the top surface of the substrate;
a liner layer formed within the divot;
at least one doped region adjacent the trench at the top surface of the substrate;
a first conductor contacting the gate electrode; and
a second conductor contacting the at least one doped region.
21. The vertical gate transistor of claim 20 wherein the first material is polysilicon and the second material is polysilicon-germanium.
22. The vertical gate transistor of claim 20 wherein the liner layer is silicon nitride.
23. The vertical gate transistor of claim 20 wherein the first etchant is NH4OH.
24. The vertical gate transistor of claim 20 further comprising a second doped region adjacent the trench and being formed below the top surface of the substrate.
25. The vertical gate transistor of claim 20 further comprising a trench capacitor formed within the trench.
26. The vertical gate transistor of claim 20 wherein the predetermined distance is within the range of 200 to 800 angstroms.

The claims below are in addition to those above.
All refrences to claims which appear below refer to the numbering after this setence.

1. A ligator apparatus comprising in combination:
A. a ligator barrel assembly (i) having a ligating barrel end opposite a cord penetrating barrel end and (ii) including:
a. an outer barrel mounted about at least a portion of an inner barrel, the inner barrel being rotatable with respect to the outer barrel; and
b. a cord channel penetrating the outer periphery of the outer barrel and having a first cord passage and second cord passage extending from the outer periphery of the outer barrel to the inner periphery of the outer barrel; and

B. an activating cord penetrating the cord-penetrating barrel end, the first cord passage, and the second cord passage and having an inner barrel activation end abutting the inner barrel.
2. The ligator of claim 1 wherein the outer barrel has interior threads matably engaging exterior threads on the inner barrel.
3. The ligator of claim 1 wherein the cord channel includes an angled section at a 20-90 degree angle to the axis of the inner barrel.
4. The ligator of claim 2 wherein the cord channel includes an angled section at a 20-90 degree angle to the axis of the inner barrel, the angled section terminating in the second cord passage.
5. The ligator of claim 3 wherein the cord channel includes an arcuate section.
6. The ligator of claim 4 wherein the cord channel is includes an arcuate section having angled section.
7. The ligator of claim 1 wherein the angled section is at a 60-90 degree angle to the axis of the inner barrel.
8. The ligator of claim 2 wherein the angled section is at a 60-90 degree angle to the axis of the inner barrel.
9. The ligator of claim 7 wherein the cord channel includes an arcuate section.
10. The ligator of claim 8 wherein the cord channel includes an arcuate section having angled section.
11. The ligator of claim 1 wherein the inner barrel activation end of the activating cord wraps around the outer periphery of the inner barrel.
12. The ligator of claim 2 wherein the inner barrel activation end of the activating cord wraps around the outer periphery of the inner barrel.
13. The ligator of claim 8 wherein the inner barrel activation end of the activating cord wraps around the outer periphery of the inner barrel.
14. The ligator of claim 10 wherein the inner barrel activation end of the activating cord wraps around the outer periphery of the inner barrel.
15. The ligator of claim 1 wherein the inner barrel includes a viewing passage through the ligator.
16. The ligator of claim 2 wherein the inner barrel includes a viewing passage through the ligator.
17. The ligator of claim 8 wherein the inner barrel includes a viewing passage through the ligator.
18. The ligator of claim 10 wherein the inner barrel includes a viewing passage through the ligator.
19. The ligator of claim 11 wherein the inner barrel includes a viewing passage through the ligator.
20. The ligator of claim 14 wherein the inner barrel includes a viewing passage through the ligator.
21. A ligator apparatus comprising in combination:
A. a ligator barrel assembly (i) having a ligating barrel end opposite a cord penetrating barrel end and (ii) including:
a. an outer barrel mounted about at least a portion of an inner barrel providing a ligator viewing passage through the ligator barrel assembly;
b. a cord channel penetrating the outer periphery of the outer barrel and having a first cord passage and second cord passage extending from the outer periphery of the outer barrel to the inner periphery of the outer barrel; and

B. an activating cord penetrating the cord-penetrating barrel end, the first cord passage, and the second cord passage and having an inner barrel activation end abutting the inner barrel.
22. The ligator apparatus of claim 21 wherein the ligator barrel assembly includes an endoscope mounting section providing a mounting section viewing passage through the endoscope mounting section.
23. The ligator apparatus of claim 21 wherein the inner barrel is laterally movably mounted in the ligator barrel assembly with respect to the outer barrel.
24. The ligator apparatus of claim 22 wherein the inner barrel is laterally movably mounted in the ligator barrel assembly with respect to the outer barrel.
25. The ligator apparatus of claim 21 wherein the inner barrel is rotatably mounted in the ligator barrel assembly with respect to the outer barrel.
26. The ligator apparatus of claim 22 wherein the inner barrel is rotatably mounted in the ligator barrel assembly with respect to the outer barrel.
27. The ligator apparatus of claim 24 wherein the inner barrel is rotatably mounted in the ligator barrel assembly with respect to the outer barrel.
28. The ligator apparatus of claim 26 further comprising: (C) an activating cord pulling assembly mountable at a fixed distance from the ligator barrel assembly.
29. The ligator apparatus of claim 26 further comprising: (C) an activating cord pulling assembly having an endoscope mount mountable adjacent a working channel access passage in an endoscope.
30. The ligator apparatus of claim 29 where in the activating cord pulling assembly includes a rotatable cord wrap rod.
31. The ligator apparatus of claim 30 wherein the activating cord pulling assembly includes a cord wrap indexing handle connected to the rotatable cord wrap rod.
32. (canceled)
33. (canceled)
34. (canceled)
35. (canceled)
36. (canceled)
37. (canceled)
38. (canceled)
39. (canceled)
40. (canceled)
41. (canceled)
42. (canceled)
43. (canceled)
44. (canceled)