All The Claims

1. A device, comprising:
a functional circuit, said functional circuit comprising:
a logic circuit; and
a variable delay; and
a latch;
wherein
said variable delay is coupled to receive input from a data path and coupled to provide output to the latch; and
said latch is coupled to receive input from the variable delay and provide input to said logic circuit; and
a control circuit, said control circuit comprising:
a register;
a repeater;
a comparator; and
a command detector;
wherein
said register is coupled to receive input from a first external source and coupled to provide output to said repeater and said comparator;
said repeater is coupled to receive input from said register and said command detector and to provide output to a second external source;
said command detector is coupled to receive input from said second external source and to provide output to said repeater and said comparator; and
said comparator is coupled to receive input from said latch of said functional circuit and said register and provide output to control said variable delay.
2. The device of claim 1, wherein said device is a memory device and said logic circuit comprise a memory array.
3. The device of claim 2, wherein said memory array comprises a plurality of dynamic random access memory (DRAM) cells.
4. The device of claim 1, wherein said first external source is a register coupled to said device and said second external source is a bus coupled to said device.
5. The device of claim 4, wherein said device is a memory controller and said logic circuit comprise a control logic for controlling a memory device.
6. The device of claim 5, wherein said control logic is capable of operating a dynamic random access memory (DRAM) device.
7. A system, comprising:
a bus;
a pattern register;
a first device, said first device coupled to said bus and said first device comprising:
a first functional circuit, said first functional circuit comprising:
a first logic circuit; and
a first variable delay; and
a first latch;
wherein
said first variable delay is coupled to receive input from a data path and coupled to provide output to the first latch; and
said first latch is coupled to receive input from the first variable delay and provide input to said first logic circuit; and
a first control circuit, said first control circuit comprising:
a first register;
a first repeater;
a first comparator; and
a first command detector;
wherein
said first register is coupled to receive input from said pattern register and coupled to provide output to said repeater and said first comparator;
said first repeater is coupled to receive input from said first register and said command detector and to provide output to said bus;
said first command detector is coupled to receive input from said bus and to provide output to said repeater and said first comparator; and
said first comparator is coupled to receive input from said latch of said first functional circuit and said first register and provide output to control said first variable delay; and
a second device, said second device coupled to the bus and said second device comprising:
a second functional circuit, said second functional circuit comprising:
a second logic circuit; and
a second variable delay; and
a second latch;
wherein
said second variable delay is coupled to receive input from the data path and coupled to provide output to the second latch; and
said second latch is coupled to receive input from the second variable delay and provide input to said second logic circuit; and
a second control circuit, said second control circuit comprising:
a second register;
a second repeater;
a second comparator; and
a second command detector;
wherein
said second register is coupled to receive input from said bus and coupled to provide output to said repeater and said second comparator;
said second repeater is coupled to receive input from said second register and said command detector and to provide output to said bus;
said second command detector is coupled to receive input from said bus and to provide output to said repeater and said second comparator; and
said second comparator is coupled to receive input from said latch of said second functional circuit and said second register and provide output to control said second variable delay.
8. The system of claim 7, wherein said first device is a memory controller.
9. The system of claim 7, wherein said second device is a memory device.

The claims below are in addition to those above.
All refrences to claims which appear below refer to the numbering after this setence.

1. An integrated circuit, comprising:
a first macro circuit block having an input;
a second macro circuit block having an input;
a first configurable delay circuit having an output connected to the input of the first macro circuit block;
a second configurable delay circuit having an output connected to the input of the second macro circuit block; and
a signal distribution network having an output connected to an input of the first configurable delay circuit;
wherein the first configurable delay circuit and the second configurable delay circuit have a same footprint, but have different delay characteristics.
2. The integrated circuit of claim 1, wherein the output of the signal distribution network is connected to an input of the second configurable delay circuit.
3. The integrated circuit of claim 1, wherein the signal distribution network is a clock signal distribution network, and wherein the input of the first macro circuit block is a clock input.
4. The integrated circuit of claim 1, wherein the signal distribution network is a data signal distribution network, and wherein the input of the first macro circuit block is a data input.
5. The integrated circuit of claim 1, wherein the first and second configurable delay circuits each comprise a chain of buffers, wherein a number of buffers in the chain of buffers is the same in the first and second configurable delay circuits.
6. The integrated circuit of claim 5, wherein a total delay for a given one of the first and second configurable delay circuits is based on a number of buffers in the chain of buffers, which are serially connected between an input and output of the given configurable delay circuit.
7. The integrated circuit of claim 1, further comprising a third configurable delay circuit having footprint that is different than the footprints of the first and second configurable delay circuits.
8. The integrated circuit of claim 7, further comprising a third macro circuit block having an input connected to an output of the third configurable delay circuit.
9. The integrated circuit of claim 7, wherein an output of the third configurable delay circuit is connected to an input of the second configurable delay circuit.
10. The integrated circuit of claim 9, wherein an input of the third configurable delay circuit is connected to an output of the signal distribution network.
11. A chip package comprising the integrated circuit of claim 1.
12. An integrated circuit, comprising:
a macro circuit block having an input;
a signal distribution network having an output; and
a chain of configurable delay circuits serially connected between the input of the macro circuit block and the output of the signal distribution network;
wherein the plurality of configurable delay circuits comprises at least a first configurable delay circuit and a second configurable delay circuit, which have a same footprint, but have different delay characteristics.
13. The integrated circuit of claim 12, wherein the signal distribution network is a clock signal distribution network, and wherein the input of the macro circuit block is a clock input.
14. The integrated circuit of claim 12, wherein the signal distribution network is a data signal distribution network, and wherein the input of the macro circuit block is a data input.
15. The integrated circuit of claim 12, wherein the first and second configurable delay circuits each comprise a chain of buffers, wherein a number of buffers in the chain of buffers is the same in the first and second configurable delay circuits.
16. The integrated circuit of claim 15, wherein a total delay for a given one of the first and second configurable delay circuits is based on a number of buffers in the chain of buffers, which are serially connected between an input and output of the given configurable delay circuit.
17. The integrated circuit of claim 12, wherein the chain of configurable delay circuits further comprises a third configurable delay circuit having footprint that is different than the footprints of the first and second configurable delay circuits.
18. A chip package comprising the integrated circuit of claim 12.
19. An integrated circuit, comprising:
a macro circuit block having an input;
a signal distribution network having an output; and
a chain of configurable delay circuits serially connected between the input of the macro circuit block and the output of the signal distribution network;
wherein the plurality of configurable delay circuits comprises at least a first configurable delay circuit and a second configurable delay circuit, which have different footprints, but have the same delay characteristics.
20. A chip package comprising the integrated circuit of claim 19.

1. A component frame assembly for a patient lift device, the component frame assembly comprising:
first and second opposed frame plates, and at least one plate connector connecting the plates, the plates and plate connector being sized, shaped and positioned such that the plates are separated by an interior component space and so as to define an opening to the interior component space between an edge of the first plate and an edge of the second plate, each plate having an inner side facing the interior component space and an opposite outer side;
a force transmitter coupled to the plates and positioned in the interior component space;
a force applicator mounted to the outer side of one of the first and second frame plates.
2. A component frame assembly as claimed in claimed 1, wherein the force transmitter comprises a gear assembly.
3. A component frame assembly as claimed in claim 1, where the force applicator comprises a motor.
4. A component fame assembly as claimed in claim 3, the assembly further comprising a controller mounted to the outer side of one of the first and second frame plates.
5. A component frame assembly as claimed in claim 4, the assembly further comprising a power source, the power source being coupled to the plates and positioned on an outer side of one of the plates.
6. A component frame assembly as claimed in claim 1, wherein the opening extends over at least fifty percent of the perimeter of the plates.
7. A component frame assembly as claimed in claim 1, wherein the assembly includes a patient connector retraction and extension device positioned in the interior component space adjacent said opening.
8. A component frame assembly as claimed in claim 7, wherein the patient connector retraction and extension device comprises a spool for retracting and extending a patient connector.
9. A component frame assembly as claimed in claim 4, wherein the assembly further comprises at least one limit switch to limit operation of the motor, the limit switch being positioned on an outer side of one of the plates.
10. A component frame assembly as claimed in claim 4, wherein the assembly further comprises at least one current-controlling fuse, the fuse being positioned on an outer side of one of the plates.
11. A component frame assembly as claimed in claim 5, wherein the power source comprises a pair of batteries.
12. A component frame assembly as claimed in claim 4, wherein the controller comprises a circuit board that includes control circuitry.
13. A component frame assembly as claimed in claim 12, wherein the assembly further comprises a power source coupled to the plates and positioned on an outer side of one of the plates, and wherein the circuit board is positioned between one of the plates and the power source.
14. A component frame assembly as claimed in claim 4, wherein the motor is positioned on an outer side of the first plate.
15. A component frame assembly as claimed in claim 14, wherein the assembly further comprises at least one limit switch to limit operation of the motor, the limit switch being positioned on the outer side of the first plate.
16. A component frame assembly as claimed in claim 15, wherein the controller is positioned on an outer side of the second plate.
17. A component frame assembly as claimed in claim 16, wherein the assembly further comprises a power source, the power source being coupled to the plates and positioned toward an outer side of the second plate.

The claims below are in addition to those above.
All refrences to claims which appear below refer to the numbering after this setence.

1. A rolled-up inductor structure for a radiofrequency integrated circuit (RFIC), the rolled-up structure comprising:
a multilayer sheet in a rolled configuration comprising multiple turns about a longitudinal axis, the multilayer sheet comprising a conductive pattern layer on a strain-relieved layer,
wherein the conductive pattern layer comprises:
at least one conductive strip having a length extending in a rolling direction, the at least one conductive strip thereby wrapping around the longitudinal axis in the rolled configuration; and
two conductive feed lines connected to the at least one conductive strip for passage of electrical current therethrough,

wherein the conductive strip is an inductor cell of the rolled-up inductor structure.
2. The rolled-up inductor structure of claim 1, further comprising a plurality of the conductive strips disposed along the direction of the longitudinal axis and connected in series by connecting lines.
3. The rolled-up structure of claim 2 comprising n of the conductive strips, n being an even number from 2 to 20, and further comprising n\u22121 of the connecting lines.
4. The rolled-up inductor structure of claim 2, wherein a first connecting line connects a base of a first conductive strip to a top of a second conductive strip, and a second connecting line connects a base of the second inductor cell to a top of a third inductor cell, such that the electrical current passes through adjacent conductive strips in the same direction.
5. The rolled-up inductor structure of claim 4, wherein each of the connecting lines defines an angle \u03b8 with respect to a side of one of the conductive strips, the angle \u03b8 ranging from about 30\xb0 to about 60\xb0.
6. The rolled-up inductor structure of claim 2, wherein a first connecting line connects a base of a first conductive strip to a base of a second conductive strip, and a second connecting line connects a top of the second conductive strip to a top of a third conductive strip, such that electrical current passes through adjacent conductive strips in opposing directions.
7. The rolled-up inductor structure of claim 6, wherein the connecting lines are aligned substantially parallel to the longitudinal axis.
8. The rolled-up inductor structure of claim 2, wherein the two conductive feed lines are connected to first and second ends of the plurality of the conductive strips.
9. The rolled-up inductor structure of claim 1, wherein the two conductive feed lines extend away from the at least one conductive strip in a rolling direction.
10. The rolled-up inductor structure of claim 1, wherein the strain-relieved layer comprises two layers, and wherein, in an unrolled configuration of the multilayer sheet, a top layer of the two layers is in tension and a bottom layer of the two layers is in compression.
11. The rolled-up inductor structure of claim 10, wherein each of the two layers comprises non-stoichiometric silicon nitride.
12. The rolled-up inductor structure of claim 1, wherein the conductive pattern layer comprises one or more materials selected from the group consisting of carbon, silver, gold, aluminum, copper, molybdenum, tungsten, zinc, palladium, platinum, and nickel.
13. The rolled-up inductor structure of claim 1, wherein the conductive pattern layer comprises a thickness of from about 10 nm to about 100 nm.
14. The rolled-up inductor structure of claim 1, wherein a ratio of the thickness of the conductive pattern layer to an inner diameter of the rolled configuration of the multilayer sheet is at least about 0.005.
15. The rolled-up inductor structure of claim 1, wherein the rolled configuration of the multilayer sheet comprises at least about 10 turns.
16. The rolled-up inductor structure of claim 1, wherein the length of the at least one conductive strip is aligned substantially parallel to a rolling direction of the rolled configuration.
17. The rolled-up inductor structure of claim 1, wherein the rolled configuration of the multilayer sheet comprises an on-wafer footprint of about 5000 \u03bcm2 or less.
18. A device comprising:
a plurality of the rolled-up inductor structures of claim 1 on a substrate, wherein the rolled-up inductor structures are components of a radiofrequency integrated circuit (RFIC), the substrate comprising a semiconductor.
19. A method of making a rolled-up inductor structure for a radiofrequency integrated circuit (RFIC), the method comprising:
forming a sacrificial layer on a substrate;
forming a strained layer on the sacrificial layer, the strained layer comprising an upper portion under tensile stress and a lower portion under compressive stress, the strained layer being held on the substrate by the sacrificial layer;
forming a conductive pattern layer on the strained layer, the conductive pattern layer comprising at least one conductive strip having a length extending in a rolling direction;
initiating removal of the sacrificial layer from the substrate, thereby releasing an end of the strained layer, and
continuing the removal of the sacrificial layer, thereby allowing the strained layer to move away from the substrate and roll up to relieve strain in the strained layer, the conductive pattern layer adhering to the strained layer during the roll-up, thereby forming a rolled-up inductor structure,
wherein, after the roll-up, the at least one conductive strip wraps around the longitudinal axis, the at least one conductive strip being an inductor cell of the rolled-up inductor structure.
20. The method of claim 19, further comprising transferring the rolled-up structure to a different substrate.