All The Claims

What is claimed is:

1. A cavity-preventing type reactor, comprising:
an introduction part having a reactant inlet through which a reactant is introduced into the reactor,
a reaction part; and
at least one cavity-preventing structure, wherein
the introduction part and the reaction part are adjacent and separated by a wall having a reactant flow path through which the introduction part is in communication with the reaction part, and
the at least one cavity-preventing structure having at least one reactant flow path and disposed in the flow path of the reactant between the reaction part and the reactant inlet of the introduction part to allow the reactant to flow from the introduction part to the reaction part while preventing a cavity from extending into the reaction part during rotation of the reactor.
2. The cavity-preventing type reactor as claimed in claim 1, wherein the shape of the cavity-preventing structure is cylindrical or plate-like.
3. The cavity-preventing type reactor as claimed in claim 1, wherein the reactor is made of glass, quartz, ceramics or plastics.
4. The cavity-preventing type reactor as claimed in claim 1, wherein a radius of the reactor is between approximately 1 and 10 cm and a length of the reactor is 100 cm or less.
5. A method for fabricating a preform for a plastic optical fiber using a cavity-preventing type reactor having a reactant introduction part, a reaction part, and at least one cavity-preventing structure interposed therebetween, comprising:
filling the reaction part and the introduction part of the reactor with a reactant; and
polymerizing the reactant in the reaction part under the rotation of the reactor.
6. The method for fabricating a preform for a plastic optical fiber as claimed in claim 5, further comprising charging and pressurizing unoccupied space in the introduction part with inert gas.
7. The method for fabricating a preform for a plastic optical fiber as claimed in claim 6, further comprising pressurizing both an inner part and an outer part of the cavity-preventing type reactor.
8. The method for fabricating a preform for a plastic optical fiber as claimed in claim 5, wherein the reactor is rotated at a constant or varying speed.
9. The method for fabricating a preform for a plastic optical fiber as claimed in claim 8, wherein the varying speed of rotation of the reactor follows a simple repetition of rotating and stopping, a sinusoidal function or a function whose period, phase andor amplitude is varied.
10. The method for fabricating a preform for a plastic optical fiber as claimed in claim 5, wherein the reactant is a monomer mixture comprised of at least two kinds of monomers having a different refractive index relative to each other, a polymerization initiator and a chain transfer agent.
11. The method for fabricating a preform for a plastic optical fiber as claimed in claim 10, wherein the at least two kinds of monomers are two monomers wherein one monomer has a higher refractive index and a lower density than the other monomer, and the monomer mixture comprised of the two kinds of monomers, a polymerization initiator and a chain transfer agent are charged into the introduction part and the reaction part of the reactor.
12. The method for fabricating a preform for a plastic optical fiber as claimed in claim 10, wherein a monomer mixture filling the introduction part has a refractive index that is higher than that of a monomer filling the reaction part.
13. The method for fabricating a preform for a plastic optical fiber as claimed in claim 10, wherein crushed fragements of a polymer having a lower refractive index than that of the monomer mixture is swelled or dissolved in the monomer mixture before the monomer mixture is introduced to the reaction part.
14. The method for fabricating a preform for a plastic optical fiber as claimed in claim 10, wherein a prepolymer having a lower refractive index than that of the monomer mixture is dissolved in the monomer mixture or partially filled with the reaction part before the monomer mixture is introduced to the reaction part.
15. The method for fabricating a preform for a plastic optical fiber as claimed in claim 10, wherein the at least two kinds of monomers are selected from the group consisting of methylmethacrylate, benzylmethacrylate, phenylmethacrylate, 1-methylcyclohexylmethacrylate, cyclohexylmethacrylate, chlorobenzylmethacrylate, 1-phenylethylmethacrylate, 1,2-diphenylethylmethacrylate, diphenylmethylmethacrylate, furfurylmethacrylate, 1-phenylcyclohexylmethacrylate, pentachlorophenylmethacrylate, pentabromophenylmethacrylate, styrene, TFEMA(2,2,2-trifluoroethylmethacrylate), PFPMA (2,2,3,3,3-pentafluoropropylmethacrylate), HFIPMA(1,1,1,3,3,3-hexafluoroisopropylmethacrylate) and HFBMA(2,2,3,3,4,4,4-heptafluorobuthylmethacrylate).
16. The method for fabricating a preform for a plastic optical fiber as claimed in claim 13, wherein the polymer is a homopolymer of a monomer selected from the group consisting of methylmethacrylate, benzylmethacrylate, phenylmethacrylate, 1-methylcyclohexylmethacrylate, cyclohexylmethacrylate, chlorobenzylmethacrylate, 1-phenylethylmethacrylate, 1,2-diphenylethylmethacrylate, diphenylmethylmethacrylate, furfurylmethacrylate, 1-phenylcyclohexylmethacrylate, pentachlorophenylmethacrylate, pentabromophenylmethacrylate, styrene, TFEMA(2,2,2-trifluoroethylmethacrylate), PFPMA(2,2,3,3,3-pentafluoropropylmethacrylate), HFIPMA(1,1,1,3,3,3-hexafluoroisopropylmethacrylate) and HFBMA(2,2,3,3,4,4,4-heptafluorobuthylmethacrylate).
17. The method for fabricating a preform for a plastic optical fiber as claimed in claim 13, wherein the polymer is a copolymer selected from the group consisting of methylmethacrylate(MMA)-benzylmethacrylate(BMA) copolymer, styrene-acrylonitrile copolymer (SAN), MMA-TFEMA (2,2,2-trifluoroethylmethacrylate) copolymer, MMA-PFPMA(2,2,3,3,3-pentafluoropropylmethacrylate) copolymer, MMA-HFIPMA(1,1,1,3,3,3-hexafluoroisopropylmethacrylate) copolymer, MMA-HFBMA(2,2,3,3,4,4,4-heptafluorobuthylmethacrylate) copolymer, TFEMA-PFPMA copolymer, TFEMA-HFIPMA copolymer, styrene-methylmethacrylate copolymer and TFEMA-HFBMA copolymer.
18. The method for fabricating a preform for a plastic optical fiber as claimed in claim 14, wherein the prepolymer is made from one or more monomers selected from the group consisting of methylmethacrylate, benzylmethacrylate, phenylmethacrylate, 1-methylcyclohexylmethacrylate, cyclohexylmethacrylate, chlorobenzylmethacrylate, 1-phenylethylmethacrylate, 1,2-diphenylethylmethacrylate, diphenylmethylmethacrylate, furfurylmethacrylate, 1-phenylcyclohexylmethacrylate, pentachlorophenylmethacrylate, pentabromophenylmethacrylate, styrene, TFEMA(2,2,2-trifluoroethylmethacrylate), PFPMA(2,2,3,3,3-pentafluoropropylmethacrylate), HFIPMA(1,1,1,3,3,3-hexafluoroisopropylmethacrylate) and HFBMA(2,2,3,3,4,4,4-heptafluorobuthylmethacrylate).
19. The method for fabricating a preform for a plastic optical fiber as claimed in claim 14, wherein the prepolymer has a viscosity of from 500 to 500,000 cps at 25 C.
20. The method for fabricating a preform for a plastic optical fiber as claimed in claim 5, wherein the reactant of the reaction part is polymerized through thermal polymerization or UV photopolymerization.
21. The method for fabricating a preform for a plastic optical fiber as claimed in claim 5, wherein the reactor is rotated while set to an angle of from 90 to 90 degrees relative to the horizontal surface.

The claims below are in addition to those above.
All refrences to claims which appear below refer to the numbering after this setence.

1. A method, comprising:
switching a power switch of a power supply regulator at an operating frequency (f) during operation of the power supply regulator; and
controlling a current through the power switch to keep the current through the power switch below a peak current limit threshold (Ip) during operation of the power supply regulator, wherein a maximum deliverable power value of a power supply to be regulated by the power supply regulator is controlled by trimming of the power supply such that the operating frequency (f) and the peak current limit threshold (Ip) are substantially dependent upon each other.
2. The method of claim 1 wherein the maximum deliverable power value of the power supply is substantially constant with a maximum deliverable power value of another power supply.
3. The method of claim 1 wherein the trimming of the power supply includes trimming at least one of the operating frequency (f) and the peak current limit threshold(Ip) during manufacture of the power supply such that a product Ipm\xb7fn is substantially constant.
4. The method of claim 3 wherein m is substantially equal to 2 and n is substantially equal to 1.
5. The method of claim 1 wherein the trimming of the power supply comprises trimming a frequency trim circuit coupled to an oscillator and trimming a peak current limit threshold trim circuit coupled to a current limit circuit.
6. The method of claim 5 wherein the operating frequency (f) is an operating frequency of the oscillator that is determined in response to the frequency trim circuit and the peak current limit threshold (Ip) is determined in response to the peak current limit threshold trim circuit.
7. The method of claim 1 wherein the operating frequency (f) is substantially constant during operation under substantially all operating conditions of the power supply regulator.
8. The method of claim 1 wherein the operating frequency (f) is substantially constant during operation under a fixed range of operating conditions of the power supply regulator.
9. The method of claim 1 wherein the power supply is a flyback converter power supply.
10. The method of claim 1 wherein the power supply is buck converter power supply.

1. A battery security device, comprising:
a holder having a containing cavity;
a cover slidably dis-mountable from the holder and having two raised lumps protruding into the containing cavity; and
at least one flexible planar plate disposed between the holder and the cover, being pivotally connected to the holder, and having two elastic arms, each of the elastic arms has a pressed portion and at least one contact portion, wherein the pressed portions project toward the cover, each of the raised lumps of the cover abut against a respective pressed portion, and each contact portion is radially displaced relative to the flexible planar plate into the containing cavity to contact an electrode of a respective battery disposed therein responsive to a force occasioned by a respective raised lump of the cover abutting against the pressed portion of a corresponding elastic arm.
2. The battery security device as claimed in claim 1, wherein the raised lumps and the cover are made integrally in one piece.
3. The battery security device as claimed in claim 1, wherein the raised lumps are rectangular, square, elliptical, round or polygonal.
4. The battery security device as claimed in claim 1, wherein each raised lump includes a push portion, which is capable of applying force on a respective contact portion.
5. The battery security device as claimed in claim 1, wherein the flexible planar plate has two openings punched therethrough, each elastic arm is located in a respective opening and has an end connected to the flexible planar plate.
6. The battery security device as claimed in claim 1, wherein each elastic arm is folded to form the pressed portion.

The claims below are in addition to those above.
All refrences to claims which appear below refer to the numbering after this setence.

1. A semiconductor integrated circuit, comprising:
a sense amplifier which senses and outputs data read out from memory cells connected to word lines and bit lines, the sense amplifier outputting data in accordance with a potential difference between the potential on the bit line and the potential on a reference bit line; and
a read-out control circuit which has a standby state consuming minimum necessary power and a read state reading out the memory cells, and controls read-out of the memory cells;
wherein the read-out control circuit includes:
a bit line switching circuit which switches whether or not to transmit a potential on the bit line to an input terminal of the sense amplifier;
a first switching control circuit which controls the bit line switching circuit to prevent the potential on the bit line from being transmitted to the input terminal of the sense amplifier during a period of the standby state and a predetermined period after the standby state is released; and
a second switching control circuit which controls the bit line switching circuit to prevent the potential on the reference bit line from being transmitted to the corresponding input terminal of the sense amplifier during the period of the standby state and a predetermined period after the standby state is released.
2. The semiconductor integrated circuit according to claim 1,
wherein the first switching control circuit sets the input terminal of the sense amplifier to a predetermined reference voltage level during the period of the standby state and the predetermined period after the standby state is released.
3. The semiconductor integrated circuit according to claim 1,
wherein the first switching control circuit switches whether or not to transmit the potential on the bit line to the corresponding input terminal of the sense amplifier based on a bit line potential control signal on which a logic inverts at a predetermined period after the standby state elapses; and
the second switching control circuit switches whether or not to transmit the potential on the reference bit line to the corresponding input terminal of the sense amplifier based on the bit line potential control signal.
4. The semiconductor integrated circuit according to claim 1,
wherein the read-out control circuit includes:
a bias transistor which sets the bit line to a predetermined potential at the timing of reading out the memory cells; and
a bias control circuit which controls a gate voltage of the bias transistor;
wherein the first and second switching control circuit decide the predetermined period in conformity to a time when the gate voltage of the bias transistor stabilizes after the standby state is released.
5. The semiconductor integrated circuit according to claim 4,
wherein the first and second switching control circuit decide the predetermined period in conformity to a time when fluctuation of the gate voltage of the bias transistor does not exist any more after the standby state is released.
6. The semiconductor integrated circuit according to claim 1,
wherein the bit line switching circuit has a plurality of transistors which switch whether or not to transmit the potential on the bit line to the input terminal of the sense amplifier and are connected to a plurality of bit lines, respectively; and
the first switching control circuit turns off the plurality of transistors during the period of the standby state and the predetermined period after the standby state is released.
7. The semiconductor integrated circuit according to claim 6,
wherein the first switching control circuit turns on one of the plurality of transistors at the predetermined period after the standby state is released.
8. The semiconductor integrated circuit according to claim 1,
wherein the memory cells are memory cells of a flash memory; and
the first switching control circuit is a decoder which decodes a portion of addresses of the flash memory.
9. A microcomputer, comprising:
a cell array having a plurality of memory cells each connected to word lines and bit lines;
a plurality of sense amplifiers which are provided in units of the plurality of bit lines, sense and output data read out from the plurality of memory cells, each the sense amplifier outputting data in accordance with a potential difference between the potential on the bit line and the potential on a reference bit line; and
a read-out control circuit which has a standby state consuming minimum necessary power and a read state reading out the memory cells, and controls read-out of the memory cells;
wherein the read-out control circuit includes:
a bit line switching circuit which switches whether or not to transmit a potential on the bit line to an input terminal of the corresponding sense amplifier;
a first switching control circuit which controls the bit line switching circuit to prevent the potential on the bit line from being transmitted to the input terminal of the corresponding sense amplifier during a period of the standby state and a predetermined period after the standby state is released; and
a second switching control circuit which controls the bit line switching circuit to prevent the potential on the reference bit line from being transmitted to the input terminal of the corresponding sense amplifier during the period of the standby state and the predetermined period after the standby state is released.
10. The microcomputer according to claim 9,
wherein the first switching control circuit sets the input terminal of the sense amplifier to a predetermined reference voltage level during the period of the standby state and the predetermined period after the standby state is released.
11. The microcomputer according to claim 9,
wherein the first switching control circuit switches whether or not to transmit the potential on the bit line to the corresponding input terminal of the sense amplifier based on a bit line potential control signal on which a logic inverts at a predetermined period after the standby state elapses; and
the second switching control circuit switches whether or not to transmit the potential on the reference bit line to the corresponding input terminal of the sense amplifier based on the bit line potential control signal.
12. The microcomputer according to claim 9,
wherein the read-out control circuit includes:
a bias transistor which sets the bit line to a predetermined potential at the timing of reading out the memory cells; and
a bias control circuit which controls a gate voltage of the bias transistor;
wherein the first and second switching control circuit decide the predetermined period in conformity to a time when the gate voltage of the bias transistor stabilizes after the standby state is released.
13. The microcomputer according to claim 12,
wherein the first and second switching control circuit decide the predetermined period in conformity to a time when fluctuation of the gate voltage of the bias transistor does not exist any more after the standby state is released.
14. The microcomputer according to claim 9,
wherein the bit line switching circuit has a plurality of transistors which switch whether or not to transmit the potential on the bit line to the input terminal of the sense amplifier and are connected to a plurality of bit lines, respectively; and
the first switching control circuit turns off the plurality of transistors during the period of the standby state and the predetermined period after the standby state is released.
15. The microcomputer according to claim 14,
wherein the first switching control circuit turns on one of the plurality of transistors at the predetermined period after the standby state is released.
16. The microcomputer according to claim 9,
wherein the memory cells are memory cells of a flash memory; and
the first switching control circuit is a decoder which decodes a portion of addresses of the flash memory.