1. A chip package comprising:
a substrate:
a first chip over the substrate;
a second chip over the substrate; and
a voltage regulator device over the substrate, wherein the voltage regulator device is configured and arranged to accommodate different voltage needs of the first chip and second chip.
2. The chip package of claim 1, wherein the voltage regulator device comprises a semiconductor chip, wherein the semiconductor chip includes:
a silicon substrate;
multiple active devices in or over the silicon substrate, wherein the active devices comprise a switch controller and a voltage feedback device, wherein the switch controller and the voltage feedback device comprise a plurality of MOS devices;
a first dielectric layer over the silicon substrate;
a metallization structure over the first dielectric layer, wherein the metallization structure is connected to the active devices, and wherein the metallization structure comprises a first metal layer and a second metal layer over the first metal layer;
a second dielectric layer between the first and second metal layers;
a passivation layer over the metallization structure and over the first and second dielectric layers, an opening in the passivation layer exposing a pad and a contact pad of the metallization structure; and
an inductor component and a capacitor component connected to the pads through a first solder layer, wherein the inductor component, the capacitor component, the switch controller and the voltage feedback device form the voltage regulator.
3. The chip package of claim 2, wherein the passivation layer comprises a silicon nitride layer having a thickness of more than 0.3 micrometers.
4. The chip package of claim 2, further comprising an under bump metal structure between the pad and the inductor component and the capacitor component, wherein the first solder layer is over the under bump metal structure.
5. The chip package of claim 4, wherein the under bump metal structure comprises a nickel layer.
6. The chip package of claim 4, wherein the under bump metal structure comprises a copper layer.
7. The chip package of claim 1, wherein the second chip is over the first chip.
8. The chip package of claim 1, wherein the substrate comprises a Ball Grid Array (BGA) substrate.
9. A chip package comprising:
a substrate:
a first chip over the substrate;
a second chip over the substrate; and
a voltage converter device over the substrate, wherein the voltage regulator device is configured and arranged to accommodate different voltage needs of the first chip and second chip.
10. The chip package of claim 9, wherein the voltage converter device comprises a semiconductor chip, wherein the semiconductor chip includes:
a silicon substrate;
multiple active devices in or over the silicon substrate, wherein the active devices comprise a switch controller and a voltage feedback device, wherein the switch controller and the voltage feedback device comprise a plurality of MOS devices;
a first dielectric layer over the silicon substrate;
a metallization structure over the first dielectric layer, wherein the metallization structure is connected to the active devices, and wherein the metallization structure comprises a first metal layer and a second metal layer over the first metal layer;
a second dielectric layer between the first and second metal layers;
a passivation layer over the metallization structure and over the first and second dielectric layers, an opening in the passivation layer exposing a pad and a contact pad of the metallization structure; and
an inductor component and a capacitor component connected to the pads through a first solder layer, wherein the inductor component, the capacitor component, the switch controller and the voltage feedback device form an on-chip voltage converter.
11. The chip package of claim 10, wherein the passivation layer comprises a silicon nitride layer having a thickness of more than 0.3 micrometers.
12. The chip package of claim 10, further comprising an under bump metal structure between the pad and the inductor component and the capacitor component, wherein the first solder layer is over the under bump metal structure.
13. The chip package of claim 12, wherein the under bump metal structure comprises a nickel layer.
14. The chip package of claim 12, wherein the under bump metal structure comprises a copper layer.
15. The chip package of claim 9, wherein the second chip is over the first chip.
16. The chip package of claim 9, wherein the substrate comprises a ball grid array (BGA) substrate.
17. A chip package comprising:
a substrate:
a first chip over the substrate;
a second chip over the substrate; and
a power management device over the substrate, wherein the power management device is configured and arranged to accommodate different voltage needs of the first chip and the second chip.
18. The chip package of claim 17, wherein the power management device comprises a semiconductor chip, wherein the semiconductor chip includes:
a silicon substrate;
multiple active devices in or over the silicon substrate, wherein the active devices comprise a switch controller and a voltage feedback device, wherein the switch controller and the voltage feedback device comprise a plurality of MOS devices;
a first dielectric layer over the silicon substrate;
a metallization structure over the first dielectric layer, wherein the metallization structure is connected to the active devices, and wherein the metallization structure comprises a first metal layer and a second metal layer over the first metal layer;
a second dielectric layer between the first and second metal layers;
a passivation layer over the metallization structure and over the first and second dielectric layers, an opening in the passivation layer exposing a pad and a contact pad of the metallization structure; and
an inductor component and a capacitor component connected to the pads through a first solder layer.
19. The chip package of claim 18, wherein the passivation layer comprises a silicon nitride layer having a thickness of more than 0.3 micrometers.
20. The chip package of claim 18, further comprising an under bump metal structure between the pad and the inductor component and the capacitor component, wherein the first solder layer is over the under bump metal structure.
21. The chip package of claim 20, wherein the under bump metal structure comprises a nickel layer.
22. The chip package of claim 20, wherein the under bump metal structure comprises a copper layer.
23. The chip package of claim 17, wherein the second chip is over the first chip.
24. The chip package of claim 17, wherein the substrate comprises a Ball Grid Array (BGA) substrate.
The claims below are in addition to those above.
All refrences to claims which appear below refer to the numbering after this setence.
1. A continuous ink jet printer comprising a fluid system comprising:
an ink tank for holding ink;
a print head;
an ink nozzle disposed in the print head and in fluid communication with the ink tank for ejecting ink droplets;
a gutter disposed in the print head for receiving, through an ink-receiving inlet thereof, ink droplets which are not used for printing;
a gutter flow path starting at the ink-receiving inlet, for ink that has entered the gutter through the ink-receiving inlet, and providing fluid communication to the ink tank;
a makeup tank in vapor communication with the ink tank to allow air to be conveyed from the ink tank to the makeup tank;
a return line in fluid communication between the makeup tank and the print head for conveying air from the makeup tank to the print head and into the gutter flow path; and
a condenser in fluid communication with the makeup tank and the return line, the condenser disposed between the makeup tank and the return line, the condenser adapted to receive exhaust from the makeup tank and condense solvent from the exhaust, the condensed solvent flowing into the makeup tank.
2. The continuous ink jet printer of claim 1 where the return line is connected to the gutter flow path.
3. The continuous ink jet printer of claim 1, further comprising an ink supply line disposed between the ink tank and the ink nozzle.
4. The continuous ink jet printer of claim 1, further comprising a solvent supply line disposed between the ink tank and the print head.
5. The continuous ink jet printer of claim 1 wherein the condenser is a passive condenser.
6. The continuous ink jet printer of claim 1 wherein the condenser is an active condenser.
7. The continuous ink jet printer of claim 1 wherein the condenser is disposed above the makeup tank.
8. The continuous ink jet printer of claim 1 further comprising a heater disposed adjacent the condenser for heating air conveyed from the makeup tank.
9. The continuous ink jet printer of claim 1 further comprising a heater disposed in the return line adjacent the gutter for heating air conveyed to the gutter.
10. The continuous ink jet printer of claim 1 wherein the makeup tank and the ink tank are integrated in a single component.
11. The continuous ink jet printer of claim 10 wherein there is direct vapor communication between the ink tank and the makeup tank.
12. The continuous ink jet printer of claim 10 wherein the single component comprises a wall disposed between the makeup tank and the ink tank with an opening adjacent a top of the component for allowing vapor communication between the makeup tank and the ink tank.
13. The continuous ink jet printer of claim 1 wherein the makeup tank and the ink tank are separate components.
14. The continuous ink jet printer of claim 1 wherein the return line conveys air with evaporated solvent at an amount less than saturation and the air is substantially free of liquid solvent.
15. The continuous ink jet printer of claim 1 further comprising an air intake line to introduce air into the makeup tank andor the ink tank from outside the fluid system.
16. A method of operating a continuous ink jet printer comprising:
conveying ink from an ink tank to an ink nozzle;
ejecting ink droplets from the nozzle;
receiving, through an ink-receiving inlet of a gutter, ink droplets which are not used for printing;
conveying ink that has entered the gutter through the ink-receiving inlet to the ink tank;
conveying air from a makeup tank to the print head;
conveying air from the ink tank to the makeup tank; and
condensing solvent from air from the makeup tank and conveying the condensed solvent to the makeup tank.
17. The method of claim 16 further comprising introducing ambient air into the makeup tank andor the ink tank.
18. The method of claim 16 further comprising removing solvent from the ink tank by condensing solvent into the makeup tank.
19. The continuous ink jet printer of claim 1 wherein the return line is in fluid communication between the makeup tank and the print head for conveying air from the makeup tank to the gutter flow path.
20. The method of claim 16 wherein the printer has a solvent consumption of less than 3.5 mlhr with a volatile organic solvent selected from MEK, acetone, ethanol, and mixtures thereof.