All The Claims

1. Spraying head for the humidification of the intake air of a piston engine, said spraying head comprising at least one nozzle (3) for supplying a liquid humidifying the intake air into the air intake duct or into a space leading to the air intake duct of the engine, characterized in that the spraying head (1) is movable between at least two positions, a first position, in which first position the spraying head is retracted, and a second position, in which second position the spraying head is protruding.
2. Spraying head according to claim 1, characterized in that, in a non-active state, the spraying head is in the retracted first position, while in an active state, in the second position, at least one of the nozzles (3) of the spraying head extends to a position inside the air intake duct relative to the level of the edges of the spraying head holder (2) or andor the interior surface of the air intake duct (5).
3. Spraying head according to claim 1, characterized in that the holder (2) is provided with at least one guide element (13) and the spraying head with at least one guide element mating surface (14) for keeping the spraying head in a desired orientation.
4. Spraying head according to claim 1, characterized in that the spraying head (1), preferably its shank part (7), and the holder (2) are arranged to function as a cylinder-piston combination in which the spraying head, preferably its shank part (7), is provided with a piston part (7) and the holder (2) comprises a cylinder chamber (8), the piston part being movably fitted in it.
5. Spraying head according to claim 1 characterized in that the spraying head arrangement comprises means for moving the spraying head (1) from the protruding position into the retracted position.
6. Spraying head according to claim 1, characterized in that a spring element (10) is arranged between the spraying head (1) and the holder (2) for 8 moving the spraying head from the protruding position to the retracted position.
7. Spraying head according to claim 1, characterized in that the spraying head comprises at least one first channel (11) for conveying a pressure medium to at least one nozzle (3).
8. Spraying head according to claim 1, characterized in that the spraying head comprises at least one second channel (21) for conveying a second pressure medium to at least one nozzle.
9. Spraying head according to claim 1, characterized in that the spraying head (1) comprises at least two nozzles (3).
10. Spraying head according to claim 1, characterized in that the spraying head (1) comprises at least one second channel for conveying a medium to another nozzle.
11. Spraying head according to claim 1, characterized in that the spraying head sprays a liquid mist, especially water mist.
12. Spraying head according to claim 1, characterized in that the spraying head (1) is moved from the first position to the second position by the action of a pressure medium.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. A thermal storage apparatus for using a hydrate thermal storage medium comprising:
a storage tank for storing a cooling medium liquid;
a refrigerating machine, connected with the storage tank via a pipe for cooling the cooling medium liquid, the cooling medium liquid circulating between the storage tank and the refrigerating machine;
a thermal storage body immersed in the cooling medium liquid, wherein the thermal storage medium comprising,
a hermetically sealed container,
an aqueous solution filled in the hermetically sealed container, to generate at least one selected from the group consisting of a primary hydrate and a secondary hydrate, wherein the primary hydrate has smaller hydration number and smaller heat capacity than the secondary hydrate, the secondary hydrate has larger hydration number and larger heat capacity than the primary hydrate,
fine particles to prevent the aqueous solution from super-cooling, the fine particles being contained in the hermetically sealed container.
2. The thermal storage apparatus according to claim 1, further comprising container drive means for changing position of the container and moving the container in the cooling medium liquid to disperse the fine particles in the container.
3. The thermal storage apparatus according to claim 2, wherein the container drive means comprises a fluid mechanism to change position of the container or to move the container by fluidizing the cooling medium liquid in the storage tank.
4. The thermal storage apparatus according to claim 2, wherein the container drive means comprises an air-injection mechanism to change position of the container or to move the container by injecting air into the cooling medium liquid in the storage tank and by ascending air bubbles.
5. The thermal storage apparatus according to claim 2, wherein the container drive means comprises a mechanical drive mechanism for mechanically changing position of the container or moving the container.
6. The thermal storage apparatus according to claim 1, wherein the container of the thermal storage medium floats freely in the cooling medium liquid in the storage tank.
7. The thermal storage apparatus according to claim 1, wherein the container of the thermal storage medium is supported in the storage tank in a free-rotational mode.
8. The thermal storage apparatus according to claim 1, wherein the container of the storage tank provides at least one piece of blade members outside of the container, to promote changing position of the container or moving the container.
9. The thermal storage apparatus according to claim 1, wherein the aqueous solution filled in the hermetically sealed container contains a guest compound, where the generation temperature of at least one selected from the group consisting of the primary hydrate and the secondary hydrate varies in accordance with the concentration of the aqueous solution.
10. The thermal storage apparatus according to claim 1, wherein the fine particles have a diameter size of 100 m or less.
11. The thermal storage apparatus according to claim 1, wherein the fine particles have a diameter size of 10 m or less.
12. The thermal storage apparatus according to claim 1, wherein the fine particles have a diameter size of 100 m or less, and the fine particles in the aqueous solution have a concentration of 0.1 mgl or more.
13. A hydrate thermal storage medium comprising:
an aqueous solution containing a guest compound to generate a hydrate slurry by cooling; and,
a corrosion inhibitor.
14. The hydrate thermal storage medium according to claim 13, wherein the contained corrosion inhibitor is 5,000 wt.ppm or less of concentration.
15. The hydrate thermal storage medium according to claim 13, wherein the guest compound is one selected from the group consisting of a tetra-n-butylammonium salt, a tetra-iso-amylammonium salt, a tetra-iso-butylphosphonium salt, and a tri-iso-amylsulfonium salt.
16. A method for producing a hydrate thermal storage medium comprising the steps of:
(a) preparing an aqueous solution containing a guest compound to generate at least one selected from the group consisting of a primary hydrate and a secondary hydrate, wherein the primary hydrate has smaller hydration number and smaller heat capacity than the secondary hydrate, the secondary hydrate has larger hydration number and larger heat capacity than the primary hydrate; and,
(b) cooling the aqueous solution to produce at least one selected from the group consisting of the primary hydrate and the secondary hydrate.
17. The method according to claim 16, wherein the aqueous solution is cooled at a rate of 6 kcalhr-kg or more.
18. The method according to claim 16, wherein the aqueous solution contains the guest compound at a concentration of from 10 to 26 wt. %.
19. The method according to claim 16, wherein the aqueous solution is cooled to a temperature range of from 5 C. to 8 C.
20. The method according to claim 16, wherein the guest compound is one selected from the group consisting of a tetra-n-butylammonium salt, a tetra-iso-amylammonium salt, a tetra-iso-butylphosphonium salt, or a tri-iso-amylsulfonium salt.
21. A method for producing a hydrate slurry comprising the steps of:
(a) preparing an aqueous solution containing a guest compound by cooling, to generate at least one selected from the group consisting of a primary hydrate and a secondary hydrate, wherein the primary hydrate has smaller hydration number and smaller heat capacity than the secondary hydrate, the secondary hydrate has larger hydration number and larger heat capacity than the primary hydrate,and,
(b) cooling the aqueous solution and contacting nucleus particles as nucleus of the hydrate particles with the aqueous solution to produce the hydrate particles consisting of the primary hydrate and the secondary hydrate.
22. The method according to claim 21, wherein the nucleus particles comprise hydrate particles.
23. The method according to claim 21, wherein the nucleus particles comprise fine particles.
24. The method according to claim 21, wherein the nucleus particles have a diameter size of 300 m or less.
25. The method according to claim 21, wherein the nucleus particles have a diameter size of 100 m or less.
26. The method according to claim 21, wherein the nucleus particles have a diameter size of 10 m or less.
27. The method according to claim 21, wherein the nucleus particles have a diameter size of 10 m or less and the nucleus particles in the aqueous solution have a concentration of 0.1 mgl or more.
28. The method according to claim 21, wherein the nucleus particles comprise fine particles having heavier specific gravity than the specific gravity of the aqueous solution, and wherein the step of contacting the nucleus particles with the aqueous solution comprises dispersing and floating the nucleus particles in the aqueous solution.
29. The method according to claim 21, wherein the step of contacting the nucleus particles with the aqueous solution comprises dispersing and floating the nucleus particles precipitated in the aqueous solution.
30. The method according to claim 21, wherein the specific gravity of the nucleus particles is almost equal with the specific gravity of the aqueous solution, and the nucleus particles are dispersed and floated in the aqueous solution.
31. The method according to claim 21, wherein the step of contacting the nucleus particles with the aqueous solution comprises the step of agitating the aqueous solution containing the nucleus particles.
32. The method according to claim 21, wherein the step of contacting the nucleus particles with the aqueous solution comprises the step of contacting the aqueous solution with members to which surface the nucleus particles adhere.
33. An apparatus for producing hydrate slurry by cooling an aqueous solution containing a guest compound and by generating hydrate particles comprising:
a generation heat exchanger having a heat transfer surface for cooling the aqueous solution and cooling the aqueous solution by contacting the aqueous solution with the heat transfer surface; and,
a nucleus particles supply mechanism for supplying the nucleus particles as nuclei of the hydrate particles to the aqueous solution passing through the generation heat exchanger.
34. The apparatus according to claim 33, wherein the nucleus particles supply mechanism comprises a supply mechanism for supplying the hydrate particles.
35. The apparatus according to claim 33, wherein the nucleus particles supply mechanism comprises a hydrate particle generation mechanism capable of operation independent from the generation heat exchanger.
36. The apparatus according to claim 33, wherein the nucleus particles supply mechanism comprises a storage tank holding a part of the hydrate slurry produced in the generation heat exchanger.
37. The apparatus according to claim 33, wherein the nucleus particles supply mechanism comprises a nucleus particle recovery mechanism for recovering the nucleus particles precipitated in the aqueous solution and for supplying the recovered nucleus particles to the generation heat exchanger.
38. An apparatus for producing a hydrate slurry by cooling an aqueous solution containing a guest compound, to generate a primary hydrate and a secondary hydrate, wherein the primary hydrate has smaller hydration number and smaller heat capacity than the secondary hydrate, the secondary hydrate has larger hydration number and larger heat capacity than the primary hydrate by generating hydrate particles, comprising:
a generation heat exchanger having a heat transfer surface for cooling the aqueous solution and cooling the aqueous solution by the contacting the aqueous solution with the heat transfer surface; and,
at least one part of a surface of members, wherein the surface contacts with the aqueous solution in the generation heat exchanger, and wherein nucleus particles as nuclei of the hydrate particles adhere to the surface.
39. The apparatus according to claim 38, wherein the generation heat exchanger comprises:
a cylindrical heat transfer surface,
a separation blade member rotating, simultaneously with contacting and sliding on the heat transfer surface for separating the hydrate generated on the heat transfer surface, and,
a surface of the separation blade member having a surface adhered by the nucleus particles.
40. An apparatus for producing a hydrate slurry by cooling an aqueous solution containing a guest compound and by generating hydrate particles, comprising:
a generation heat exchanger having a heat transfer surface for cooling the aqueous solution and cooling the aqueous solution by contacting the aqueous solution with the heat transfer surface; and,
an agitation mechanism for dispersing and floating the nucleus particles as nuclei of the hydrate particles in the aqueous solution.
41. A Hydrate thermal storage medium comprising:
an aqueous solution filled in the hermetically sealed container, to generate at least one selected from the group consisting of a primary hydrate and a secondary hydrate, wherein the primary hydrate has smaller hydration number and smaller heat capacity than the secondary hydrate, the secondary hydrate has larger hydration number and larger heat capacity than the primary hydrate.
42. The thermal storage medium according to claim 41, wherein the aqueous solution contains the guest compound, the concentration being from 10% to 26%.
43. The thermal storage medium according to claim 41, wherein the guest compound contained in the aqueous solution is one selected from the group consisting of a tetra-n-butylammonium salt, a tetra-iso-amylammonium salt, a tetra-iso-butylphosphonium salt, and a tri-iso-amylsulfonium salt.
44. A hydrate cold thermal storage transporting medium comprising:
a primary hydrate and a secondary hydrate, wherein the primary hydrate has smaller hydration number and smaller heat capacity than the secondary hydrate, the secondary hydrate has larger hydration number and larger heat capacity than the primary hydrate.
45. The hydrate cold thermal storage transporting medium according to claim 44, wherein the aqueous solution contains the guest compound, the concentration being from 10% to 26%.
46. The hydrate cold thermal storage transporting medium according to claim 44, wherein the guest compound contained in the aqueous solution is one selected from the group consisting of a tetra-n-butylammonium salt, a tetra-iso-amylammonium salt, a tetra-iso-butylphosphonium salt, and a tri-iso-amylsulfonium salt.
47. The hydrate thermal storage medium according to claim 13, wherein the contained corrosion inhibitor is at least one selected from the group consisting of sodium nitrite, sodium sulfite, sodium pyrophosphate, and benzotriazole.
48. The method according to claim 16, the aqueous solution is cooled to generation temperature or less of the secondary hydrate.

What is claimed is:

1. A process for protecting a gas purification system from damage comprising:
a) passing a first impurity-containing gas stream into a data analyzer flow scheme;
b) passing a second reactant-containing gas stream into the analyzer flow scheme;
c) mixing said first impurity-containing gas stream with the second reactant-containing gas stream to form a mixed gas stream;
d) passing said mixed gas stream to a first temperature measuring device to determine its temperature and passing the resulting temperature data to a data analyzer;
e) passing the mixed gas stream from step d) to a catalytic bed to allow the reaction in the mixed gas stream to proceed, and forming a reacted mixed gas stream;
f) passing the reacted mixed stream to a second temperature measuring device to determine its temperature and passing the resulting temperature data to said data analyzer; and
g) controlling the flow of the first impurity-containing gas stream passing to or from the gas purification apparatus based on data received from the data analyzer.
2. The process of claim 1 further comprising passing said first impure gas stream through a flow control device.
3. The process of claim 1 further comprising passing said second reactant-containing gas stream through a flow control device.
4. The process of claim 1 further comprising passing said first impure gas stream through a pressure gauge.
5. The process of claim 1 further comprising passing said second reactant containing gas stream through a pressure gauge.
6. The process of claim 1 wherein said temperature measuring device is a thermocouple.
7. The process of claim 1 wherein said reaction vessel comprises a catalyst bed.
8. The process of claim 1 wherein said catalyst bed is comprised of palladium on a substrate.
9. The process of claim 1 which comprises passing said mixed gas stream to a plurality of temperature measuring devices and catalytic beds in parallel to determine the temperature of the reaction in the catalytic beds.
10. A process for protecting a gas purification system from damage comprising:
a) passing a first impurity-containing gas stream into a data analyzer flow scheme and a gas purification apparatus;
b) passing a second reactant-containing gas stream into the analyzer flow scheme;
c) mixing said first impurity-containing gas stream with the second reactant-containing gas stream to form a mixed gas stream;
d) separating the mixed gas stream into a plurality of split streams;
e) passing one of the split streams to a first temperature measuring device to determine its temperature and passing the resulting temperature to a data analyzer;
f) passing the resulting split stream from step e) to a reaction vessel to purify said resulting split stream;
g) passing the resulting split stream from step f) to a second temperature measuring device to determine its temperature and passing the resulting temperature to the data analyzer;
h) repeating the steps of e) to g) with another split stream through corresponding temperature measuring devices and reaction vessels; and
i) controlling the flow of the first impurity-containing gas stream passing to the gas purification apparatus based on data received from the data analyzer.
11. The process of claim 10 further comprising passing said first impurity-containing gas stream through a flow control device.
12. The process of claim 10 further comprising passing said second reactant-containing gas stream through a flow control device.
13. The process of claim 10 further comprising passing said first impurity-containing gas stream through a pressure gauge.
14. The process of claim 10 further comprising passing said second reactant-containing gas stream through a pressure gauge.
15. The process of claim 10 wherein said temperature measuring device is a thermocouple.
16. The process of claim 10 wherein said reaction vessel comprises a catalyst bed.
17. A system for protecting a gas-purification system from damage comprising:
a) a first impure gas stream;
b) a second reactant containing gas stream;
c) a reactor vessel;
d) a plurality of temperature measuring devices to measure the temperature of said mixture of first impure gas stream and second reactant containing gas streams before and after the gas flow in said reactor vessel;
e. a data analyzer for analyzing the temperature difference of said mixture of first impure gas stream and second reactant containing gas streams before and after the gas flow in said reactor vessel and controlling the flow of said first impure gas stream.
18. The system of claim 17 further comprising a plurality of flow controlling devices to control the flow of the first impure gas stream and second reactant containing gas stream.
19. The system of claim 17 further comprising a plurality of pressure gauges for measuring the flow of said first impure gas stream and second reactant containing gas stream.
20. The system of claim 17 wherein said reactor vessel comprises a catalyst bed for purifying the mixture of gases.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of manufacturing a semiconductor device comprising:
performing an operation test on a plurality of memory cells each accessed based on a row address and a column address;
generating error pattern information and error address information when a first defective memory cell is detected in the operation test;
each time one of a plurality of second defective memory cells different from the first defective memory cell is detected in the operation test, updating the error pattern information based on a relative arrangement relationship between the first and second defective memory cells and updating the error address information based on addresses of at least part of the first and second defective memory cells; and
replacing the first and second defective memory cells with respective redundant memory cells based on the error pattern information and the error address information,
wherein the error pattern information is updated from a first value to a second value if the first and second defective memory cells have either a same row address or a same column address,
wherein the error pattern information is updated from the second value to a third value if two of three defective memory cells consisting of the first defective memory cell and two of the second defective memory cells including a predetermined defective memory cell have a same row address, and two of the three defective memory cells including the predetermined defective memory cell have a same column address, and
wherein the error pattern information is updated from the third value to a fourth value if each of four defective memory cells consisting of the first defective memory cell and three of the second defective memory cells has either one of first and second row addresses and either one of first and second column addresses.
2. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the semiconductor device includes a plurality of semiconductor chips packaged in a same package, and at least one of the semiconductor chips includes the plurality of memory cells.
3. The method of manufacturing a semiconductor device as claimed in claim 2, wherein the error pattern information and the error address information are generated and updated by an analysis circuit that is arranged on another one of the semiconductor chips.
4. A method of manufacturing a semiconductor device comprising:
performing an operation test on a plurality of memory cells each accessed based on a row address and a column address;
generating error pattern information and error address information when a first defective memory cell is detected in the operation test;
each time one of a plurality of second defective memory cells different from the first defective memory cell is detected in the operation test, updating the error pattern information based on a relative arrangement relationship between the first and second defective memory cells and updating the error address information based on addresses of at least part of the first and second defective memory cells; and
replacing the first and second defective memory cells with respective redundant memory cells based on the error pattern information and the error address information,
wherein the error pattern information is updated from a first value to a second value if the first and second defective memory cells have either a same row address or a same column address,
wherein the error pattern information is updated from the second value to a fifth value if three or more defective memory cells consisting of the first defective memory cell and two or more of the second defective memory cells coincide in either one of the row address and the column address, and
wherein the error address information associated with the error pattern information having the fifth value includes the one of the row address and column address of the three or more defective memory cells, a smallest address value of other of the row address and column address of the three or more defective memory cells, and a largest address value of the other of the row address and column address of the three or more defective memory cells.
5. A method of manufacturing a semiconductor device comprising:
performing a first operation test on a plurality of memory devices in a wafer state;
analyzing addresses of defective memory cells detected by the first operation test to identify first defective word lines and first defective bit lines;
replacing the first defective word lines and the first defective bit lines with first redundant word lines and first redundant bit lines in the wafer state, respectively;
dicing the wafer into individual memory chips;
packaging one or more semiconductor chips including at least one of the memory chips;
performing a second operation test on the packaged semiconductor device;
analyzing addresses of defective memory cells detected by the second operation test to identify second defective word lines and second defective bit lines; and
replacing the second defective word lines and the second defective bit lines with second redundant word lines and second redundant bit lines, respectively, wherein
the addresses of the defective memory cells detected by the second operation test are analyzed by an analysis circuit provided in the semiconductor device, and
the analysis circuit updating error pattern information and error address information each time the defective memory cell is detected, the error pattern information indicating a relative arrangement relationship between a plurality of defective memory cells, the error address information indicating the addresses of at least part of the plurality of defective memory cells.
6. The method of manufacturing a semiconductor device as claimed in claim 5, wherein
the analysis circuit sets the error pattern information to a first value and sets the error address information to a value that includes a row address and a column address of the defective memory cell when a first defective memory cell is detected, and
when a second defective memory cell that coincides with the first defective memory cell in either one of the row address and column address is detected, the analysis circuit updates the error pattern information from the first value to a second value and updates the error address information to a value that includes the one of the row address and column address of the first and second defective memory cells, other of the row address and column address of the first defective memory cell, and the other of the row address and column address of the second defective memory cell.
7. The method of manufacturing a semiconductor device as claimed in claim 5, wherein
the memory chips include two or more memory chips and at least one control chip for controlling the memory chips, and
the analysis circuit is arranged in the control chip.
8. The method of manufacturing a semiconductor device as claimed in claim 5, wherein
the memory chip includes a plurality of redundant word lines that are usable at least as the first redundant word line and a plurality of redundant bit lines that are usable at least as the first redundant bit line,
different numbers are assigned to the respective plurality of redundant word lines,
different numbers are assigned to the respective plurality of redundant bit lines,
redundant word lines to which smaller numbers are assigned are preferentially used when the first defective word lines are replaced with the first redundant word lines,
redundant bit lines to which smaller numbers are assigned are preferentially used when the first defective bit lines are replaced with the first redundant bit lines,
redundant word lines to which greater numbers are assigned are preferentially used when the second defective word lines are replaced with the second redundant word lines, and
redundant bit lines to which greater numbers are assigned are preferentially used when the second defective bit lines are replaced with the second redundant bit lines.
9. A semiconductor device comprising:
a memory chip including a plurality of memory cells that include defective memory cells and redundant memory cells; and
a control chip stacked with the memory chip to control data read and write operations of the memory chip, the control chip including an analysis circuit,
wherein the analysis circuit of the control chip includes a plurality of fuse circuits to store a plurality of defective address information respectively indicative of the defective memory cells of the memory chip to generate replacing addresses, the replacing addresses causing the defective memory cells to be replaced respectively with ones of the redundant memory cells.
10. The semiconductor device as claimed in claim 9, wherein the analysis circuit of the control chip generates, when initially receiving the defective address information of one of the defective memory cells, error pattern information in response to the defective address information of the one of the defective memory cells and updates, when receiving the defective address information of another of the defective memory cells, the error pattern information in response to the defective address information of both of the one and another of the defective memory cells.
11. The semiconductor device as claimed in claim 10, wherein the control chip further includes an analysis memory including a register to store the error pattern information generated by the analysis circuit and the error pattern information stored in the register being overwritten when the error pattern information is updated by the analysis circuit.
12. The semiconductor device as claimed in claim 11, wherein the analysis memory of the control chip further includes one or more additional registers to store specified one or ones of the defective address information and the analysis circuit of the control chip generates the replacing addresses in response to both of the error pattern information stored in the register and the specified one or ones of the defective address information stored in the additional registers.
13. The semiconductor device as claimed in claim 9, wherein the memory cells of the memory chip further include additional defective memory cells and the memory chip further includes:
an additional fuse circuit storing additional replacing addresses, the additional replacing addresses causing the additional defective memory cells to be replaced respectively with additional ones of the redundant memory cells; and
a defective address latch circuit latching each of the replacing addresses and the additional replacing addresses.
14. The semiconductor device as claimed in claim 13, wherein one or more of the plurality of fuse circuits is to be programmed by an electric current and the additional fuse circuit of the memory chip is to be programmed by a laser beam.
15. The semiconductor device as claimed in claim 13, wherein the additional fuse circuit of the memory chip comprises an optical fuse circuit.
16. The semiconductor device as claimed in claim 9, wherein one or more of the plurality of fuse circuits comprises an electrical fuse circuit.