All The Claims

1. A semiconductor processing method of forming a contact opening comprising:
partially forming a first contact opening over a first insulative material over a node location with which electrical communication is desired;
at least partially filling the contact opening with a second insulative material; and
etching a second contact opening through the second insulative material and the first insulative material.
2. The semiconductor processing method of claim 1, wherein the etching outwardly exposes the substrate node location.
3. The semiconductor processing method of claim 1, wherein the etching comprises selectively etching the second contact opening relative to a different insulative material disposed within the confines of the second contact opening.
4. The semiconductor processing method of claim 1, wherein the first and second insulative materials are different.
5. The semiconductor processing method of claim 1, wherein the etching comprises selectively etching the second contact opening relative to a different insulative material which is disposed over a conductive component within the second contact opening, the second contact opening being self-aligned relative to the conductive component.
6. A semiconductor processing method of forming memory circuitry comprising:
forming an array of word lines and bit lines over a substrate surface and having a intervening insulative layer therebetween;
outwardly exposing conductive portions of the bit lines;
after the outwardly exposing, forming a layer of material over the substrate and exposed conductive portions of the bit lines;
removing selected portions of the layer of material and the intervening layer sufficient to (a) expose selected areas of the substrate surface at least some of which defining bit line contact areas with which electrical communication is desired, and (b) re-expose said conductive portions of the bit lines; and
after said removing, forming conductive material to electrically connect individual bit line contact areas and associated conductive portions of individual bit lines.
7. The semiconductor processing method of claim 6, wherein the outwardly exposing of the conductive portions of the bit lines comprises masking over portions of the bit lines and etching unmasked portions of the bit lines selectively relative to the intervening insulative layer.
8. The semiconductor processing method of claim 6, wherein the forming of the array of word lines and bit lines comprises:
forming a series of word lines over the substrate surface;
forming an insulative oxide layer over the word lines;
planarizing the insulative oxide layer, said insulative oxide layer defining said intervening layer; and
forming a series of bit lines over the intervening insulative oxide layer.
9. The semiconductor processing method of claim 6, wherein:
the forming of the array of word lines and bit lines comprises:
forming a series of word lines over the substrate surface;
forming an insulative oxide layer over the word lines;
planarizing the insulative oxide layer, said insulative oxide layer defining said intervening layer; and
forming a series of bit lines over the intervening insulative oxide layer; and

the outwardly exposing comprises:
masking the bit lines with a masking layer having a plurality of openings therein;
etching bit line material through the openings sufficiently to expose said conductive portions.
10. The semiconductor processing method of claim 6, wherein:
the forming of the array of word lines and bit lines comprises:
forming a series of word lines over the substrate surface;
forming an insulative oxide layer over the word lines;
planarizing the insulative oxide layer, said insulative oxide layer defining said intervening layer; and
forming a series of bit lines over the intervening insulative oxide layer;

the outwardly exposing comprises:
masking the bit lines with a masking layer having a plurality of openings therein; and
etching bit line material through the openings sufficiently to expose said conductive portions; and

the forming of the layer of material over the substrate comprises:
forming a second insulative oxide layer over the substrate; and
planarizing said second insulative oxide layer.
11. The semiconductor processing method of claim 6, wherein the forming of the layer of material over the substrate comprises forming an insulative oxide layer over the substrate and planarizing said insulative oxide layer.
12. The semiconductor processing method of claim 6, wherein the removing of the selected-portions of the layer of material and the intervening layer comprises:
masking over the individual word lines; and
etching the layer of material and the intervening layer selective to word line material.
13. The semiconductor processing method of claim 6, wherein the intervening layer separating the word lines and bit lines and the layer of material which is formed over the substrate comprise borophosphosilicate glass.
14. The semiconductor processing method of claim 6, wherein the forming of the conductive material comprises:
depositing polysilicon over the bit line contact areas and the associated conductive portion of the individual bit lines; and
removing polysilicon sufficient to isolate individual polysilicon plugs over the bit line contact areas.
15. The semiconductor processing method of claim 6, wherein other of the selected areas, which are exposed by the removing of the selected portions of the layer of material, define capacitor contact areas with which electrical communication with individual capacitors is desired.
16. The semiconductor processing method of claim 15, wherein forming of the conductive material to electrically connect individual bit line contact areas and associated conductive portions of individual bit lines also comprises forming said conductive material over and in electrical communication with the capacitor contact areas.
17. The semiconductor processing method of claim 16 further comprising:
forming insulative material over the conductive material electrically connecting the individual bit line contact areas and the associated conductive portions of the individual bit lines; and
forming a plurality of capacitors over the substrate, individual capacitors being in electrical communication with respective individual capacitor contact areas through the conductive material formed thereover.
18. In a matrix of conductive lines formed over a substrate comprising first and second- series of conductive lines, one series being formed over another, an electrical connection method of establishing electrical communication between at least some of the lines and substrate node locations comprising:
forming a masking layer over the substrate defining a plurality of openings over an uppermost of the series of lines;
removing material of individual lines of the uppermost series of lines and exposing conductive material of the individual lines;
after the removing of the material of the individual lines, forming insulative material over the substrate and the exposed conductive material;
masking over the substrate and defining mask openings over substrate node locations with which electrical communication is desired;
removing insulative material through the mask openings and other substrate material sufficient to expose both the conductive material of the individual lines which was previously exposed and the substrate node locations with which electrical communication is desired; and
forming a plurality of conductive interconnects over the substrate, the interconnects establishing electrical communication between second exposed conductive material of the individual lines and individual respective substrate node locations.
19. The electrical connection method of claim 18, wherein:
the removing of the insulative material and the other substrate material exposes other substrate node locations with which electrical communication is desired, the other substrate node locations being different from those substrate node locations which are in electrical communication with the second exposed conductive material through individual interconnects; and
the forming of a plurality of conductive interconnects also comprises forming conductive material over the other substrate node locations.
20. The electrical connection method of claim 19 further comprising:
forming insulative material over the individual interconnects; and
after the forming of the insulative material, forming a plurality of capacitors over the substrate and in electrical communication with the conductive material formed over the other substrate node locations.
21. The electrical connection method of claim 18, wherein the matrix comprises a portion of a memory array and the first and second series of conductive lines respectively comprise word lines and bit lines of the memory array.
22. The electrical connection method of claim 21, wherein the memory array comprises a DRAM array.
23. A semiconductor processing method of forming DRAM circuitry comprising:
forming an array of word lines and bit lines over a substrate, the bit lines being formed over the word lines and atop a first generally planarized insulative layer portions of which are disposed between the word lines and bit lines;
forming a masking layer over the substrate having openings therein which expose portions of the bit lines;
selectively etching bit line material through the openings relative to the insulative layer sufficient to expose conductive portions of the bit lines;
forming a second insulative layer over the substrate and the exposed conductive portions of the bit lines;
etching a plurality of contact openings through the first and second insulative layers sufficient to expose underlying substrate areas and to reexpose the conductive portions of the bit lines within some of the contact openings, the contact openings defining bit line contact openings and capacitor contact openings; and
depositing conductive material within the contact openings and in electrical communication with the exposed substrate areas, some of said material establishing electrical communication between the re-exposed conductive portions of the bit lines and respective associated exposed substrate areas.
24. The semiconductor processing method of claim 23, wherein etching of the bit line material comprises etching material from both the top and sides of individual bit lines sufficient to expose the conductive material.
25. The semiconductor processing method of claim 23, wherein etching of the bit line material comprises conducting an angled etch sufficient to expose conductive portions of the bit lines along individual sidewalls thereof.
26. The semiconductor processing method of claim 23 further comprising:
forming insulative material over conductive material within the bit line contact openings; and
forming capacitors over and in electrical communication with conductive material within the capacitor contact openings.
27. A semiconductor processing method of forming a DRAM array comprising:
forming a plurality of conductive lines over a substrate, at least some of which comprising word lines;
forming a first insulative layer over the substrate and word lines;
forming a plurality of bit lines over the first insulative layer, the word lines and bit lines defining an array having substrate contact areas with which electrical communication is desired, the substrate contact areas comprising both bit line contact areas and capacitor contact areas;
exposing conductive portions of the bit lines;
forming a second insulative layer over the substrate and exposed conductive portions of the bit lines;
exposing bit line contact areas, capacitor contact areas, and previously-exposed bit line conductive portions through at least one of the first and second insulative layers;
forming conductive material over and in respective electrical communication with exposed bit line contact areas and capacitor contact areas, conductive material over the bit line contact areas establishing electrical communication with the previously-exposed bit line conductive portions;
masking over the conductive material formed over the bit line contact areas; and
forming a plurality of storage capacitors over the substrate, individual capacitors being in electrical communication with individual respective capacitor contact areas through the respective conductive material formed thereover.
28. The semiconductor processing method of claim 27, wherein the exposing of the conductive portions of the bit lines comprises selectively etching material of the bit lines relative to the first insulative material.
29. The semiconductor processing method of claim 27, wherein the exposing of the conductive portions of the bit lines comprises not exposing any word line material.
30. The semiconductor processing method of claim 27, wherein the exposing of the conductive portions of the bit lines comprises conducting an angled etch sufficient to expose sidewall material of the bit lines.
31. The semiconductor processing method of claim 27, wherein the exposing of the conductive portions of the bit lines comprises etching bit line material from the top and sides of the individual bit lines.
32. The semiconductor processing method of claim 27, wherein the exposing of the conductive portions of the bit lines comprises selectively etching bit line material from the top and sides of the individual bit lines relative to the first insulative material.
33. The semiconductor processing method of claim 27 further comprising planarizing the second insulative layer prior to exposing the bit line contact areas, capacitor contact areas, and bit line conductive portions.
34. The semiconductor processing method of claim 27, wherein the exposing of the bit line contact areas, capacitor contact areas, and bit line conductive portions comprises etching both the first and second insulative layers selectively relative to both bit line and word line material.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A pressure-sensitive adhesive foam, which is a foamed cured product of a curable composition comprising:
a partial polymer comprising
(a) one or more alkyl (meth)acrylate monomers having one reactive unsaturated group, the alkyl group having 12 or less carbon atoms,
(b) a monomer for crosslinking, which is copolymerizable with the component (a), and
(c) a copolymer of the component (a) and the component (b);
a thermally conductive filler; and
a foaming adjuvant containing surface modified nanoparticles having a particle diameter of 20 nm or less,
wherein a crosslinked structure containing said component (c) is formed in said curable composition.
2. The pressure-sensitive adhesive foam, which is a foamed cured product of a curable composition comprising:
a partial polymer comprising
(a) one or more alkyl (meth)acrylate monomers having one reactive unsaturated group, the alkyl group having 12 or less carbon atoms,
(b1) one or more monomers having two or more reactive unsaturated groups, and
(c1) a copolymer of the component (a) and the component (b1), the amount of said component (c1) being from 2% to 15% by weight based on the weight of said partial polymer;
a thermally conductive filler in the amount of 100 to 250 parts by weight based on 100 parts by weight of said partial polymer; and
a foaming adjuvant containing surface modified nanoparticles having a particle diameter of 20 nm or less, in the amount of 0.1 to 1.5 parts by weight based on 100 parts by weight of said partial polymer,
wherein a crosslinked structure formed in said curable composition is a crosslinked copolymer of said component (a) and said component (b1) and
wherein said pressure-sensitive adhesive foam has an air bubble content that is expressed by the volume percentage based on the entire volume of the foam, the value of (parts by weight of said foaming adjuvant based on 100 parts by weight of the resin component of said curable composition)(content of air bubbles of said pressure-sensitive adhesive foam) is from 0.02 to 0.05.
3. The pressure-sensitive adhesive foam, which is a foamed cured product of a curable composition comprising:
a partial polymer comprising
(a) one or more alkyl (meth)acrylate monomers having one reactive unsaturated group, the alkyl group having 12 or less carbon atoms,
(b2) one or more monomers having a carboxyl group, and
(c2) a copolymer of the component (a) and the component (b2), the amount of said component (c2) being from 2% to 15% by weight based on the weight of said partial polymer;
a thermally conductive filler in the amount of 60 to 300 parts by weight based on 100 parts by weight of said partial polymer, said thermally conductive filler being a metal hydroxide having a basic group on the particle surface; and
a foaming adjuvant containing surface modified nanoparticles having a particle diameter of 20 nm or less, in the amount of 0.1 to 1.5 parts by weight based on 100 parts by weight of said partial polymer,
wherein a crosslinked structure formed in said curable composition is a crosslinked structure in which said component (c2) is crosslinked through said component (b2) in said component (c2) and said thermally conductive filler, and
wherein said pressure-sensitive adhesive foam has an air bubble content that is expressed by the volume percentage based on the entire volume of the foam, the value of (parts by weight of said foaming adjuvant based on 100 parts by weight of the resin component of said curable composition)(content of air bubbles of said pressure-sensitive adhesive foam) is from 0.02 to 0.05.
4. The pressure-sensitive adhesive foam, which is a foamed cured product of a curable composition comprising:
a partial polymer comprising
(a) one or more alkyl (meth)acrylate monomers having one reactive unsaturated group, the alkyl group having 12 or less carbon atoms,
(b1) one or more monomers having two or more reactive unsaturated groups,
(b2) one or more monomers having a carboxyl group, and
(c3) a copolymer of the component (a), the component (b1) and the component (b2), the amount of said component (c3) being from 2% to 15% by weight based on the weight of said partial polymer;
a thermally conductive filler in the amount of 60 to 300 parts by weight based on 100 parts by weight of said partial polymer, said thermally conductive filler being a metal hydroxide having a basic group on the particle surface; and
a foaming adjuvant containing surface modified nanoparticles having a particle diameter of 20 nm or less, in the amount of 0.1 to 1.5 parts by weight based on 100 parts by weight of said partial polymer,
wherein a crosslinked structure formed in said curable composition is a crosslinked structure in which said component (a) is copolymerized with said component (b1) to form a crosslink and in which said component (c3) is crosslinked through said component (b2) in said component (c3) and said thermally conductive filler, and
wherein said pressure-sensitive adhesive foam has an air bubble content that is expressed by the volume percentage based on the entire volume of the foam, the value of (parts by weight of said foaming adjuvant based on 100 parts by weight of the resin component of said curable composition)(content of air bubbles of said pressure-sensitive adhesive foam) is from 0.02 to 0.05.
5. The pressure-sensitive adhesive foam of claim 1, having the air bubble content from 5% to 25% by volume based on the entire volume of the foam.
6. The pressure-sensitive adhesive foam of claim 1, wherein said thermally conductive filler is aluminum hydroxide.
7. The pressure-sensitive adhesive foam of claim 1, wherein said curable composition is ultraviolet-curable.
8. (canceled)
9. The pressure-sensitive adhesive foam of claim 2 having the air bubble content from 5% to 25% by volume based on the entire volume of the foam.
10. The pressure-sensitive adhesive foam of claim 2, wherein said thermally conductive filler is aluminum hydroxide.
11. The pressure-sensitive adhesive foam of claim 2, wherein said curable composition is ultraviolet-curable.
12. The pressure-sensitive adhesive foam of claim 3 having the air bubble content from 5% to 25% by volume based on the entire volume of the foam.
13. The pressure-sensitive adhesive foam of claim 3, wherein said thermally conductive filler is aluminum hydroxide.
14. The pressure-sensitive adhesive foam of claim 3, wherein said curable composition is ultraviolet-curable.
15. The pressure-sensitive adhesive foam of claim 4 having the air bubble content from 5% to 25% by volume based on the entire volume of the foam.
16. The pressure-sensitive adhesive foam of claim 4, wherein said thermally conductive filler is aluminum hydroxide.
17. The pressure-sensitive adhesive foam of claim 4, wherein said curable composition is ultraviolet-curable.
18. A method for producing a pressure-sensitive adhesive foam, comprising:
preparing a partial polymer comprising
(a) one or more alkyl (meth)acrylate monomers having one reactive unsaturated group, the alkyl group having 12 or less carbon atoms,
(b) a monomer for crosslinking, which is copolymerizable with the component (a), and
(c) a copolymer of the component (a) and the component (b);
mixing said partial polymer with a thermally conductive filler;
adding a foaming adjuvant containing surface modified nanoparticles having a particle diameter of 20 nm or less to said partial polymer to obtain a curable composition in which a crosslinked structure containing said component (c) is formed;
mechanically foaming said curable composition; and
curing a molded article of said foamed curable composition.

1. A sensor electrode for interrogating an earth formation, the sensor electrode comprising:
a geometry that reduces spatial aliasing in formation data when the sensor electrode is disposed in an array.
2. The sensor electrode as in claim 1, wherein a geometry for the sensor electrode comprises one of a diamond shape, a one-row zigzag shape, a one-row double zigzag shape, a one-row triple zigzag shape and a one-row wavelet shape.
3. The sensor electrode as in claim 1, wherein the geometry of the sensor electrode provides for high resolution in at least one of vertical direction and a horizontal direction.
4. The sensor electrode as in claim 1, wherein the geometry provides for reduction of spatial offset.
5. The sensor electrode as in claim 1, wherein the geometry provides for reduction in angular dependance.
6. The sensor electrode as in claim 1, wherein the geometry provides for improved frequency response.
7. The sensor electrode as in claim 1, wherein the geometry comprises smoothed and tuned edges.
8. The sensor electrode as in claim 1, wherein the geometry of the sensor electrode comprises dimensions such that an apparent horizontal size of the sensor electrode is larger than a horizontal separation when the sensor electrode is disposed in the array.
9. A method for designing a sensor electrode for interrogating an earth formation, the method comprising:
determining a geometry for the sensor electrode;
evaluating a response function for the sensor electrode; and
adjusting a geometry of the sensor electrode to improve the response function.
10. The method as in claim 9, wherein the response function comprises a response function for at least one of spatial aliasing, spatial offset, angular dependance, frequency response and resolution.
11. The method as in claim 9, wherein a geometry for the sensor electrode is one of a diamond shape, a one-row zigzag shape, a one-row double zigzag shape, a one-row triple zigzag shape and a one-row wavelet shape.
12. The method as in claim 9, wherein determining comprises selecting dimensions for the sensor electrode such that in an array of the sensor electrodes, (1apparent horizontal dimension of the sensor electrode) is less than (2horizontal separation of each sensor electrode of the array).
13. A computer program product stored on machine readable media, the product comprising machine executable instructions for designing a sensor electrode for interrogating an earth formation, the instructions comprising instructions for:
receiving an input geometry for the sensor electrode;
evaluating at least one response function for the sensor electrode; and
adjusting the geometry according to desired response for each response function.
14. The computer program product as in claim 13, wherein the response function comprises a Nyquist criteria.
15. An array of sensor electrodes for interrogating an earth formation, the array comprising sensor electrodes comprising a one-row wavelet geometry.
16. The array as in claim 15, wherein the geometry provides for reduction of spatial offset.
17. The array as in claim 15, wherein the geometry provides for reduction in angular dependance.
18. The array as in claim 15, wherein the geometry provides for improved frequency response.
19. The array as in claim 15, wherein the geometry comprises smoothed and tuned edges.
20. The array as in claim 15, wherein the geometry of the sensor electrode comprises dimensions such that an apparent horizontal size of the sensor electrode is larger than a horizontal separation when the sensor electrode is disposed in the array.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A substrate based on silicon nitride for semiconductor components, characterized in that the substrate contains, as crystalline phases, silicon nitride (Si3N4), silicon carbide (SiC) and silicon oxynitride (Si2N2O), and the crystalline silicon content is 5%, based on the sum of the crystalline phases which are present, the shrinkage during production is <5% and the open porosity of the substrate is <15% by volume.
2. The substrate as claimed in claim 1, characterized in that the substrate contains sintering additives in a total concentration of <20% by weight, which additives form a liquid phase during production and are present in the substrate as an amorphous secondary phase or as more complex additional crystalline phases.
3. The substrate as claimed in claim 2, characterized in that the sintering additives are SiO2, alkaline earth metal oxides, oxides from group III B and IV B of the periodic system, including the rare earth oxides V, Nb, Ta, Cr, Fe, Co andor Ni oxide alone or in combination with B2O3, Al2O3 andor TiO2.
4. The substrate as claimed in at least one of claims 1 to 3, characterized in that the substrate contains carbides, nitrides, carbonitrides, oxynitrides, silicides andor borides of the elements Si, Al, Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, W, Mn, Fe, Ca andor Ni in concentrations of <10% by weight, calculated as the corresponding compound, the total content of these constituents not exceeding 10% by weight.
5. The substrate as claimed in at least one of claims 1 to 4, characterized in that the substrate contains carbides, nitrides, carbonitrides, suicides andor borides of the elements Si, Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, W, Mn andor Fe as a further main crystalline phase in concentration of 30% by volume and has an electrical conductivity of 0,1 Sm.
6. The substrate as claimed in at least one of claims 4 to 5, characterized in that the abovementioned substances are introduced as inorganic fibers, whiskers, platelets or particles andor are present in this form in the substrate.
7. The substrate as claimed in at least one of claims 1 to 6, characterized in that the substrate contains carbon fibers which are present as such in the substrate or have partially or completely reacted to form more complex compounds.
8. A process for producing the substrate as claimed in one of claims 1 to 7, characterized in that the starting mixture is mixed intensively, shaped by pressing, slip casting, hot pressing, extrusion or tape casting, crosslinked and pyrolyzed in an inert atmosphere, then nitrided and if necessary sintered.
9. The process as claimed in claim 8, characterized in that the shaping of the starting mixture takes place by tape casting of a solids suspension based on the silicon-organic polymer dissolved in an organic solvent.
10. The process as claimed in claim 9, characterized in that the solids suspension contains further organic additives in addition to the silicon-organic polymer.
11. The process as claimed in at least one of claims 8 to 10, characterized in that the nitriding takes place at temperatures of <1500 C. at an N2 pressure of 1 bar.
12. The process as claimed in at least one of claims 8 to 10, characterized in that the nitriding takes place at temperatures of <1500 C. under a N2 pressure of from 1 to 100 bar.
13. The use of the substrate as claimed in one of claims 1 to 7 for producing semiconductor components.
14. The use of the substrate as claimed in one of claims 1 to 7 for producing thin-film solar cells.
15. A semiconductor component which includes the substrate as claimed in at least one of claims 1 to 7.
16. The semiconductor component as claimed in claim 15, characterized in that one or more crystalline silicon layers are deposited on the substrate.
17. The semiconductor component as claimed in claim 16, characterized in that one or more additional layers are applied between the substrate and the silicon layers.
18. The semiconductor component as claimed in claim 17, characterized in that the additional layers are silicon nitride, silicon oxide or silicon carbide layers.
19. The semiconductor component as claimed in at least one of claims 15 to 18, characterized in that the semiconductor component is a thin-film solar cell.