All The Claims

1. An atomic layer deposition method, comprising the steps of:
placing a semiconductor substrate in an atomic layer deposition chamber;
flowing a first precursor gas to the semiconductor substrate within the atomic layer deposition chamber to form a first discrete monolayer on the semiconductor substrate;
flowing an inert purge gas to the semiconductor substrate within the atomic layer deposition chamber to remove the first precursor gas which does not form the first monolayer on the semiconductor substrate;
flowing a second precursor gas to the atomic layer deposition chamber to react with the first precursor gas which forms the first monolayer, thereby forming a first discrete compound monolayer;
flowing an inert purge gas to the semiconductor substrate within the atomic layer deposition chamber to remove the second precursor gas which does not react with the first precursor gas and a byproduct of the reaction between the first and the second precursor gases;
forming a first dielectric layer to cover the first discrete compound monolayer on the semiconductor substrate;
flowing a third precursor gas to the atomic layer deposition chamber to form a third discrete monolayer above first dielectric layer;
flowing an inert purge gas to the atomic layer deposition chamber to remove the third precursor gas which does not form the third monolayer with the first dielectric layer;
flowing a forth precursor gas to the atomic layer deposition chamber to react with the third precursor gas which has formed the third monolayer, thereby forming a second discrete compound monolayer;
flowing an inert purge gas to the atomic layer deposition chamber to remove the forth precursor gas which does not react with the third monolayer and a byproduct of the reaction between the third and the forth precursor gases; and
forming a second dielectric layer to cover the second discrete compound monolayer above the first dielectric layer.
2. The atomic layer deposition method in claim 1, further comprising forming a third discrete compound monolayer on the second dielectric layer; forming a third dielectric layer to cover the third discrete compound monolayer above the second dielectric layer; . . . ; and in the same way, forming a (N+1)th discrete compound monolayer on the Nth dielectric layer, and forming a (N+1)th dielectric layer to cover the (N+1)th discrete compound monolayer above the Nth dielectric layer, where the N is an integer no less than 3.
3. The atomic layer deposition method in claim 1, wherein the first precursor is selected from one or more of metal, semiconductor, metal coordinated with halogen and organic complex, and semiconductor coordinated with halogen and organic complex, or mixtures thereof.
4. The atomic layer deposition method in claim 3, wherein the metal comprises Ta, Ti, W, Mo, Nb, Cu, Ni, Pt, Ru, Me, Ni or Al.
5. The atomic layer deposition method in claim 3 wherein the semiconductor is silicon.
6. The atomic layer deposition method in claim 3, wherein the metal coordinated with halogen and organic complex comprises Al(CH3)3, HfN(CH3)(C2H5)4, HfN(C2H5)24, HfOC(CH3)34, or HfCl4, and the semiconductor coordinated with halogen and organic complex comprises SiCl2H2, Si(OC2H5)4, Si2Cl6, SiH2NH(C4H9)2, or SiH(OC2H5)3.
7. The atomic layer deposition method in claim 1, wherein when the first precursor is SiCl2H2, the first precursor flows to the semiconductor substrate in the atomic layer deposition chamber at a flow rate of 0.06\u02dc0.3 slm for 0\u02dc10 sec.
8. The atomic layer deposition method in claim 1, wherein the second precursor comprises NH3, N2O, N2, O2, O3, or H2O.
9. The atomic layer deposition method in claim 1, wherein the third precursor is selected from one or more of metal, semiconductor, metal coordinated with halogen and organic complex, and semiconductor coordinated with halogen and organic complex, or mixtures thereof.
10. The atomic layer deposition method in claim 9, wherein the metal comprises Ta, Ti, W, Mo, Nb, Cu, Ni, Pt, Ru, Me, Ni or Al.
11. The atomic layer deposition method in claim 9, wherein the semiconductor is silicon.
12. The atomic layer deposition method in claim 9, wherein the metal coordinated with halogen and organic complex comprises Al(CH3)3, HfN(CH3)(C2H5)4, HfN(C2H5)24, HfOC(CH3)34, or HfCl4, and the semiconductor coordinated with halogen and organic complex comprises SiCl2H2, Si(OC2H5)4, Si2Cl6, SiH2NH(C4H9)2, or SiH(OC2H5)3.
13. The atomic layer deposition method in claim 9, wherein when the third precursor is SiCl2H2, the third precursor flows to the semiconductor substrate in the atomic layer deposition chamber at a flow rate of 0.06\u02dc0.3 slm for 0\u02dc10 sec.
14. The atomic layer deposition method in claim 1, wherein the fourth precursor gas comprises NH3, N2O, N2, O2, O3, or H2O.
15. The atomic layer deposition method in claim 1, wherein the process for forming the first dielectric layer is an atomic layer deposition process.
16. The atomic layer deposition method in claim 15, wherein the process for forming the first dielectric layer comprises the following steps:
(I) flowing a fifth precursor gas to the atomic layer deposition chamber to form a fifth monolayer above the semiconductor substrate and the first discrete compound monolayer, wherein the fifth monolayer fills the spacing in the first discrete compound monolayer;
(II) flowing an inert purge gas to the atomic layer deposition chamber to remove the fifth precursor gas that does not form the fifth monolayer above the semiconductor substrate and the first discrete compound monolayer;
(III) flowing a sixth precursor gas to the atomic layer deposition chamber to react with the fifth precursor gas that has formed the fifth monolayer, thereby forming a first dielectric mono-atomic layer;
(IV) flowing an inert purge gas to the atomic layer deposition chamber to remove the sixth precursor gas that does not form the first dielectric mono-atomic layer and the byproduct of the reaction between the fifth and the sixth precursor gases; and
repeating the steps (I) to (IV) until the resulting first dielectric layer has a given thickness to cover the first discrete compound monolayer.
17. The atomic layer deposition method in claim 1, wherein the first dielectric layer is made of silicon oxide.
18. A semiconductor device, comprising a semiconductor substrate, a three-layer stack structure of medium layer-charge trapping layer-medium layer disposed above the semiconductor substrate, a gate disposed above the three-layer stack structure, and a source and a drain disposed in the semiconductor substrate at either side of the three-layer stack structure, the charge trapping layer is a dielectric layer containing one or more discrete compound monolayers formed by ALD method.
19. The semiconductor device in claim 18, wherein the size of the discrete compound monolayer is at atomic level.
20. The semiconductor device in claim 18, wherein the discrete compound monolayer is made of silicon nitride, aluminum oxide, hafnium oxide or tungsten nitride.
21. The semiconductor device in claim 18 wherein the dielectric layer is made of silicon oxide.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1-7. (cancelled)
8. A steering wheel that comprises a closed annular steering wheel rim and spokes and further comprises a steering wheel skeleton as well as a sheathing therefore, said sheathing being one of a foam covering and a leather covering that surrounds said steering wheel skeleton, said one-piece steering wheel skeleton having a closed annular portion to form said steering wheel rim, a cross-section of said steering wheel rim having an open hollow profile, a body that serves as a spacer being inserted in said open hollow profile and almost completely filling said hollow profile, and said steering wheel skeleton being provided with said sheathing at least in an area of said steering wheel rim.

1. A watering jug for dispensing a measured amount of water to hanging plants, said jug comprising
a) a container for receiving a quantity of water to be dispensed;
b) a lid securable to a top portion of said container;
c) an intake tube extending through said lid;
d) a manually operable pump sitting atop said intake tube, said pump drawing a measured amount of water into said intake tube;
e) a discharge tube forming a juncture with, and extending outwardly from, said intake tube at a point beneath said pump;
f) a valve in said intake tube at said juncture allowing said pump to draw said measured amount of water from said container through said intake tube and redirect it into said discharge tube;
g) an elongated delivery tube extending from said discharge tube a distance exceeding a height of said container;

whereby said watering jug enables a person to deliver a measured amount of water conveniently and reliably to a hanging plant positioned several feet above herhis head
h) an extension sleeve formed over an end of said intake tube, said extension sleeve being movable between a plurality of distinctly defined fixed positions;
i) an adjustment handle attached to said extension sleeve, said adjustment handle having a plurality of teeth formed along at least one side thereof and extending through said lid, said plurality of teeth defining said plurality of distinctly defined fixed positions, a distance between a pair of said plurality of teeth defining a quantity of water which can be extracted from said container and delivered from said end of said delivery tube.
2. The watering jug of claim 1 further comprising a distal end of said elongated delivery tube having a curved portion to render its discharge opening downwardly directed.
3. The watering jug of claim 2 further comprising a sprinkling head affixed to said downwardly directed distal end.
4. The watering jug of claim 1 further comprising a rigid brace extending upwardly from said lid, underlying a significant portion of a length of said delivery tube, and being clipped in a plurality of places to said delivery tube to maintain said delivery tube in an upwardly angled position.
5. The watering jug of claim 1 wherein said lid has an opening in a rear portion thereof to permit filling of said jug without removing said lid.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. A method of fabricating a buried plate electrode within a trench cell capacitor of a semiconductor substrate, comprising:
forming a trench within a semiconductor substrate;
forming an oxide collar in an upper portion of said trench;
depositing a conformal metal film to cover a lower portion of said trench and said oxide collar;
annealing said semiconductor substrate to form a self-aligned silicide layer in said lower portion of said trench; and
selectively removing all or portions of said conformal metal film from said oxide collar.
2. The method of claim 1 further comprising depositing hemispherical silicon grains in said trench prior to depositing said conformal metal film, such that said silicide layer has increased surface area.
3. The method of claim 1 further comprising forming a node dielectric over said self-aligned silicide layer.
4. The method of claim 3 further comprising depositing polysilicon over said node dielectric, depositing a second conformal metal film over said polysilicon and annealing said second conformal metal film to form a suicide node electrode within said trench.
5. The method of claim 4 further comprising depositing polysilicon to fill said trench, thereby forming a node electrode.
6. The method of claim 1, wherein said metal film is deposited by low pressure chemical vapor deposition at temperatures ranging between 40C and 700C.
7. The method of claim 6, wherein said low pressure chemical vapor deposition is performed at pressures between 1 mTorr and 500 mTorr.
8. The method of claim 7, wherein said low pressure chemical vapor deposition if performed by atomic layer chemical vapor deposition using a plasma enhanced process step.
9. The method of claim 1, wherein said annealing step is performed in a single-wafer rapid thermal annealing (RTA) system.
10. The method of claim 1, wherein said annealing step is performed in a large batch style furnace.
11. The method of claim 2, wherein said collar is formed by trench sidewall oxidation at an oxidizing pressure below 106 Torr.
12. An integrated circuit including a trench capacitor, said trench capacitor comprising:
an oxide collar formed in an upper portion of a trench etched into a semiconductor substrate; and
a metal silicide covering a lower portion of said trench as a buried plate electrode of said trench capacitor, said silicide being self-aligned to said collar by depositing a conformal metal film over said trench, including said collar, annealing said conformal metal film to form said metal silicide in said lower portion and etching unreacted metal film from said collar thereafter.
13. The trench capacitor of claim 12, wherein said trench has a bottle-shape.
14. The trench capacitor of claim 13 further comprising a layer of hemispherical silicon grains in said lower portion of said trench, over which said metal silicide is formed.
15. The trench capacitor of claim 12 further comprising a node dielectric covering said metal silicide.
16. The trench capacitor of claim 15 further comprising a metal silicide overlaying said node dielectric as a node electrode.
17. The trench capacitor of claim 15 further comprising a metal layer overlaying said node dielectric as a node electrode.