All The Claims

1. A storage control system, connected to an external storage control system and a host device, for controlling access by the host device to the storage resources in the external storage control system, comprising:
a plurality of logical storage devices that store data exchanged with the host device;
one or a plurality of physical storage devices comprising the plurality of logical storage devices;
a cache memory that stores data exchanged between the host device and the physical storage devices;
a channel control unit, having a control processor, that receives control system information from the external storage control system and controls data communications between the cache memory and at least one of the host device and the external storage control system;
a disk control unit that controls data communications between the cache memory and the physical storage devices; and
a key information item storage area that stores one or a plurality of key information items with a fixed constitution,
wherein each of the one or the plurality of key information items corresponds with each of the type or types of the external storage control system, and
wherein the control processor of the channel control unit selects a key information item from among the one or the plurality of key information items, judges whether, in the control system information received from the external storage control system and indicated by the information element in the selected key information item, there exists the information element in the selected key information item, and forms a logical path between the host device and the storage resources in the external storage control system when an affirmative judgment result is obtained but does not form the logical path when a negative judgment result is obtained.
2. The storage control system according to claim 1, wherein the key information item includes:
an information element that indicates at least one of the vendor ID and device name of the external storage control system corresponding with this key information item;
an information element that indicates the location in the control system information of at least one of the vendor ID and the device name; and
an information element that indicates at least one of the data size of the vendor ID and the device name.
3. The storage control system according to claim 1, wherein a maintenancemanagement system for maintaining or managing the storage control system is connected to the channel control unit, and
wherein when the affirmative judgment result is obtained, the control processor of the channel control unit transmits all the information items included in the received control system information to the maintenancemanagement system such that all the information items are displayed, and forms the logical path upon receiving a logical path formation request from the maintenancemanagement system.
4. The storage control system according to claim 1, wherein another information element indicating the usable storage capacity in the storage resources in the external storage control system corresponding with the key information item is included in another predetermined location of the key information item, and
wherein when write target data is received from the host device, the control processor of the channel control unit judges whether the storage capacity indicated by the another information element in the key information item corresponding with the type of the external storage control system is exceeded by the total value of the data size of the write target data and the total data size of one or a plurality of data stored cumulatively in the external storage control system, and stores the write target data in the storage resources in the external storage control system when the indicated storage capacity is not exceeded.
5. The storage control system according to claim 4, wherein, when the total value exceeds the indicated storage capacity, the control processor of the channel control unit communicates the fact that it is necessary to increase the storage capacity indicated by the another information element in the key information item to the host device, receives data for increasing the indicated storage capacity and then increases the value of the indicated storage capacity.
6. The storage control system according to claim 1, wherein the control processor of the channel control unit forms the logical path and then, when a predetermined event has occurred, receives the control system information from the external storage control system and performs the judgment, erasing the logical path if a negative judgment result is obtained.
7. The storage control system according to claim 1, wherein a maintenancemanagement system for maintaining or managing the storage control system is connected to the channel control unit,
wherein the maintenancemanagement system comprises:
a maintenancemanagement storage unit for storing data;
the key information item is downloaded to the maintenancemanagement system from a key management database that stores cumulatively a plurality of key information items corresponding with a plurality of types of the external storage control system and is then stored in the key information item storage area; and
the key information item storage area is provided in local memory that is used by the control processor of the channel control unit, and the maintenancemanagement storage unit.
8. The storage control system according to claim 1, wherein a Fibre Channel Adapter or iSCSI adapter connected to the external storage control system is included in the channel control unit, and
wherein the control processor is mounted in the Fibre Channel Adapter or the iSCSI adapter.
9. The storage control system according to claim 8, wherein the Fibre Channel Adapter or the iSCSI adapter transmits an inquiry command according to the SCSI protocol to the external storage control system and receives the control system information from the external storage control system in response to the inquiry command.
10. The storage control system according to claim 1, comprising:
a virtual intermediate storage device between the logical storage device and the physical storage device,
wherein the control processor of the channel control unit forms the logical path by associating the logical storage device and the external logical storage device, which is a storage resource in the external storage control system, with a logical location in the virtual intermediate storage device.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for kernel masking dynamic random access memory (DRAM) defects, the method comprising:
detecting and correcting a single-bit error associated with a physical address in a dynamic random access memory (DRAM);
receiving error data associated with the physical address from the DRAM;
storing the received error data in a failed address table located in a non-volatile memory; and
retiring a kernel page corresponding to the physical address if a number of errors associated with the physical address exceeds an error count threshold;
wherein the retiring the kernel page corresponding to the physical address comprises:
generating and storing a bad pages list in the non-volatile memory, the bad pages list identifying a kernel page holding the physical address which is to be excluded from memory allocation.
2. The method of claim 1, wherein the single-bit error is detected and corrected by the DRAM.
3. The method of claim 1, wherein receiving the error data associated with the physical address from the DRAM comprises: an operating system querying the DRAM for error data.
4. The method of claim 1, wherein the received error data identifies a DRAM bank, column, and row address corresponding to a failed codeword address.
5. The method of claim 4, wherein the storing the received error data in the failed address table comprises: updating the number of errors associated with the failed codeword address.
6. The method of claim 1, further comprising:
transferring content of the kernel page to a new empty kernel page; and
removing the kernel page from future use.
7. The method of claim 1, further comprising:
at a device boot-up, reading the bad pages list stored in the non-volatile memory; and
excluding the kernel page identified in the bad pages list from an operating system free page block list.
8. The method of claim 1, further comprising:
executing, at a device boot-up, a primary boot loader from a memory other than the DRAM and the non-volatile memory;
reading the bad pages list from the non-volatile memory; and
determining a contiguous block of error-free DRAM by excluding one or more kernel pages identified in the bad pages list.
9. The method of claim 8, further comprising:
executing a secondary boot loader from the error-free DRAM;
loading an operating system from the error-free DRAM;
the operating system configuring a free blocks list that excludes the kernel page identified in the bad pages list.
10. The method of claim 1, wherein the retiring the kernel page corresponding to the physical address comprises: excluding the kernel page from allocated DRAM.
11. A system for kernel masking dynamic random access memory (DRAM) defects, the system comprising:
means for detecting and correcting a single-bit error associated with a physical address in a dynamic random access memory (DRAM);
means for receiving error data associated with the physical address from the DRAM;
means for storing the received error data in a failed address table located in a non-volatile memory; and
means for retiring a kernel page corresponding to the physical address if a number of errors associated with the physical address exceeds an error count threshold, wherein the means for retiring the kernel page corresponding to the physical address comprises:
means for generating and storing a bad pages list in the non-volatile memory, the bad pages list identifying a kernel page holding the physical address which is to be excluded from memory allocation.
12. The system of claim 11, wherein the means for receiving the error data from the DRAM comprises: means for querying the DRAM for error data.
13. The system of claim 11, wherein the received error data identifies a DRAM bank, column, and row address corresponding to a failed codeword address.
14. The system of claim 13, wherein the means for storing the received error data in the failed address table comprises: means for updating the number of errors associated with the failed codeword address.
15. The system of claim 11, further comprising:
means for reading, at a device boot-up, the bad pages list stored in the non-volatile memory; and
means for excluding the kernel page identified in the bad pages list from an operating system free page block list.
16. The system of claim 11, further comprising:
means for executing, at a device boot-up, a primary boot loader from a memory other than the DRAM and the non-volatile memory;
means for reading the bad pages list from the non-volatile memory; and
means for determining a contiguous block of error-free DRAM by excluding one or more kernel pages identified in the bad pages list.
17. The system of claim 11, further comprising:
means for executing a secondary boot loader from the error-free DRAM;
means for loading an operating system from the error-free DRAM;
means for configuring an operating system free blocks list that excludes the kernel page identified in the bad pages list.
18. The system of claim 11, wherein the retiring the kernel page corresponding to the physical address comprises: excluding the kernel page from allocated DRAM.
19. A computer program embodied in a non-transitory computer readable medium and executable by a processor for kernel masking dynamic random access memory (DRAM) defects, the computer program comprising logic configured to:
detect and correct a single-bit error associated with a physical address in a dynamic random access memory (DRAM);
receive error data associated with the physical address from the DRAM;
store the received error data in a failed address table located in a non-volatile memory; and
retire a kernel page corresponding to the physical address if a number of errors associated with the physical address exceeds an error count threshold, wherein the logic configured to retire the kernel page corresponding to the physical address comprises: logic configured to generate and store a bad pages list in the non-volatile memory, the bad pages list identifying a kernel page holding the physical address which is to be excluded from memory allocation.
20. The computer program of claim 19, wherein the single-bit error is detected and corrected by the DRAM.
21. The computer program of claim 19, wherein the logic configured to receive the error data from the DRAM comprises: logic configured to query the DRAM for error data.
22. The computer program of claim 19, wherein the received error data identifies a DRAM bank, column, and row address corresponding to a failed codeword address.
23. The computer program of claim 22, wherein the logic configured to store the received error data in the failed address table comprises: logic configured to update the number of errors associated with the failed codeword address.
24. The computer program of claim 19, further comprising:
logic configured to read, at a device boot-up, the bad pages list stored in the non-volatile memory; and
logic configured to exclude the kernel page identified in the bad pages list from an operating system free page block list.
25. The computer program of claim 19, further comprising:
logic configured to execute, at a device boot-up, a primary boot loader from a memory other than the DRAM and the non-volatile memory;
logic configured to read the bad pages list from the non-volatile memory; and
logic configured to identify a contiguous block of error-free DRAM by excluding one or more kernel pages identified in the bad pages list.
26. The computer program of claim 25, further comprising:
logic configured to execute a secondary boot loader from the error-free DRAM;
logic configured to load an operating system from the error-free DRAM;
logic configured to generate a free blocks list that excludes the kernel page identified in the bad pages list.
27. The computer program of claim 19, wherein the logic configured to retire the kernel page corresponding to the physical address comprises: logic configured to exclude the kernel page from allocated DRAM.
28. A system for masking dynamic random access memory (DRAM) defects, the system comprising:
a dynamic random access memory (DRAM) system;
an error correcting code (ECC) module for detecting and correcting bit errors associated with failed codeword addresses in the DRAM system; and
a central processing unit (CPU) executing an operating system comprising a bad page masking module, the bad page masking module comprising logic configured to:
receive, via one or more of the DRAM system and the ECC module, error data associated with the failed codeword addresses;
store the received error data in a failed codeword address table located in a non-volatile memory; and

retire kernel pages corresponding to a failed codeword address if a number of errors associated with a respective failed codeword address exceeds an error count threshold, wherein the logic configured to retire the kernel page corresponding to the failed codeword address comprises: logic configured to generate and store a bad pages list in the non-volatile memory, the bad pages list identifying a kernel page holding the failed codeword address.
29. The system of claim 28, wherein the ECC module resides in the DRAM system, and the CPU resides on a system on chip (SoC) electrically coupled to the DRAM system.
30. The system of claim 28, wherein the logic configured to receive, via one or more of the DRAM system and the ECC module, the error data comprises: logic configured to query the DRAM system for error data.
31. The system of claim 28, wherein the logic configured to store the received error data in the failed codeword address table comprises: logic configured to update the number of errors associated with a failed codeword address.
32. The system of claim 28, further comprising:
logic configured to read, at a device boot-up, the bad pages list stored in the non-volatile memory; and
logic configured to exclude the kernel page identified in the bad pages list from an operating system free page block list.
33. The system of claim 28, further comprising:
logic configured to execute, at a device boot-up, a primary boot loader from one of a read only memory (ROM) and a static random access memory (SRAM);
logic configured to read the bad pages list from the non-volatile memory; and
logic configured to identify a contiguous block of error-free DRAM by excluding the kernel pages identified in the bad pages list.
34. The system of claim 33, further comprising:
logic configured to execute a secondary boot loader from the error-free DRAM;
logic configured to load an operating system from the error-free DRAM;
logic configured to generate a free blocks list that excludes the kernel page identified in the bad pages list.
35. The system of claim 28, wherein the logic configured to retire the kernel pages corresponding to the respective failed codeword addresses comprises: logic configured to exclude the kernel pages identified in the bad pages list from allocated DRAM.
36. The system of claim 28, embodied in a portable computing device.

1. A windshield wiper arm assembly for wiping a windshield of a motor vehicle comprising:
a wiper linkage head having a bore formed therein for being connected to a rotatable wiper-drive shaft;
a wiper arm coupled to the wiper linkage head through a pivot pin allowing pivoting movement of the wiper arm with respect to the wiper linkage head between a stable windshield-engaged position and a stable windshield-disengaged position; and
a beam compression spring for biasing the wiper arm and the wiper linkage head between the stable windshield-engaged position and the stable windshield-disengaged position.
2. The assembly of claim 1 further comprising:
the beam compression spring integrally formed with one of the wiper arm and the wiper linkage head.
3. The assembly of claim 1 further comprising:
the beam compression spring integrally formed with the wiper arm.
4. The assembly of claim 1 further comprising:
the beam compression spring attachable to the wiper arm.
5. The assembly of claim 1 further comprising:
the beam compression spring formed of a composite pultruded material.
6. The assembly of claim I further comprising:
the beam compression spring integrally stamped from a metal material forming the wiper arm.
7. The assembly of claim 1 further comprising:
the beam compression spring for a windshield wiper including a cross-woven elongate tri-axial glass fiber sock bathed in a thermoset resin and cured in a heated pultrusion die to form a pultruded elongate strip.
8. The assembly of claim 7 further comprising:
the pultruded elongate strip overmolded with thermoplastic extruded cylindrical bearing ends on opposite sides.
9. The assembly of claim 7 further comprising:
the elongate strip cut transversely to form a pultruded beam compression spring of a desired width having overmolded cylindrical bearing ends and cross-woven glass fibers oriented axially between the bearing ends at an angle of between approximately 0\xb0 and approximately 30\xb0, inclusive.
10. A process for assembling a windshield wiper arm for wiping a windshield of a motor vehicle comprising the steps of:
forming a wiper linkage head having a bore for being connected to a rotatable wiper-drive shaft;
coupling a wiper arm to the wiper linkage head through a pivot pin allowing pivoting movement of the wiper arm with respect to the wiper linkage head between a stable windshield-engaged position and a stable windshield-disengaged position; and
biasing the wiper arm and the wiper linkage head with a beam compression spring between the stable windshield-engaged position and the stable windshield-disengaged position.
11. The process of claim 10 further comprising the step of:
integrally forming the beam compression spring with one of the wiper arm and the wiper linkage head.
12. The process of claim 10 further comprising the step of:
integrally forming the beam compression spring with the wiper arm.
13. The process of claim 10 further comprising the step of:
attaching the beam compression spring to the wiper arm.
14. The process of claim 10 further comprising the step of:
forming the beam compression spring of a composite pultruded material.
15. The process of claim 10 further comprising the step of:
integrally stamping the beam compression spring from a metal material forming the wiper arm.
16. The process of claim 10, wherein the beam compression spring further comprising the steps of:
cross-weaving an elongate tri-axial glass fiber sock;
bathing the elongate cross-woven sock in a thermoset resin; and
curing the bathed cross-woven sock in a heated pultrusion die to form a pultruded elongate strip.
17. The process of claim 16 further comprising the step of:
overmolding thermoplastic extruded cylindrical bearing ends on opposite sides of the pultruded elongate strip.
18. The process of claim 16 further comprising the step of:
cutting the elongate strip transversely to form a pultruded beam compression spring of a desired width having overmolded cylindrical bearing ends and cross-woven glass fibers oriented axially between the bearing ends at an angle of between approximately 0\xb0 and approximately 30\xb0, inclusive.
19. A process for fabricating a beam compression spring for a windshield wiper arm assembly comprising the steps of
cross-weaving an elongate tri-axial glass fiber sock;
bathing the elongate cross-woven sock in a thermoset resin; and
curing the bathed cross-woven sock in a heated pultrusion die to form a pultruded elongate strip.
20. The process of claim 19 further comprising the step of
overmolding thermoplastic extruded cylindrical bearing ends on opposite sides of the pultruded elongate strip.
21. The process of claim 20 further comprising the step of:
cutting the elongate strip transversely to form a pultruded beam compression spring of a desired width having overmolded cylindrical bearing ends and cross-woven glass fibers oriented axially between the bearing ends at an angle of between approximately 0\xb0 and approximately 30\xb0, inclusive.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method comprising the steps of:
inserting into soil an insect bait station, said bait station comprising:
a screw-shaped body member and a top member, said top member comprising a flange extending radially outwardly from said screw-shaped body member and also defining an opening to said toxicantbait receiving chamber; and
a sealing member for sealing said opening defined by said top member, said sealing member fitting flush with said flange, said sealing member bearing identifying indicia;

entering into an electronic data entrystorage device the identifying indicia for said insect bait station; and
entering into said electronic data entrystorage device information about the location of said insect bait station, such that said location information is associated with said identifying indicia.
2. A method comprising the steps of:
inserting into soil an insect bait station bearing identifying indicia, said bait station comprising:
a body member defining a hollow bait receiving chamber; and
a bait receiving bracket disposed in said bait receiving chamber, said bait receiving bracket being adapted to receive and retain an elongate bait member in an installation position, and further being adapted such that if said elongate bait member is at least partially consumed by an insect in said bait receiving chamber, said elongate bait member is no longer retained by said bait receiving bracket in said installation position;
entering into an electronic data entrystorage device the identifying indicia for said insect bait station; and
entering into said electronic data entrystorage device information about the location of said insect bait station, such that said location information is associated with said identifying indicia.