All The Claims

1. A method for operating a drive train (1) in a motor vehicle with a dual mass flywheel (9) driven by an internal combustion engine (2) via a crankshaft (3) and at least a transmission input shaft (5) of a transmission (6) that can be coupled with an output part (7) of the dual mass flywheel (9), comprising:
effecting a hysteresis-laden damping device (8) between an input part (4) and the output part (7);
influencing, using the hysteresis-laden damping device, engine torque output from the internal combustion engine (2) and load torque transmitted to the at least a transmission input shaft (5) through a hysteresis characteristic;
constantly determining rotation speeds of the input part and of the output part; and
determining in real time depending on a differential angle determined from the rotation speeds between the input part (4) and the output part (7) and from characteristic numbers of the damping device (8), a characteristic disturbance torque for influencing at least the load torque, wherein the characteristic numbers at least partially result from stiffness and friction behavior of the damping device.
2. The method according to claim 1, further comprising correcting the load torque by means of the characteristic disturbance torque.
3. The method according to claim 2, further comprising controlling the transmission (6) depending on the load torque corrected by means of the characteristic disturbance torque.
4. The method according to claim 1, further comprising calculating the characteristic disturbance torque for respective differential angles in different respective ways depending on at least a portion of the characteristic numbers that change proportionally with a rotation speed of the dual mass flywheel.
5. The method according to claim 4, further comprising:
providing several differential angle areas (14, 15, 16, and 17); and,
determining the characteristic disturbance torque in the several different angle areas respectively according to a same correlation of the characteristic numbers depending on the rotation speeds.
6. The method according to claim 5, wherein characteristic numbers of the damping device (8) are at least stiffness of an arc spring (12), with windings supported radially outside, acting between input- and output part (4, 7), moment of friction acting between input- and output part (4, 7) and moments of inertia of flywheel masses assigned to the input- and output part (4, 7).
7. The method according to claim 6, wherein the first differential angle area (14) comprises an activation area of the arc spring (12).
8. The method according to claim 6, further comprising determining the characteristic disturbance torque for the second differential angle area (15) without the consideration of the windings of the arc spring (12) going solid.
9. The method according to claim 6, further comprising determining the characteristic disturbance torque for the third differential angle area (16) whilst considering the windings of the arc spring (12) partially going solid.
10. The method according to claim 6, further comprising determining the characteristic disturbance torque for the fourth differential angle area (17) whilst considering the windings of the arc spring (12) fully going solid.
11. The method according to claim 6, wherein the first differential angle area (14) comprises an activation area of the arc spring (12), the method further comprising:
determining the characteristic disturbance torque for the second differential angle area (15) without the consideration of the windings of the arc spring (12) going solid;
determining the characteristic disturbance torque for the third differential angle area (16) whilst considering the windings of the arc spring (12) partially going solid; and,
determining the characteristic disturbance torque for the fourth differential angle area (17) whilst considering the windings of the arc spring (12) fully going solid.
12. The method according to claim 11, wherein the first differential angle area (14) is smaller than 30\xb0, the second differential angle area (15) lies between 20\xb0 and 50\xb0, the third differential angle area (16) lies between 40\xb0 and 70\xb0 and the fourth differential angle area (17) is greater than 60\xb0.
13. The method according to claim 11, further comprising determining the characteristic disturbance torque of at least one of the differential angle area (14, 15, 16, 17) dependent on a deflection of the arc spring (12) for a full hysteresis loop by which all the windings of the arc spring (12) are laid out in one direction and partial hysteresis loops (19), by which the sign of the differential angle changes, whereas all the windings are not yet deflected in one direction.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for performing a quantum error correction comprising:
performing an error correction on each of a plurality of qubit sets to restore a desired basis state of the qubit set, each qubit set corresponding to an associated logical qubit of a plurality of logical qubits;
recording a number of corrected qubits at each of the plurality of qubit sets;
determining a first set of the plurality of logical qubits having a first state and a second set of the plurality of logical qubits having a second state; and
correcting one of the first set of logical qubits and the second set of logical qubits according to the recorded numbers of corrected qubits.
2. The method of claim 1, wherein correcting a plurality of logical qubits according to the recorded numbers of corrected qubits comprises:
assigning a weight to each logical qubit according to the recorded number of corrected qubits at its corresponding qubit set and an associated type of error corrected at each corrected qubit;
ranking the plurality of logical qubits by weight; and
correcting at least one logical qubit having the highest weight.
3. The method of claim 2, wherein assigning a weight to each logical qubit comprises computing the weight as a function of a probability of that the corrected logical qubit is in the wrong state given a number and type of corrections of qubits within the logical qubit and a known likelihood of each type of error.
4. The method of claim 1, wherein correcting a plurality of logical qubits according to the recorded numbers of corrected qubits comprises selecting at least one of the first set of logical qubits and the second set of logical qubits according to a set of logical rules, at least one of the logical rules evaluating a number of corrected qubits recorded at one of the qubit sets.
5. The method of claim 1, wherein the plurality of qubits sets each contain three qubits, and the set of logical rules comprises correcting one of the first and second sets of logical qubits that contains only one logical qubit unless the qubit set associated with the one logical qubit contained no corrected qubits and each of the remaining two qubit sets contained a corrected qubit.
6. The method of claim 1, the plurality of logical qubits comprising a first set of first-level logical qubits of a plurality of sets of first-level logical qubits, the method further comprising:
recording a number of corrected first-level logical qubits at each set of first-level logical qubits, each set of first-level logical qubits corresponding to an associated second-level qubit;
determining a first set of second-level logical qubits having a first state and a second set of second-level logical qubits having a second state;
correcting one of the first set of second-level logical qubits and the second set of second-level logical qubits according to the recorded numbers of corrected first-level logical qubits.
7. The method of claim 1, wherein determining a first set of the plurality of logical qubits having a first state and a second set of the plurality of logical qubits having a second state comprises entangling a qubit from each qubit set with at least one of a set of ancillary qubits that are not part of the plurality of qubit sets and measuring each of the set of ancillary qubits.
8. The method of claim 1, wherein performing an error correction on a qubit set of the plurality of qubit sets comprises:
determining a first set of qubits from a plurality of qubits in the qubit set having a first state and a second set of qubits from the plurality of qubits having a second state; and
correcting the one of the first set of qubits and the second set of qubits having fewer qubits.
9. A system for storing a quantum bit of information, the system comprising:
a quantum storage system comprising a plurality of physical structures configured to collectively store a quantum bit of interest as a plurality of qubits; and
a system control comprising:
an error correction component configured to perform an error correction on each of a plurality of qubit sets formed from the plurality of qubits, the qubit sets corresponding to respective logical qubits of a plurality of logical qubits; and
a measurement arbitration component that records a number and type of errors at each of the plurality of qubit sets and an associated type of each correction, determines a plurality of sets of logical qubits having respective associated states and corrects one of the plurality of sets of logical qubits according to the recorded numbers of corrected qubits and the recorded types of corrections associated with the logical qubits comprising each of the plurality of sets.
10. The system of claim 9, the system control further comprising a storage interface configured to allow the control system to alter respective energy states of qubits from the plurality of qubit sets stored within the plurality of physical structures.
11. The system of claim 9, wherein the plurality of physical structures comprises a plurality of resonators and a plurality of qubit cells, each of the plurality of resonators being selectively coupled to at least one of the plurality of qubit cells such that quantum information can be passed freely among the plurality of resonators and the plurality of qubit cells.
12. The system of claim 9, wherein the measurement arbitration component corrects one of the plurality of sets of logical qubits according to a weighted voting algorithm, each of a plurality of weights in the weighted voting algorithm being a function of a recorded number of corrected qubits at an associated qubit set, and a weight associated with each of the plurality of sets of logical qubits comprising a linear combination of the weights associated with the logical qubits comprising the set.
13. The system of claim 9, wherein the measurement arbitration component corrects one of the plurality of sets of logical qubits according to a set of logical rules, at least one of the logical rules evaluating a number of corrected qubits recorded at one of the qubit sets.
14. The system of claim 13, wherein the plurality of qubits sets comprises three qubit sets, each containing three qubits, and the set of logical rules comprises correcting a one of first and second sets of the plurality of sets of logical qubits that contains only one logical qubit unless the qubit set associated with the one logical qubit contained no corrected qubits and each of the two qubit sets associated with the other of the first and second sets of logical qubits contained a corrected qubit.
15. The system of claim 9, the plurality of logical qubits comprising a first set of first-level logical qubits of a plurality of sets of first-level logical qubits, and the measurement arbitration component further being configured to record a number of corrected first-level logical qubits at each set of first-level logical qubits, with each set of first-level logical qubits corresponding to an associated second-level qubit, determine a first set of second-level logical qubits having a first state and a second set of second-level logical qubits having a second state, and correct one of the first set of second-level logical qubits and the second set of second-level logical qubits according to the recorded numbers of corrected first-level logical qubits.
16. The system of claim 9, wherein the measurement arbitration component determines a first set of the plurality of logical qubits having a first state and a second set of the plurality of logical qubits having a second state by entangling a qubit from each qubit set with at least one of a set of ancillary qubits that are not part of the plurality of qubit sets and measuring each of the set of ancillary qubits.
17. The system of claim 9, wherein the error correction component performs an error correction on a qubit set of the plurality of qubit sets by determining a first set of qubits from a plurality of qubits in the qubit set having a first state and a second set of qubits from the plurality of qubits having a second state and correcting the one of the first set of qubits and the second set of qubits having fewer qubits.
18. A method for quantum error correction comprising:
performing a first error correction on each of a plurality of qubit sets, each qubit set representing an associated logical qubit of a plurality of logical qubits;
determining a first set of the plurality of logical qubits having a first state and a second set of the plurality of logical qubits having a second state, the first set of logical qubits being larger than the second set; and
correcting the first set of logical qubits to the second state.
19. The method of claim 18, wherein determining a first set of logical qubits having a first state and a second set of logical qubits having a second state comprises entangling a qubit from each qubit set with at least one of a set of ancillary qubits that are not part of the plurality of qubit sets and measuring each of the set of ancillary qubits.
20. The method of claim 18, further comprising recording a number of qubits corrected in each qubit set during the first error correction.

1. A flexible circuit board for producing a flexible-rigid circuit board composite made of at least one flexible circuit board and at least one rigid circuit board, the at least one flexible circuit board having at least one first planar segment which interacts in the installed state as intended with at least one second planar segment of the at least one rigid circuit board, wherein the at least one first planar segment comprises at least one flexible connecting element, which is elastically connected to a face of the at least one first planar segment.
2. The flexible circuit board according to claim 1, wherein the at least one flexible connecting element is embedded within the face of the at least one first planar segment.
3. The flexible circuit board according to claim 1, wherein the at least one flexible connecting element is connected by means of elastic webs to the face of the at least one first planar segment.
4. The flexible circuit board according to claim 1, wherein at least one opening is provided in the at least one first planar segment, through which, in the intended installed state of the at least one flexible and rigid circuit boards, one or more components of the at least one rigid circuit board is or are accessible.
5. The flexible circuit board according to claim 1, wherein the flexible connecting element directly adjoins the opening, and the flexible connecting element has an indentation, which is provided in the intended installed state as a contacting zone between the flexible circuit board and the rigid circuit board.
6. A circuit board arrangement having at least one flexible circuit board according to claim 1, wherein the at least one flexible circuit board is clamped in a frame.
7. The circuit board arrangement according to claim 6, wherein a plurality of first planar segments is provided in a matrix-type arrangement, which first planar segments each comprise at least one flexible connecting element, which are each elastically connected to a face of the at least one first planar segment.
8. A flexible-rigid circuit board composite made of at least one flexible circuit board according to claim 1, and at least one rigid circuit board, the at least one flexible circuit board having at least one first planar segment, which interacts as intended with at least one second planar segment of the at least one rigid circuit board, wherein the at least one first planar segment comprises at least one flexible connecting element, which is elastically connected to a face of the at least one first planar segment.
9. The flexible-rigid circuit board composite according to claim 8, wherein at least one opening is provided in the at least one first planar segment, through which one or more components of the at least one rigid circuit board is or are accessible.
10. The flexible-rigid circuit board composite according to claim 8, wherein a contacting zone comprising a soldering zone is provided, the contacting zone being arranged on an interface between the at least one flexible connecting element and the at least one opening.
11. The flexible-rigid circuit board composite according to claim 8, wherein the at least one flexible circuit board and the at least one rigid circuit board are formed by isolating planar segments of a flexible and rigid circuit board arrangement respectively.
12. A method for producing a flexible-rigid circuit board composite between a flexible circuit board according to claim 1, and a rigid circuit board, having at least one flexible circuit board, the method comprising the following steps:
providing a flexible circuit board arrangement and a rigid circuit board arrangement, the flexible circuit board arrangement having at least one planar segment, which has a flexible connecting element, which is elastically connected to a face of the at least one first planar segment;
bringing the flexible and rigid circuit board arrangements into contact with one another with a pre-alignment of the at least one first planar segment of the flexible circuit board arrangement in relation to at least one second planar segment of the rigid circuit board arrangement;
finely aligning the at least one first planar segment in relation to the at least one second planar segment by adapting a position of the flexible connecting element at least parallel to or within the at least one first planar segment;
connecting the at least one first planar segment to the at least one second planar segment; and
forming at least one circuit board composite by cutting the connected first and second planar segments out of the connected circuit board arrangements.
13. The method according to claim 12, wherein the at least one second planar segment has one or more components comprising SMD components, which are prepared on their contact regions for a soldered connection, and the connection of the first and second planar segments occurs in a processing step with a connection of the one or more components to contact faces of the at least one second planar segment.
14. The method according to claim 12, wherein the at least one first planar segment is pre-equipped with one or more components comprising SMD components, before the flexible and rigid circuit board arrangements are brought into contact with one another.
15. A device for carrying out the method according to claim 12, for producing a flexible-rigid circuit board composite between a flexible circuit board according claim 1, and a rigid circuit board, having at least one flexible circuit board, wherein the device is implemented so that at least the following steps can be carried out:
after a pre-alignment of the at least one first planar segment of the flexible circuit board arrangement in relation to at least one second planar segment of the rigid circuit board arrangement; and
using a vacuum suction unit, finely aligning the at least one first planar segment in relation to the at least one second planar segment by adapting a position of the flexible connecting element at least parallel to or within the at least one first planar segment.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A data management system which communicates with one or more applications and stores files accessed by the applications, the server comprising:
a processor; and
a memory storing instructions that when executed by the processor, cause the processor to perform acts including:
monitoring a plurality of events from the one or more applications;
analyzing the events according to the one or more applications and the files associated with the events;
generating an application template from the events; and
analyzing the application template according to a file type of one or more of the files.
2. The data management system according to claim 1, wherein:
the memory stores instructions that when executed by the processor, cause the processor to perform acts further including:
determining whether the generated application template matches with a previously generated application template; and
when the generated application template matches the previously generated application template, determining at least one data management action for each file associated with the generated application template.
3. The data management system according to claim 2, wherein:
the memory stores instructions that when executed by the processor, cause the processor to perform acts further including:
executing the at least one data management action for each file associated with the generated application template.
4. The data management system according to claim 3, wherein:
for each file, the at least one data management action includes at least one of migrating data of the respective file, archiving the data of the respective file, and deleting the data of the respective file.
5. The data management system according to claim 4, wherein:
for each file, the at least one data management action includes a timing for execution thereof.
6. The data management system according to claim 1, further comprising:
a storage volume containing metadata of the files, and wherein the server is connected to a storage area network which stores data of each of the files.
7. The data management system according to claim 6, further comprising:
a storage volume containing metadata of the files; and
a storage device containing the data of the files.
8. The data management system according to claim 2, wherein:
the memory stores the plurality of events in a global event history table for a predetermined period of time, stores the plurality of events for each application and for each file in an application event history table, stores the file type of the one or more of the files and event details in sequence in the generated application template, stores the file type and an identifier of the one or more applications in a file type application access table, stores the file type and the at least one data management action in a data management table, and stores, when the generated application template matches the previously generated application template, each file associated with the generated application template and the at least one data management action in correspondence with a time of execution in a pending data management table.
9. A data management system which communicates with one or more applications and stores files accessed by the applications, the server comprising:
a processor; and
a memory storing instructions that when executed by the processor, cause the processor to perform acts including:
monitoring a plurality of events from the one or more applications;
analyzing the events according to the one or more applications and the files associated with the events;
generating a set of application templates from the events;
correlating file types of one or more of the files with applications from the set of application templates; and
generating a workflow from the set of application templates according to the correlation of the file types thereof.
10. The data management system according to claim 9, wherein:
the memory stores instructions that when executed by the processor, cause the processor to perform acts further including:
generating a new application template from the events;
determining whether the new application template matches with the set of generated application templates; and
when the new application template matches with the set of generated application templates:
creating a workflow file set, for each file associated with the new application template,
determining whether the workflow file set matches with the workflow from the set of application templates, and
when the workflow file set matches with the workflow from the set of application templates:
verifying that all applications of the workflow file set have completed, and
determining at least one data management action for each file associated with the workflow file set.
11. The data management system according to claim 10, wherein:
the memory stores instructions that when executed by the processor, cause the processor to perform acts further including:
executing the at least one data management action for each file associated with the workflow file set.
12. The data management system according to claim 11, wherein:
for each file, the at least one data management action includes at least one of migrating data of the respective file, archiving the data of the respective file, and deleting the data of the respective file.
13. The data management system according to claim 12, wherein:
for each file, the at least one data management action includes a timing for execution thereof.
14. The data management system according to claim 9, further comprising:
a storage volume containing metadata of the files, and
wherein the server is connected to a storage area network which stores data of the files.
15. The data management system according to claim 9, further comprising:
a storage volume containing metadata of the files; and
a storage device containing data of the files.
16. The data management system according to claim 10, wherein:
when the new application template does not match with the set of generated application templates:
determining that the files of the new application template are associated with a new workflow.
17. The data management system according to claim 1, further comprising:
a metadata server including a storage volume containing metadata of the files; and
one or more data servers connected to the metadata server, each of the data servers including a data volume storing data of one or more of the files,
wherein the metadata server and the one or more data servers are connected over a network, and
wherein the events from the one or more applications are received by the metadata server over the network.
18. The data management system according to claim 1, further comprising:
a metadata server including a storage volume containing metadata of the files; and
one or more data servers connected to the metadata server, each of the data servers including a data volume storing data of one or more of the files,
wherein the events from the one or more applications are received by the metadata server over a first network, and
wherein the metadata server and the one or more data servers are connected over a network.
19. The server according to claim 9, further comprising:
a metadata server including a storage volume containing metadata of the files; and
one or more data servers connected to the metadata server, each of the data servers including a data volume storing data of one or more of the files,
wherein the metadata server and the one or more data servers are connected over a network, and
wherein the events from the one or more applications are received by the metadata server over the network.
20. The server according to claim 9, further comprising:
a metadata server including a storage volume containing metadata of the files; and
one or more data servers connected to the metadata server, each of the data servers including a data volume storing data of one or more of the files,
wherein the events from the one or more applications are received by the metadata server over a first network, and
wherein the metadata server and the one or more data servers are connected over a network.