All The Claims

1. A III-N semiconductor device comprising:
a gate;
a nitride channel layer including a first channel region beneath the gate, and two channel access regions on opposite sides of the first channel region, the composition of the nitride channel layer being selected from the group consisting of nitrides of gallium, indium and aluminum, and combinations thereof;
an AlXN layer adjacent the channel layer, wherein X is selected from the group consisting of gallium, indium or their combination; and
an n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions, but not in the area adjacent to the first channel region;
the concentration of Al in the AlXN layer, the AlXN layer thickness, and the n-doping concentration in the n-doped GaN layer being selected to induce a 2DEG charge in the channel access regions adjacent the AlXN layer without inducing any substantial 2DEG charge in the first channel region, so that the channel is not conductive in the absence of a switching voltage applied to the gate region, but can readily become conductive when a switching voltage greater than a threshold voltage is applied to the gate region.
2. The III-N semiconductor device of claim 1 having a substrate and an additional nitride layer between the substrate and the nitride channel layer, the additional nitride layer being selected from the group consisting of nitrides of gallium, indium and aluminum and combinations thereof, wherein the channel layer is GaN and the additional nitride layer is AlzGaN, where z is between a finite value greater than 0, and 1.
3. The III-N semiconductor device of claim 1 wherein the n-doped GaN layer is doped with silicon.
4. The III-N semiconductor device of claim 3 wherein the switching voltage is greater than 2.5 volts and a current flows through the channel of at least 300 mA per mm of gate width when the channel is conductive.
5. The III-N semiconductor device of claim 3 wherein the switching voltage is greater than 2 volts and a current flows through the channel of at least 200 mA per mm of gate width when the channel is conductive.
6. The III-N semiconductor device of claim 5 wherein the current through the channel when the channel is conductive is at least 10,000 times the current when the channel is not conductive.
7. A III-N semiconductor device comprising:
a nitride channel layer including a first channel region beneath a gate region, and two channel access regions on opposite sides of the first channel region, the composition of the nitride channel layer being selected from the group consisting of nitrides of gallium, indium and aluminum, and combinations thereof;
a first AlXN layer adjacent the channel layer wherein X is selected from the group consisting of gallium, indium or their combination;
a second AlXN layer adjacent the first AlXN layer in the areas adjacent to the channel access regions, but not in the area adjacent to the first channel region, the first AlXN layer having a substantially higher concentration of Al than the second AlXN layer;
the concentration of Al in each of the first and second AlXN layers, respectively, and their respective thicknesses being selected to induce a 2DEG charge in channel access regions adjacent the first AlXN layer without inducing any substantial 2DEG charge in the first channel region, so that the channel is not conductive in the absence of a switching voltage applied to the gate region, but is conductive when a switching voltage greater than a threshold voltage is applied to the gate region.
8. The III-N semiconductor device of claim 7 wherein the concentration of Al in the first AlXN layer is at least twice the concentration of Al in the second AlXN layer.
9. The III-N semiconductor device of claim 7 wherein the second AlXN layer is n-doped.
10. The III-N semiconductor device of claim 9 wherein the n-dopant is Si.
11. The III-N semiconductor device of claim 7 having a substrate and an additional nitride layer between the substrate and the nitride channel layer, the additional nitride layer being selected from the group consisting of nitrides of gallium, indium and aluminum and combinations thereof, wherein the channel layer is GaN and the additional nitride layer is AlzGaN, where z is between a finite value greater than 0, and 1.
12. The III-N semiconductor device of claim 11 wherein the additional nitride layer is AlXN.
13. A III-N semiconductor device comprising:
a nitride channel layer including a first channel region beneath a gate region, and two channel access regions on opposite sides of the first channel region, the composition of the nitride channel layer being selected from the group consisting of nitrides of gallium, indium and aluminum, and combinations thereof;
a first AlXN layer adjacent the channel layer wherein X is selected from the group consisting of gallium, indium or their combination;
a second AlXN layer adjacent the first AlXN layer, the first AlXN layer having a substantially higher concentration of Al than the second AlXN layer;
a gate region formed in the second AlXN layer, the gate region comprising an aperture in the second AlXN layer and an insulator covering at least part of the aperture; and
a conductive gate contact atop the insulator and insulated from the first and second AlXN layers; wherein
the concentration of Al in each of the first and second AlXN layers, respectively, and their respective thicknesses being selected to induce a 2DEG charge in channel access regions adjacent the first AlXN layer without inducing any substantial 2DEG charge in the first channel region, so that the channel is not conductive in the absence of a switching voltage applied to the gate region, but is conductive when a switching voltage greater than a threshold voltage is applied to the gate region.
14. The III-N device of claim 13 wherein the aperture has slanted sides.
15. The III-N device of claim 13 wherein conductive contacts are formed to make source and drains electrical contacts with opposing ends of the channel layer.
16. The III-N device of claim 15 wherein a passivating layer is applied to the top surface of the device, including at least part of the gate, source and drain contacts.
17. A GaN semiconductor device comprising:
a GaN channel layer, including a first channel region beneath a gate region, and two channel access regions on opposite sides of the first channel region;
a layer of AlxGaN on the channel layer, where x is between about 0.05 and 0.3;
an n-doped GaN layer adjacent the AlxGaN layer in the areas adjacent to the channel access regions, but not in the area adjacent to the first channel region;
the concentration of Al in the AlxGaN layer, the AlxGaN layer thickness and the n-doping concentration in the n-doped GaN layer being selected to induce a 2DEG charge in channel access regions adjacent the AlxGaN layer without inducing any substantial 2DEG charge in the first channel region, so that the channel is not conductive in the absence of a switching voltage applied to the gate region, but can readily become conductive when a switching voltage greater than a threshold voltage is applied to the gate region.
18. The GaN semiconductor device of claim 17 having an additional SiN layer on top of the n-doped GaN layer.
19. The GaN semiconductor device of claim 17 wherein the n-doped GaN layer is doped with silicon.
20. The GaN semiconductor device of claim 19 wherein the n-doped GaN layer is delta-doped.
21. The GaN semiconductor device of claim 17 wherein the substrate is SiC.
22. The GaN semiconductor device of claim 17 having an AlzGaN buffer layer between the GaN channel layer and the substrate, where z is between 1 and a finite value greater than 0, and wherein x is between 0.05 and 0.4.
23. The GaN semiconductor device of claim 17 having an additional AlXN layer on top of the n-doped GaN layer, wherein X is selected from the group consisting of gallium, indium or their combination.
24. The GaN semiconductor device of claim 23 having an additional SiN layer on top of the additional AlXN layer.
25. A III-N semiconductor device comprising:
a gate in a recessed gate region;
a nitride channel layer including a first channel region beneath the recessed gate region, the composition of the nitride channel layer being selected from the group consisting of nitrides of gallium, indium and aluminum, and combinations thereof;
an AlXN layer adjacent the channel layer wherein X is selected from the group consisting of gallium, indium or their combination;
a III-N layer adjacent the AlXN layer and surrounding the recessed gate region, the III-N layer including two channel access regions on opposite sides of the first channel region respectively connected to a source and a drain,
an AlmYN layer adjacent to the III-N layer and surrounding the recessed gate region, wherein Y is selected from the group consisting of gallium, indium or their combination, the concentration m of Al in the AlmYN layer and its thickness being selected to induce a 2DEG charge in the two channel access regions,
the first channel region being non-conductive in the absence of a switching voltage applied to the gate, but being conductive in the presence of a gate voltage greater than a threshold voltage, creating a 2DEG region in the first channel region and through a gate-induced, substantially vertical conducting region through the AlXN layer, thereby completing the conduction path through the access regions from the source to the drain.
26. The III-N semiconductor device of claim 25 wherein the III-N layer or the AlmYN layer is n-doped.
27. The III-N semiconductor device of claim 26 wherein the n-dopant is Si.
28. The III-N semiconductor device of claim 25 having an additional nitride layer between the substrate and the nitride channel layer, wherein the channel layer is GaN.
29. The III-N semiconductor device of claim 28 wherein the additional nitride layer is AlXN where X is selected from the group consisting of gallium, indium, aluminum and combinations thereof.
30. The III-N semiconductor device of claim 28 wherein the additional nitride layer is AlzGaN, where z is between a finite value greater than 0, and 1.
31. The III-N semiconductor device of claim 25 wherein the conduction path through the AlXN layer is created by tunneling.
32. The III-N semiconductor device of claim 25 wherein the conduction path through the AlXN layer is created by thermionic emission.
33. The III-N semiconductor device of claim 25 wherein the conduction path through the AlXN layer is created by both tunneling and thermionic emission.
34. The III-N semiconductor device of claim 25 wherein the conduction path is modulated by the switching voltage and runs along a side of and beneath the gate.
35. The III-N semiconductor device of claim 25 wherein the gate has a bottom and substantially vertical or tapered sides, whereby charge is modulated along both the sides and the bottom when the switching voltage is present.
36. The III-N semiconductor device of claim 25 where m is between about 0.1 to 0.3.
37. The III-N semiconductor device of claim 25 having an additional AlN layer between about 4-30 \u212b thick in between the AlmYN layer and the III-N layer.
38. The III-N semiconductor device of claim 37 having a threshold voltage of at least 1 volt, less than 20 ohm-mm on resistance and current carrying capability between source and drain when the device is on of greater than 400 mAmm.
39. The III-N semiconductor device of claim 37 having a threshold voltage of at least 1.5 volts, less than 15-ohm-mm on resistance and current carrying capability between the source and the drain when the device is on of greater than 600 mAmm.
40. The III-N semiconductor device of claim 25 having an additional III-N layer adjacent to the AlmYN layer, the additional III-N layer also being recessed in the gate region.
41. The III-N semiconductor device of claim 40 wherein the additional III-N layer is n-doped.
42. The III-N semiconductor device of claim 25 wherein the recessed gate includes a gate insulator composed substantially of a material selected from the group consisting of SiN, AlSiN, SiO2, HfO2, ZrO2, Ta2O5 or a combination thereof.
43. The III-N semiconductor device of claim 42 wherein at least one of the insulating materials is a high-K dielectric.
44. The III-N device of claim 42 further including an additional SiN layer on the AlmYN layer, the SiN layer being recessed with a tapered sidewall, the tapered sidewall further continuing through the AlmYN layer and the III-N layer, and a gate metal layer deposited in the recessed gate region over the gate insulator, a portion of the gate metal extending over the gate insulator on both sides.
45. The III-N device of claim 44 having an additional SiN passivation layer applied on top of the device and beneath the gate metal.
46. The III-N device of claim 45 having a field plate metal deposited on the SiN passivation layer, the field plate metal connected electrically either to the source or the gate contact.
47. A III-N transistor having a source, a drain and a gate, comprising:
a first layer of a first material including two 2DEG-containing channel access regions adjacent the gate, one coupled to the source and the other coupled to the drain;
a second layer of a second material having a channel region coupled between the two channel access regions and beneath the gate, wherein the channel region is depleted of conducting charge and is not conductive in the absence of a switching voltage being applied to the gate, but which comprises a 2DEG channel and becomes conductive when a switching voltage greater than a threshold voltage is applied to the gate, thereby completing a conductive path between the source and the drain.
48. The transistor of claim 47, wherein when the switching voltage is applied to the gate, the two channel access regions are connected to the channel region via substantially vertical conducting regions induced by the gate voltage.
49. The III-N semiconductor device of claim 25 wherein the nitride channel layer contains a second pair of channel access regions respectively underneath the two channel access regions in the III-N layer.
50. The III-N semiconductor device of claim 49 where the nitride channel layer makes electrical contact to the source and drain.
51. The III-N semiconductor device of claim 49 having an additional AlN layer between about 4 and 30 \u212b thick between the nitride channel layer and the AlXN layer.
52. The III-N semiconductor device of claim 25 wherein the nitride channel layer, the AlXN layer, the III-N layer, and the AlmYN layer are all oriented in a nonpolar direction or in a Ga-terminated semipolar direction.
53. The III-N semiconductor device of claim 52 wherein the III-N layer or the AlmYN layer is n-doped.
54. The III-N semiconductor device of claim 53 wherein the n-dopant is Si.
55. A III-N semiconductor device comprising:
a nitride channel layer including a first channel region beneath a recessed gate region, the composition of the nitride channel layer being selected from the group consisting of nitrides of gallium, indium and aluminum, and combinations thereof;
a III-N layer adjacent the nitride channel layer and surrounding the recessed gate region, the III-N layer including two channel access regions on opposite sides of the first channel region and respectively connected to a source and a drain,
an AlmYN layer adjacent to the III-N layer and surrounding the recessed gate region, wherein Y is selected from the group consisting of gallium, indium or their combination,
the first channel region being non-conductive in the absence of a switching voltage applied to the gate, but being conductive in the presence of a switching voltage greater than a threshold voltage applied to the gate, creating a 2DEG region in the first channel region and through a gate-induced, substantially vertical conducting region through the III-N layer, thereby completing the conduction path through the two channel access regions, the first channel region and the vertical conducting region from the source to the drain.
56. The device of claim 55 having an additional AlN layer between about 4 and 30 \u212b thick between the III-N layer and the AlmYN layer, and wherein the concentration m of Al in the AlmYN layer and its thickness are selected to induce a 2DEG charge in the two channel access regions.
57. The III-N semiconductor device of claim 25 wherein the thickness of the additional III-N layer is in the range of about 200 \u212b to 2000 \u212b.
58. The III-N semiconductor device of claim 41 wherein the thickness of the additional III-N layer is in the range of about 200 \u212b to 2000 \u212b.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A concurrent, multicast communication method for transmitting data packets over a network of interconnected nodes, comprising:
multicasting a message from a source node to a receiver group;
unicasting a control message from a source node across a primary node to an ordering node for a designated multicast group or transmission, wherein said primary node aggregates messages from their subtrees and hence staggers the ordering process upward within the tree;
determining a binding sequence number for this message and a multicast to the receiver group; and
delivering messages at end hosts according to agreed-upon sequence numbers.
2. A method as recited in claim 1:
wherein said messages are delivered in an order agreed-upon by all hosts.
3. A method as recited in claim 1:
wherein each node i in an acknowledgment-free is labeled with a unique label l(i), which is the prefix of all children of i.
4. A method as recited in claim 1:
wherein, for each set of messages destined to a particular multicast group, or set of hosts, an ordering node is elected by virtue of being the node having label that is the longest common prefix among all node labels in the receiver set.
5. A method as recited in claim 4:
wherein each ordering node gathers sequence number bids set en route by primary nodes deciding on a globally valid number, and multicasts the respective message to the receiver set with a final and binding sequence number directive.
6. A concurrent, multicast communication method for transmitting data packets over a network of interconnected nodes, comprising:
multicasting a message from a source node to a receiver group;
unicasting a control message from a source node across a primary node to an ordering node for a designated multicast group or transmission, wherein said primary node aggregates messages from their subtrees and hence staggers the ordering process upward within the tree;
determining a binding sequence number for this message and a multicast to the receiver group; and
delivering messages at end hosts according to agreed-upon sequence numbers;
wherein said messages are delivered in an order agreed-upon by all hosts.
7. A method as recited in claim 6:
wherein each node i in an acknowledgment-tree is labeled with a unique label l(i), which is the prefix of all children of i.
8. A method as recited in claim 6:
wherein, for each set of messages destined to a particular multicast group, or set of hosts, an ordering node is elected by virtue of being the node having label that is the longest common prefix among all node labels in the receiver set.
9. A method as recited in claim 8:
wherein each ordering node gathers sequence number bids set en route by primary nodes deciding on a globally valid number, and multicasts the respective message to the receiver set with a final and binding sequence number directive.
10. A method as recited in claim 8:
wherein each node i in an acknowledgment-tree is labeled with a unique label 1(i), which is the prefix of all children of i.
11. A concurrent, multicast communication method for transmitting data packets over a network of interconnected nodes, comprising:
multicasting a message from a source node to a receiver group;
unicasting a control message from a source node across a primary node to an ordering node for a designated multicast group or transmission, wherein said primary node aggregates messages from their subtrees and hence staggers the ordering process upward within the tree;
determining a binding sequence number for this message and a multicast to the receiver group;
delivering messages at end hosts according to agreed-upon sequence numbers;
wherein said messages are delivered in an order agreed-upon by all hosts;
wherein, for each set of messages destined to a particular multicast group, or set of hosts, an ordering node is elected by virtue of being the node having label that is the longest common prefix among all node labels in the receiver set; and
wherein each ordering node gathers sequence number bids set en route by primary nodes deciding on a globally valid number, and multicasts the respective message to the receiver set with a final and binding sequence number directive.

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate of a first conductivity type;
a first active region provided in a surface of said semiconductor substrate and having a second conductivity type which is different from said first conductivity type;
a second active region provided in the surface of said semiconductor substrate at a distance from said first active region and having said second conductivity type;
a control electrode provided on the surface of said semiconductor substrate in a part interposed between said first and second active regions; and
a buried channel layer provided in said semiconductor substrate under said control electrode and having said second conductivity type, said buried channel layer being in contact with both of said first and second active regions;
said semiconductor substrate and said first active region constituting a photodiode which is part of a solid-state image sensor;
said control electrode and said first and second active regions constituting a transistor which is part of said solid-state image sensor; and
said buried channel layer having a lower impurity concentration than said first and second active regions.
2. The semiconductor device according to claim 1, further comprising
a third active region having said first conductivity type and provided in the surface of said first active region,
wherein said buried channel layer has a larger depth than said third active region from the surface of said semiconductor substrate.
3. The semiconductor device according to claim 1,
wherein said second active region is absent, and instead, said buried channel layer is extended also in the region where said second active region would reside if present.
4. The semiconductor device according to claim 1, further comprising
an element isolation insulating layer provided in the surface of said semiconductor substrate and having an edge extending along a periphery of said second active region,
wherein said second active region is provided in said semiconductor substrate with its said periphery spaced at a certain distance from said edge of said element isolation insulating layer.
5. The semiconductor device according to claim 1,
wherein said buried channel layer extends also in the part where said first active region is provided and overlaps said first active region, and
in said first active region and its vicinity, the depth of said buried channel layer from the surface of said semiconductor substrate at least reaches the depth of said first active region from the surface of said semiconductor substrate.
6. The semiconductor device according to claim 5,
wherein said buried channel layer extends also in the part where said second active region is provided and overlaps said second active region, and
in said second active region and its vicinity, said buried channel layer has a smaller depth from the surface of said semiconductor substrate than in said first active region and its vicinity.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An integrated device comprising:
a first circuit having an input and an output, the input of the first circuit configured to receive an input signal and provide a first signal on the output of the first circuit;
a second circuit having an input and an output, the input of the second circuit configured to receive the input signal and provide a second signal on the output of the second circuit; and
a third circuit having a first input configured to receive the first signal and a second input configured to receive the second signal, the third circuit configured to combine the first signal and the second signal into a modulator drive output signal provided on an output of the third circuit,
wherein the second signal is complementary to the first signal, and
wherein the third circuit comprises a current source and a resistor, the current source cooperating with the resister to provide a bias signal, the third circuit configured to combine the bias signal, and the first signal and the second signal into the modulator drive output signal provided on the output of the third circuit.
2. The integrated circuit of claim 1, wherein the input signal is a differential signal and the modulator drive output signal is a differential modulator drive output signal.
3. The integrated device of claim 1, wherein the input signal is a single-ended signal and the modulator drive output signal is a single-ended modulator drive output signal.
4. The integrated device of claim 1, wherein the first circuit cooperates with the third circuit, such that the first signal is a high-pass response of the input signal having a first cutoff frequency, and the second circuit cooperates with the first circuit and the third circuit, such that the second signal is a low-pass response of the input signal having a second cutoff frequency.
5. The integrated device of claim 4, wherein the first cutoff frequency is substantially equal to the second cutoff frequency.
6. The integrated circuit of claim 1, wherein the first signal has a first frequency response and the second signal has a second frequency response which does not overlap the first frequency response.
7. The integrated circuit of claim 1, wherein the first signal has a first amplitude and the second signal has a second amplitude substantially the same as the first amplitude.
8. The integrated device of claim 1, wherein the current source is a programmable current source, such that the bias signal is programmable.
9. The integrated device of claim 8, wherein the programmable current source is controlled by a digital communication interface.
10. The integrated device of claim 9, wherein the digital communication interface is a 3-wire Serial Peripheral Interface or a 4-wire Serial Peripheral Interface.
11. The integrated device of claim 1, wherein the modulator is an electro-absorption modulator.
12. The integrated device of claim 11, wherein the first, second and third circuits are one of a plurality of modulated drive circuits provided on the single substrate.
13. The integrated device of claim 1, wherein the modulator is a Mach-Zehnder modulator.
14. The integrated device of claim 1, wherein the first, second and third circuits are provided on a single substrate.
15. An integrated device comprising:
a first circuit having an input and an output, the input of the first circuit configured to receive an input signal and provide a first signal on the output of the first circuit;
a second circuit having an input and an output, the input of the second circuit configured to receive the input signal and provide a second signal on the output of the second circuit; and
a third circuit having a first input configured to receive the first signal and a second input configured to receive the second signal, the third circuit configured to combine the first signal and the second signal into a modulator drive output signal provided on an output of the third circuit,
wherein the second signal is complementary to the first signal,
wherein the input signal is a differential signal and the modulator drive output signal is a differential modulator drive output signal, and
wherein the differential modulator drive output signal includes a first differential modulator drive output signal and a second differential modulator drive output signal, the third circuit further comprising a first current source coupled to the first output signal and a second current source coupled to the second output signal, the first current source providing a first bias signal and the second current source providing a second bias signal, the first differential modulator drive output signal comprising the first bias signal and the second differential modulator drive output signal comprising the second bias signal.
16. The integrated device of claim 15, wherein the first current source is a first programmable current source and the second current source is a second programmable current source.
17. The integrated device of claim 16, wherein the first programmable current source and the second programmable current source are controlled via a digital communication interface.
18. The integrated device of claim 17, wherein the digital communication interface is a 3-wire Serial Peripheral Interface or a four-wire Serial Peripheral Interface.