All The Claims

1. A band gap reference circuit, comprising:
a first branch comprising a first transistor element and a first temperature dependent resistive element;
a second branch comprising a second transistor element having a size different from the first transistor element;
an output branch comprising an second temperature dependent resistive element, the second temperature dependent resistive element being coupled to an output terminal; and
a control element coupled to the first and second branch to control a current through the first and second branches;
wherein each of the first and second temperature dependent resistive elements, comprises a transistor, whose controlled section is arranged in a current path of the respective branch and is controlled such that it operates in its linear region of its characteristics,
wherein the first temperature dependent element comprises a first current mirror, the first current mirror comprising a first input transistor and a first mirror transistor, and
wherein the second temperature dependent resistive element comprises a second current mirror, the second current mirror comprising a second input transistor and a second mirror transistor.
2. The band gap reference circuit according to claim 1, wherein each control terminal of said first input transistor and said first mirror transistor is coupled to a terminal of the first input transistor.
3. The band gap reference circuit according to claim 1, wherein the first mirror transistor comprises a channel width, which is greater than a respective channel width of the first input transistor.
4. The band gap reference circuit according to claim 1, wherein each control terminal of both said second input transistor and said second mirror transistor is coupled to a terminal of the second input transistor.
5. The band gap reference circuit according to claim 1, wherein the second temperature dependent resistive element comprises a further current mirror, said further current mirror comprising a further input transistor and further mirror transistor, wherein the further input transistor is coupled to an input terminal of the second mirror transistor and each control terminal of both transistors of the further current mirror is coupled to a terminal of the second input transistor.
6. The band gap reference circuit according to claim 1, wherein said second temperature dependent resistive element comprises a plurality of current mirrors,
wherein each current mirror comprises an input transistor and a mirror transistor;
wherein each control terminal of both transistors is coupled to a first terminal of the respective input transistor; and
wherein a terminal of a current mirror transistor of at least one of the plurality of current mirrors is coupled to a second terminal of an input transistor of a subsequent current mirror.
7. The band gap reference circuit according to claim 1, wherein the respective mirror transistor comprises a channel width which is greater than a respective channel width of the respective input transistor.
8. The band gap reference circuit according to claim 1, wherein the transistor of the second temperature dependent resistive element comprises a channel length, said channel length being greater than a channel length of the transistor of the first temperature dependent resistive element.
9. The band gap reference circuit according to claim 1, wherein the output branch comprises a current transistor element comprising a temperature dependence opposite to the temperature dependence of said second temperature dependent resistive element.
10. The band gap reference circuit according to claim 1, wherein a node between the second temperature dependent resistive element and a ground terminal is coupled to a node between the first temperature dependent resistive element and the first transistor element.
11. The band gap reference circuit according to claim 1, wherein the control element comprises one of the following:
a comparator, whose inputs are coupled to the first and second branch, respectively;
a current mirror, comprising a third mirror transistor arranges in the first branch and an input transistor arranged in the second branch, and a fourth current mirror comprising an input transistor arranged in the first branch and a mirror transistor arranged in the second branch.
12. The band gap reference circuit according to claim 1, wherein the first and second transistor elements, each comprises at least one bipolar transistor, said at least one bipolar transistor comprising a negative proportional temperature dependency.
13. The band gap reference circuit according to claim 1, wherein the output branch comprises a transistor element, said transistor element arranged between the second temperature dependent element and a reference potential terminal with a control terminal of the third transistor element being coupled to the reference potential terminal.
14. The band gap reference circuit according to claim 13, wherein the transistor element of the output branch comprises a temperature dependency similar to the temperature dependency of the first transistor element.
15. The band gap reference circuit according to claim 1, wherein said first temperature dependent resistive element comprises a first current mirror, said first current mirror comprising a first input transistor and a first mirror transistor, wherein each control terminal of both said first input transistor and said first mirror transistor is coupled to a terminal of said first input transistor, wherein said controlled section of said first mirror transistor is directly connected in the current path of the first branch, and
wherein said second temperature dependent resistive element comprises a second current mirror, said second current mirror comprising a second input transistor and a second mirror transistor, wherein each control terminal of both said second input transistor and said second mirror transistor is coupled to a terminal of the second input transistor, wherein said controlled section of said second mirror transistor is directly connected in the current path of the output branch.
16. The band gap reference circuit according to claim 15, wherein each mirror transistor comprises a channel width, which is greater than a respective channel width of the corresponding input transistor.
17. The band gap reference circuit according to claim 1, wherein the current path of the first branch and the current path of the output branch are connected between a common supply terminal and a common ground terminal.
18. A band gap reference circuit, comprising:
a first branch comprising a first transistor element and a first temperature dependent resistive element;
a second branch comprising a second transistor element having a size different from the first transistor element;
an output branch comprising a second temperature dependent resistive element, said second temperature dependent resistive element being coupled to an output terminal; and
a control element coupled to the first and second branch to control a current through the first and second branches;
wherein said first temperature dependent resistive element comprises a first current mirror, said first current mirror comprising a first input transistor and a first mirror transistor, wherein each control terminal of both said first input transistor and said first mirror transistor is coupled to a terminal of said first input transistor; and
wherein said second temperature dependent resistive element comprises a second current mirror, said second current mirror comprising a second input transistor and a second mirror transistor, wherein each control terminal of both said second input transistor and said second mirror transistor is coupled to a terminal of the second input transistor; and
wherein each controlled section of each mirror transistor is arranged in a current path of the respective branch.
19. The band gap reference circuit according to claim 18, wherein each mirror transistor comprises a channel width, which is greater than a respective channel width of the corresponding input transistor.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A waveguide type optical switch having a form of a matrix optical switch of M inputs and N outputs (each of M and N is an integral number of three or more) formed on a single substrate, the matrix optical switch comprising:
M pieces of optical switches each having one input and N outputs; and
N pieces of optical combining devices each having M inputs and one output, wherein
the a-th input (a is an integral number of 1 to M) in the matrix optical switch comprises the input of the a-th optical switch of one input and N outputs,
the b-th output (b is an integral number of 1 to N) in the matrix optical switch comprises the output of the b-th optical combining device of M inputs and one output,
each of the optical switches comprises (N\u22121) pieces of unit optical switch elements each having one input and two outputs, and
each of the optical combining devices comprises (M\u22121) pieces of unit optical combining elements each having two inputs and one output, wherein
in the optical switch,
the input of the first unit optical switch element forms the input of the optical switch,
one of the outputs in the i-th (i is an integral number of 1 to (N\u22122)) unit optical switch element is connected to the input of the (i+1)-th unit optical switch element,
the other of the outputs in the i-th unit optical switch element forms the i-th output in the optical switch, and
the two outputs in the (N\u22121)-th unit optical switch element form the (N\u22121)-th output and the N-th output in the optical switch, wherein
in the optical combining device,
the two inputs of the first unit optical combining element form the first and second inputs in the optical combining device,
one of the inputs in the j-th (j is an integral number of 2 to (M\u22121)) unit optical combining element is connected to
the output in the (j\u22121)-th unit optical combining element,
the other of the inputs in the j-th unit optical combining element forms the (j+1)-th input in the optical combining device, and
the output in the (M\u22121)-th unit optical combining element forms the output in the optical combining device, wherein
in the matrix optical switch,
the p-th optical switch (p is an integral number of 1 to M) out of the optical switches and the q-th optical combining device (q is an integral number of 1 to N) out of the optical combining devices are connected between any output in the p-th optical switch and any input in the q-th optical combining device, wherein
in a case where any output in the p-th optical switch is the k-th (k is an integral number of 1 to N) output in the connection, any input in the q-th optical combining device is the k-th input, and k is from 2 to (N\u22121) in the connection,
the waveguide intersection is not included in the connection between the output of the unit optical switch element forming the k-th output in the p-th optical switch and the input of the unit optical combining element forming the k-th input in the q-th optical combining device.
2. A waveguide type optical switch according to claim 1, wherein
a combining optical power ratio between two input terminals of the first unit optical combining element in the optical combining device is 1:1, and
a combining optical power ratio between an input terminal connected to the input of the optical switch in the j-th unit optical combining element (j is an integral number of 2 to (M\u22121)) and an input terminal connected to the other unit optical combining element is 1:j.
3. A waveguide type optical switch having a form of a matrix optical switch of N inputs and M outputs (each of M and N is an integral number of three or more) formed on a single substrate, the matrix optical switch comprising:
N pieces of optical branching devices each having one input and M outputs; and
M pieces of optical switches each having N inputs and one output, wherein
the a-th input (a is an integral number of 1 to N) in the matrix optical switch comprises the input of the a-th optical branching device of one input and M outputs,
the b-th output (b is an integral number of 1 to M) in the matrix optical switch comprises the output of the b-th optical switch of N inputs and one output,

each of the optical branching devices comprises (M\u22121) pieces of unit optical branching elements each having one input and two outputs, and
each of the optical switches comprises (N\u22121) pieces of unit optical switch elements each having two inputs and one output, wherein
in the optical branching device,
the input of the first unit optical branching element forms the input in the optical branching device,
one of the outputs in the i-th (i is an integral number of 1 to (M\u22122)) unit optical branching element is connected to the input of the (i+1)-th unit optical branching element,
the other of the outputs in the i-th unit optical branching element forms the i-th output in the optical branching device, and
two outputs in the (M\u22121)-th unit optical branching element form the (M\u22121)-th output and the M-th output in the optical branching device, wherein
in the optical switch,
two inputs in the first unit optical switch element form the first and second inputs in the optical switch,
one of the inputs in the j-th (j is an integral number of 2 to (N\u22121)) unit optical switch element is connected to the output in the (j\u22121)-th unit optical switch element,
the other of the inputs in the j-th unit optical switch element forms the (j+1)-th input in the optical switch, and
the output in the (N\u22121)-th unit optical switch element forms the output in the optical switch, wherein
in the matrix optical switch,
the p-th optical branching device (p is an integral number of 1 to N) out of the optical branching devices and the q-th optical switch (q is an integral number of 1 to M) out of the optical switches are connected between any output in the p-th optical branching device and any input in the q-th optical switch, wherein
in a case where any output in the p-th optical branching device is the k-th (k is an integral number of 1 to M) output in the connection, any input in the q-th optical switch is the k-th input, and
in a case where k is from 2 to (M\u22121) in the connection, the waveguide intersection is not included in the connection between the output in the unit optical branching element forming the k-th output in the p-th optical branching device and the input in the unit optical switch element forming the k-th input in the q-th optical switch.
4. A waveguide type optical switch according to claim 3, wherein
a branching optical power ratio between two output terminals of the (M\u22121)-th unit optical branching element in the optical branching device is 1:1, and
a branching optical power ratio between an output terminal connected to the output in the optical switch of the i-th unit optical branching element (i is an integral number of 1 to (M\u22122)) and an output terminal connected to the other unit optical branching element is 1:(M\u2212i).

1. A method of secure data processing on a computer system with a higher-level or coordinated secure operating system that is not visible for a user, wherein
the secure operating system as a computer program application provides a virtual machine (VM) with virtual computer hardware on which a user operating system visible to and usable by the user can be executed and which has at least one virtual mass memory with a file system of the user operating system, or
the secure operating system is encapsulated in a first virtual machine and the user operating system visible to and usable by the user and equipped with at least one virtual mass memory with a file system is executed in a second virtual machine,
the secure operating system cannot by manipulated by the user or a computer program application, in particular malware,
the file system of the user operating system is read in and provided to an analysis process executed on the secure operating system,
a read access of the user operating system to a data block in the virtual mass memory (sector) is intercepted and transferred to the analysis process that assigns the data block to a file and determines all the data blocks pertaining to the file, and
the analysis process controls a test process executed in the secure operating system (scan engine) to detect harmful files.
2. The method defined in claim 1, further comprising the step of
creating a data structure that links the sectors of the virtual mass memory with the files located therein and that links each file with a state variable.
3. The method defined in claim 2, further comprising the step of
providing files in the virtual mass memory that have been checked by the test process to detect harmful files and have been identified as harmless with a first state variable (\u201cclean\u201d) and files that have not yet been checked or that have been modified by the user operating system are provided with a second state variable (\u201cdirty\u201d).
4. The method defined in claim 1, further comprising the step of
copying a file identified by the test process as a harmful file into a secured memory area of the secure operating system.
5. The method defined in claim 1, further comprising the step of
overwriting a file that is identified by the test process as a harmful file and thus making it unusable such that a read access of the user operating system to this file is denied.
6. The method defined in claim 1, further comprising the step of
creating with the secure operating system an image (memory image) of the virtual hard disk.
7. The method defined in claim 6, further comprising the step of
checking the virtual hard disk by the test process in the non-active state of the user operating system.
8. The method defined in claim 6, further comprising the step of
checking the image of the virtual hard disk by the test process during operation of the user operating system.
9. The method defined in claim 7, further comprising the step of
replacing a harmful file of the virtual hard disk or of the image of the virtual hard disk with a corresponding undamaged file.
10. The method defined in claim 7, further comprising the step of first making unusable and thereafter replacing manually with a corresponding undamaged file a harmful file of the virtual hard disk or of the image of the virtual hard disk.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A developing unit comprising:
a developing roller;
a first housing unit configured to house a developer to be supplied to the developing roller;
a first stirring and transporting member configured to stir and transport the developer along a first passage formed in the first housing unit;
a second housing unit configured to house a developer and to have in its sidewall a discharge port which discharges outside overflowing developer and to form a second passage which has a bottom surface raised in the form of a slope from an upstream side to a downstream side in a developer transporting direction; and
a second stirring and transporting member configured to stir and transport the developer along the second passage and to have a first part which stirs and transports the developer and a second part which does not stir and transport the developer.
2. The developing unit according to claim 1, wherein
a rotational direction of the first stirring and transporting member is opposite to a rotational direction of the second stirring and transporting member.
3. The developing unit according to claim 1, wherein
the second passage has a bottom surface raised in the form of a slope from an upstream end of the discharge port towards a downstream side in a developer transporting direction.
4. The developing unit according to claim 1, wherein
the second stirring and transporting member configured to not have a part which stirs and transports the developer in a vicinity of the discharge port in a developer transporting direction.
5. The developing unit according to claim 1, wherein
the first housing and the second housing unit are partitioned with a partition part.
6. The developing unit according to claim 5, wherein
the second passage is formed by an inner wall of the second housing unit and a lateral surface of the partition part.
7. The developing unit according to claim 1, wherein
the second stirring and transporting member configured to have a spiral paddle and a rotational axis.
8. The developing unit according to claim 1, wherein
an outer diameter dimension near the discharge port of the second stirring and transporting member that stirs and transports the developer being smaller than in other parts.
9. The developing unit according to claim 1, wherein
the bottom surface has an inclination angle of approximately 2 degrees or less.
10. A developing unit comprising:
a developing roller;
a first housing unit configured to house a developer to be supplied to the developing roller;
a first stirring and transporting member configured to have a spiral paddle which stirs and transports the developer along a first passage formed in the first housing unit;
a second housing unit configured to house a developer and to have in its sidewall a discharge port which discharges outside overflowing developer and to form a second passage which has a bottom surface raised in the form of a slope from an upstream side to a downstream side in a developer transporting direction; and
a second stirring and transporting member configured to stir and transport the developer along the second passage and to have a spiral part which stirs and transports the developer and a non-spiral part which does not stir and transport the developer.
11. The developing unit according to claim 10, wherein
a rotational direction of the first stirring and transporting member is opposite to a rotational direction of the second stirring and transporting member.
12. The developing unit according to claim 10, wherein
the second passage has a bottom surface raised in the form of a slope from an upstream end of the discharge port towards a downstream side in a developer transporting direction.
13. The developing unit according to claim 10, wherein
the second stirring and transporting member configured to not have a part which stirs and transports the developer in a vicinity of the discharge port in a developer transporting direction.
14. The developing unit according to claim 10, wherein
the first housing and the second housing unit are partitioned with a partition part.
15. The developing unit according to claim 14, wherein
the second passage is formed by an inner wall of the second housing unit and a lateral surface of the partition part.
16. The developing unit according to claim 10, wherein
the second stirring and transporting member configured to have a spiral paddle and a rotational axis.
17. The developing unit according to claim 10, wherein
an outer diameter dimension near the discharge port of the second stirring and transporting member that stirs and transports the developer being smaller than in other parts.
18. The developing unit according to claim 10, wherein
the bottom surface has an inclination angle of approximately 2 degrees or less.