All The Claims

1. An oscillator generating a clock signal having a constant period, comprising:
a clock generator generating a clock signal in response to a first logic signal and a second logic signal, wherein the first and second logic signals have the same period but different logic level transition timing;
a logic signal generator generating the first logic signal and the second logic signal in response to a reference signal corresponding to a reference current, and compensating for variations in the reference signal by applying at least one compensation current to thereby maintain the constant period of the clock signal.
2. The oscillator of claim 1, wherein the constant period of the clock signal is derived from the period of the first logic signal and the period of the second logic signal.
3. The oscillator of claim 1, wherein the logic signal generator comprises a compensation transistor generating the at least one compensation current.
4. The oscillator of claim 3, wherein the compensation transistor is a PMOS transistor which is turned ON in response to variation in the reference current.
5. The oscillator of claim 1, wherein the logic signal generator comprises:
a first logic signal generator generating the first logic signal in response to the feedback of the clock signal; and
a second logic signal generator generating the second logic signal in response to the feedback of an inverse of the clock signal.
6. The oscillator of claim 5, wherein the first logic signal generator comprises:
a first inverter receiving and inverting the feedback of the clock signal;
a first capacitor charging and discharging in response to an output of the first inverter and outputting a first voltage;
a first compensation transistor connected in parallel with the first inverter and generating a first compensation current in accordance with variations in the reference current; and
a first comparator comparing the first voltage with a reference voltage derived from the reference current and outputting the first logic signal.
7. The oscillator of claim 6, wherein the first compensation transistor is a PMOS transistor which is turned ON in response to a variation in the reference current.
8. The oscillator of claim 6, wherein the first comparator is an amplifier outputting the first logic signal at a high logic level when the first voltage is greater than the reference voltage.
9. The oscillator of claim 6, wherein the first logic signal generator further comprises:
a first copy transistor copying the reference current.
10. The oscillator of claim 9, wherein the first copy transistor is an NMOS transistor gated by the reference voltage and connected between ground and a first node at which the outputs of the first inverter and first compensation transistor are connected.
11. The oscillator of claim 6, wherein the second logic signal generator comprises:
a second inverter receiving and inverting the inverse of the feedback of the clock signal;
a second capacitor charging and discharging in response to an output of the second inverter and generating a second voltage;
a second compensation transistor connected in parallel with the second inverter and generating a second compensation current in accordance with variations in the reference current; and
a second comparator comparing the second voltage with the reference voltage and outputting the second logic signal.
12. The oscillator of claim 11, wherein the second compensation transistor is a PMOS transistor which is turned ON in response to a variation in the reference current.
13. The oscillator of claim 11, wherein the second comparator is an amplifier outputting the second logic signal at a high logic level when the second voltage is greater than the reference voltage.
14. The oscillator of claim 11, wherein the second logic signal generator further comprises:
a second copy transistor copying the reference current.
15. The oscillator of claim 14, wherein the second copy transistor is an NMOS transistor gated by the reference voltage and connected between ground and a second node at which the outputs of the second inverter and the second compensation transistor are connected.
16. The oscillator of claim 1, wherein the clock generator comprises a latch receiving the first logic signal and the second logic signal, and outputting the clock signal and the inverse of the clock signal.
17. The oscillator of claim 1, further comprising:
a reference generator generating a reference current and a corresponding reference voltage as the reference signal in response to an enable signal.
18. The oscillator of claim 17, wherein the reference generator comprises:
a first transistor connected to a supply voltage and gated by the enable signal;
a second transistor passing the reference current to ground; and
a resistor connected between the first transistor and the second transistor and developing the reference voltage.
19. The oscillator of claim 1, wherein the reference signal varies in accordance with variations in at least one of a supply voltage and operating temperature for the oscillator.
20. An oscillator for generating a clock signal having a constant period, comprising:
a reference generator generating a reference current from an applied supply voltage, wherein the reference current varies with variations in the supply voltage and with operating temperature for the oscillator;
a logic signal generator comprising a first logic signal generator generating a first logic signal in response to a reference voltage derived from the reference current, and second logic signal generator generating a second logic signal in response to the reference voltage, wherein the reference voltage varies with variations in the supply voltage and with operating temperature for the oscillator, and wherein the first and second logic signals have the same period but different logic level transition timing;
a clock generator generating the clock signal in response to the first logic signal and the second logic signal,
wherein the logic signal generator compensates for variations in the reference current to main the constant period of the clock signal by applying a first compensation current in the first logic signal generator and a second compensation current in the second logic signal generator.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. In a computer readable medium, a treemap visualization engine for generating treemap visualizations from arbitrary hierarchical data from a caller resource, comprising:
treemap generator object that receives an arbitrary set of hierarchical data from a caller resource and draws a treemap representation of the data; and
a treemap control object for displaying the treemap representation in a software application.
2. The visualization engine of claim 1 in which the treemap generator object includes a TreemapGenerator interface having a property that receives the set of hierarchical data as an XML string to form a collection of Node objects.
3. The visualization engine of claim 2 in which the XML string includes a <Node> element for each treemap node, the <Node> element having a child <Nodes> element that contains the child nodes of the <Node> element.
4. The visualization engine of claim 2 in which the treemap generator object further includes a Nodes interface having a method that adds an individual node object to the collection of Node objects.
5. The visualization engine of claim 1 in which the treemap generator object includes a TreemapGenerator interface having a method that draws the treemap representation of the data onto an object provided by the caller resource.
6. The visualization engine of claim 1 in which the treemap generator object further includes a Nodes interface having a method that adds an individual node object to a collection of Node objects.
7. The visualization engine of claim 1 in which the treemap control object includes a TreemapControl interface having a property that receives the set of hierarchical data as an XML string to form a collection of Node objects.
8. The visualization engine of claim 7 in which the XML string includes a <Node> element for each treemap node, the <Node> element having a child <Nodes> element that contains the child nodes of the <Node> element.
9. In a computer readable medium, a treemap visualization engine for generating treemap visualizations from arbitrary hierarchical data from a caller resource, comprising:
treemap generator object that receives an arbitrary set of hierarchical data from a caller resource and draws a treemap representation of the data, the treemap generator object including a treemap generator interface, a Nodes interface, and a Node interface; and
a treemap control object for displaying the treemap representation in an application, the treemap control object including a Treemap Control interface, a Nodes interface, and a Node interface.
10. The visualization engine of claim 9 in which the treemap generator interface includes a property that receives the set of hierarchical data as an XML string to form a collection of Node objects.
11. The visualization engine of claim 10 in which the XML string includes a <Node> element for each treemap node, the <Node> element having a child <Nodes> element that contains the child nodes of the <Node> element.
12. The visualization engine of claim 10 in which the Nodes interface includes a method that adds an individual node object to the collection of Node objects.
13. The visualization engine of claim 9 in which the treemap generator interface includes a method that draws the treemap representation of the data onto an object provided by the caller resource.
14. The visualization engine of claim 9 in which the Nodes interface includes a method that adds an individual node object to a collection of Node objects.
15. The visualization engine of claim 9 in which the treemap control interface includes a property that receives the set of hierarchical data as an XML string to form a collection of Node objects.
16. The visualization engine of claim 15 in which the XML string includes a <Node> element for each treemap node, the <Node> element having a child <Nodes> element that contains the child nodes of the <Node> element.
17. In a computer readable medium, a treemap visualization engine for generating treemap visualizations from arbitrary hierarchical data from a caller resource, comprising:
treemap generator object that receives an arbitrary set of hierarchical data from a caller resource and draws a treemap representation of the data, the treemap generator object including a treemap generator interface, a Nodes interface, and a Node interface;
18. The visualization engine of claim 17 in which the treemap generator interface includes a property that receives the set of hierarchical data as an XML string to form a collection of Node objects.
19. The visualization engine of claim 18 in which the XML string includes a <Node> element for each treemap node, the <Node> element having a child <Nodes> element that contains the child nodes of the <Node> element.
20. The visualization engine of claim 17 in which the Nodes interface includes a method that adds an individual node object to the collection of Node objects.

1. A printing system, comprising:
a rasterizer processor configured to load a content file, and perform a raster process according to a predetermined ink-saving parameter so as to output a raster image;
a computer-to-plate (CTP) device installed with a blank CTP plate and configured to output the CTP plate for a printing device according to the raster image; and
an ink-saving amount determination device coupled, in parallel with the CTP device, to the rasterizer processor and configured to determine an ink-saving amount according to a raster image when the ink-saving parameter is disabled and a raster image when the ink-saving parameter is enabled.
2. The printing system according to claim 1, wherein the ink-saving amount determination device determines the ink-saving amount by calculating and comparing the ink coverage of the raster images.
3. The printing system according to claim 1, wherein the raster image is an eight-bit grayscale image obtained through converting, by an optimization algorithm, a one-bit image.
4. The printing system according to claim 1, wherein the ink-saving amount determination device determines the ink-saving amount for each color separation with respect to each color separation of the content file.
5. The printing system according to claim 4, wherein the color separation includes cyan (C), magenta (M), yellow (Y) and black (K).
6. The printing system according to claim 2, wherein the ink coverage is calculated by dividing a sum of gray values for pixels of the eight-bit image by a product of the number of the pixels and 255.
7. The printing system according to claim 1, wherein the ink-saving amount determination device stores the determined ink-saving amount in a database.
8. The printing system according to claim 7, wherein the ink-saving amount determination device, in response to a statistics command from a client, provides ink-saving data statistics according to the ink-saving amount stored in the database.
9. A printing method, comprising:
loading a content file, performing a raster process according to a predetermined ink-saving parameter, and outputting a raster image;
outputting an imaging CTP plate according to the raster image;
disabling the ink-saving parameter and acquiring the raster image; and
determining the ink-saving amount available for the content file according to a raster image acquired when the ink-saving parameter is enabled and a raster image acquired when the ink-saving parameter is disabled.
10. The printing method according to claim 9, wherein in the step of determining the ink-saving amount, the ink-saving amount is determined by calculating and comparing the ink coverage of eight-bit grayscale images.
11. The printing method according to claim 10, wherein the ink coverage is calculated by dividing a sum of gray values for pixels of the eight-bit image by a product of the number of the pixels and 255.
12. The printing method according to claim 9, wherein the ink-saving amount for each color separation is determined with respect to each color separation version of the content file.
13. The printing method according to claim 12, wherein the color separation includes cyan (C), magenta (M), yellow (Y) and black (K).
14. The printing method according to claim 9, further comprising storing the determined ink-saving amount in a database.
15. The printing method according to claim 14, further comprising, in response to a statistics command from a client, providing ink-saving data statistics according to the ink-saving amount stored in the database.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A ceramic matrix composite component coated with environmental barrier coatings, comprising:
a substrate formed of a silicide-containing ceramic matrix composite;
a silicon carbide layer deposited on a surface of the substrate;
a silicon layer deposited on a surface of the silicon carbide layer;
a mixed layer made of a mixture of mullite and ytterbium silicate and deposited on a surface of the silicon layer; and
an oxide layer deposited on a surface of the mixed layer.
2. The ceramic matrix composite component according to claim 1, wherein the ytterbium silicate is any one of Yb2SiO5 and Yb2Si2O7.
3. The ceramic matrix composite component according to claim 1, wherein
the silicon carbide layer has a thickness of not less than 10 \u03bcm nor more than 50 \u03bcm,
the silicon layer has a thickness of not less than 50 \u03bcm nor more than 140 \u03bcm, and
the mixed layer has a thickness of not less than 75 \u03bcm nor more than 225 \u03bcm.
4. The ceramic matrix composite component according to claim 3, wherein the silicon layer has a thickness of not less than 50 \u03bcm nor more than 100 \u03bcm.
5. The ceramic matrix composite component according to claim 1, wherein the oxide layer is formed of oxide mainly containing at least one selected from the group consisting of hafnium oxide, hafnium silicate, lutetium silicate, ytterbium silicate, titanium oxide, zirconium oxide, aluminum titanate, aluminum silicate, and lutetium hafnium oxide.
6. The ceramic matrix composite component according to claim 5, wherein the oxide layer is formed of monoclinic hafnium oxide.
7. The ceramic matrix composite component according to claim 1, wherein
the silicon carbide layer is a chemical vapor deposition coating,
the silicon layer and the mixed layer are thermal sprayed coatings formed by low pressure thermal spraying, and
the oxide layer is a thermal sprayed coating formed by air thermal spraying.
8. The ceramic matrix composite component according to claim 1, wherein the substrate is formed of a ceramic matrix composite obtained by combining silicon carbide fibers with a silicon carbide matrix.
9. The ceramic matrix composite component according to claim 1, wherein the ceramic matrix composite component is used in an environment in which a component surface temperature is 1200\xb0 C. to 1400\xb0 C. and in which water vapor partial pressure is 30 kPa to 140 kPa.
10. A method of manufacturing a ceramic matrix composite component coated with environmental barrier coatings, comprising:
a substrate forming step of forming a substrate of a silicide-containing ceramic matrix composite;
a silicon carbide layer deposition step of depositing a silicon carbide layer on a surface of the substrate by chemical vapor deposition;
a silicon layer deposition step of depositing a silicon layer on a surface of the silicon carbide layer by low pressure thermal spraying;
a mixed layer deposition step of depositing a mixed layer made of a mixture of mullite and ytterbium silicate on a surface of the silicon layer by low pressure thermal spraying; and
an oxide layer deposition step of depositing an oxide layer on a surface of the mixed layer by air thermal spraying.
11. The method according to claim 10, wherein
in the silicon carbide layer deposition step, the silicon carbide layer is deposited to a thickness of not less than 10 \u03bcm nor more than 50 \u03bcm,
in the silicon layer deposition step, the silicon layer is deposited to a thickness of not less than 50 \u03bcm nor more than 140 \u03bcm, and
in the mixed layer deposition step, the mixed layer is deposited to a thickness of not less than 75 \u03bcm nor more than 225 \u03bcm.
12. The method according to claim 11, wherein in the silicon layer deposition step, the silicon layer is deposited to a thickness of not less than 50 \u03bcm nor more than 100 \u03bcm.