All The Claims

1. A cooking device using steam for cooking and having a heating chamber for cooking,
wherein
a door of a heating chamber is provided with a gasket preventing leakage of steam from the heating chamber; and
a lip section of the gasket has a bag-like cross section in which an opening is formed on a side thereof that faces an inside of the heating chamber, an end of the lip section in the bag-like cross section being bent toward the door so that steam pressure acts on the opening to inflate the bag-like cross section and press the gasket against a wall around an opening of the heating chamber.
2. The cooking device of claim 1, wherein
the cooking device uses microwaves for cooking;
the door of the cooking chamber is provided with a choke structure preventing leakage of microwaves from the heating chamber and a choke cover covering the choke structure;
the gasket is fitted near the choke structure; and
the lip section of the gasket extends from a space between the choke cover and the door.
3. The cooking device of claim 1, wherein
the lip section of the gasket has a shape that appears to be a bag having a mouth thereof narrowed.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A liquid-crystalline medium, comprising
A) 2-40% by weight one or more compounds of formula I,
in which
R0 denotes a halogenated or unsubstituted alkyl or alkoxy radical having 1 to 15 C atoms, in which one or more CH2 groups are optionally each, independently of one another, replaced by \u2014C\u2261C\u2014,
\u2003in such a way that O atoms are not linked directly to one another,
X0 denotes F, Cl, ON, SF5, SCN, NCS, a halogenated alkyl radical, a halogenated alkenyl radical, a halogenated alkoxy radical or a halogenated alkenyloxy radical having up to 6 C atoms, and
Y1 and Y2 each, independently of one another, denote H or F, and
\u2003each, independently of one another, denote
\u2003where at least one of
\u2003denotes
B) 20-90% by weight one or more compounds of formula II,
in which A, R0, X0, Y1 and Y2 have the meanings indicated for formula I:
C) 2-30% by weight one or more compounds of formula III,
in which R0, X0, Y1 and Y2 have the meanings indicated for formula I, and Y3 and Y4 each, independently of one another, denote H or F;
D) optionally 2-30% by weight one or more compounds of formula IV,
in which R0, X0, Y1 and Y2 have the meanings indicated for formula I,
E) optionally 2-30% by weight one or more compounds of formulae IX-XII,
in which X0 has the meaning indicated for formula I,
L
denotes H or F,
\u201calkyl\u201d
denotes C1-7-alkyl,
R\u2032
denotes C1-7-alkyl, C1-6-alkoxy or C2-7-alkenyl,
and
\u201calkenyl\u201d and
each, independently of one another, denote
\u201calkenyl*\u201d
C2-7-alkenyl
and
F) optionally 4-30% by weight one or more compounds of formula XIV
in which R1 and R2 each, independently of one another, denote n-alkyl, alkoxy, oxaalkyl, fluoroalkyl or alkenyl, each having up to 9 C atoms.
2. A liquid-crystalline medium according to claim 1, comprising one or more compounds of the following formulae:
in which R0 and X0 have the meanings indicated for formula I.
3. A liquid-crystalline medium according to claim 1, comprising one or more compounds of the following formulae:
in which R0 and X0 have the meanings indicated for formula I.
4. A liquid-crystalline medium according to claim 1, further comprising one or more compounds of the following formulae:
in which R0, X0, Y1 and Y2 have the meanings indicated for formula I,
Y3 and Y4 each, independently of one another, denote H or F,
Z0 denotes \u2014C2H4\u2014, \u2014(CH2)4\u2014, \u2014CH\u2550CH\u2014, \u2014CF\u2550CF\u2014, \u2014C2F4\u2014, \u2014CH2CF2\u2014, \u2014CF2CH2\u2014, \u2014CH2O\u2014, \u2014OCH2\u2014, \u2014COO\u2014 or \u2014OCF2\u2014, in formulae V and VI also a single bond, in formulae V and VIII also \u2014CF2O\u2014, and
r denotes 0 or 1.
5. A liquid-crystalline medium according to claim 4, comprising one or more compounds of the following formulae:
in which R0 and X0 have the meanings indicated for formula I.
6. A liquid-crystalline medium according to claim 1, comprising one or more compounds of the following formulae:
in which X0 has the meaning indicated for formula I,
L
denotes H or F,
\u201calkyl\u201d
denotes C1-7-alkyl,
R\u2032
denotes C1-7-alkyl, C1-6-alkoxy or C2-7-alkenyl,
and
\u201calkenyl\u201d and
each, independently of one another, denote
\u201calkenyl*\u201d
C2-7-alkenyl.
7. A liquid-crystalline medium according to claim 1, further comprising one or more compounds of the following formulae:
in which R1 and R2 each, independently of one another, denote n-alkyl, alkoxy, oxaalkyl, fluoroalkyl or alkenyl, each having up to 9 C atoms.
8. An electro-optical apparatus, comprising a liquid-crystalline medium according to claim 1.
9. An electro-optical liquid-crystalline display, containing a liquid-crystalline medium according to claim 1.
10. A process for preparing a liquid-crystalline medium according to claim 1, comprising mixing together one or more compounds of formulae I, II and III.

1. A humidity control device that dehumidifies one of outdoor air and indoor air, and humidifies the other in adsorption heat exchangers each carrying an adsorbent to adsorb moisture of air, and then supplies the outdoor air to an inside of a room, and exhausts the indoor air to an outside of the room, the device comprising:
casings;
a refrigerant circuit having the adsorption heat exchangers, a compressor that circulates a refrigerant, a switching mechanism that switches a circulation direction of the refrigerant, and refrigerant pipes that connect the adsorption heat exchangers, the compressor, and the switching mechanism;
fans that respectively take the outdoor air and the indoor air into one of the casings; and
an electric component unit including control parts of the humidity control device,
wherein the casings include:
a first casing in which the fans, the switching mechanism, and the electric component unit are arranged; and
a second casing in which the adsorption heat exchangers are arranged, and
the first casing and the second casing are mutually connected through ducts.
2. The humidity control device according to claim 1, wherein
the first casing is provided with a supply air outlet to supply the air to the inside of the room and an exhaust outlet to exhaust the air to the outside of the room, and
the second casing is provided with an outside air intake to take in the outside air, and an inside air intake to take in the indoor air.
3. The humidity control device according to claim 1, wherein
the first casing is provided with an outside air intake to take in the outside air, and an inside air intake to take in the indoor air, and
the second casing is provided with a supply air outlet to supply the air to the inside of the room and an exhaust outlet to exhaust the air to the outside of the room.
4. The humidity control device according to claim 3, wherein air filters are provided on a suction side of the respective fans inside the first casing.
5. The humidity control device according to claim 2, wherein the ducts include a duct for outside air that introduces the outdoor air to the first casing, and a duct for inside air that introduces the indoor air to the first casing, the outdoor air being taken into the second casing from the outside air intake, and the indoor air being taken into the second casing from the inside air intake.
6. The humidity control device according to claim 3, wherein the ducts include a duct for outside air that introduces the outdoor air to the second casing, and a duct for inside air that introduces the indoor air to the second casing, the outdoor air being taken into the first casing from the outside air intake, and the indoor air being taken into the first casing from the inside air intake.
7. The humidity control device according to claim 1, wherein the compressor is connected to the refrigerant pipes drawn from the first casing.
8. The humidity control device according to claim 1, wherein the compressor is arranged inside the first casing.
9. The humidity control device according to claim 7, wherein a plurality of second units are connected to a first unit in parallel, the plurality of second units each being configured by the second casing and internal equipment of the second casing, and the first unit being configured by the first casing, internal equipment of the first casing, and the compressor.
10. The humidity control device according to claim 8, wherein a plurality of second units are connected to a first unit in parallel, the plurality of second units each being configured by the second casing and internal equipment of the second casing, and the first unit being configured by the first casing, internal equipment of the first casing, and the compressor.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An operation mode setting apparatus, comprising:
an operation mode setting control unit configured to discriminate the phase of a reference clock from the phase of a feedback clock to generate a locking suspension signal; and
an operation mode setting unit configured to generate a locking completion signal in response to a phase comparison signal and a pulse signal under the control of a reset signal and the locking suspension signal,
wherein the operation mode setting control unit includes:
a latch configured to latch the locking completion signal and generate an output;
a first detector configured to detect whether the phase of the feedback clock leads the phase of the reference clock by a first time, and to generate a first detection signal;
a second detector configured to detect whether the phase of the reference clock leads the phase of the feedback clock by a second time, and to generate a second detection signal; and
a signal combining unit configured to combine an output signal of the latch, the first detection signal, and the second detection signal to generate the locking suspension signal.
2. The operation mode setting apparatus of claim 1, wherein the operation mode setting control unit is configured to enable the locking suspension signal, when the phase difference between the reference clock and the feedback clock is equal to or larger than a predetermined time.
3. The operation mode setting apparatus of claim 2, wherein the operation mode setting control unit is configured to enable the locking suspension signal when the locking completion signal is enabled, the phase of the feedback clock leads the phase of the reference clock by the first time, or the phase of the reference clock leads the phase of the feedback clock by the second time.
4. The operation mode setting apparatus of claim 1, wherein the operation mode setting unit includes:
a reset unit configured to control whether to enable the locking completion signal in response to the reset signal and the locking suspension signal; and
a locking completion signal generator configured to generate the locking completion signal in response to the phase comparison signal and the pulse signal under the control of the reset unit.
5. The operation mode setting apparatus of claim 4, wherein the reset unit is configured to supply voltage to a first node to which a voltage for generating the locking completion signal is applied when the locking completion signal is disabled and then the reset signal is enabled, or when the locking completion signal is enabled and then the locking suspension signal is enabled.
6. The operation mode setting apparatus of claim 5, wherein the locking completion signal generator includes:
a power supply unit configured to supply voltage to a second node in response to the locking completion signal and the pulse signal;
a first control unit configured to control the voltage level of the first node in response to the phase comparison signal and the pulse signal;
a second control unit configured to control the voltage level of the second node in response to the phase comparison signal and the pulse signal; and
a latch unit configured to latch the voltage applied at the first node and output the locking completion signal.
7. The operation mode setting apparatus of claim 6, wherein the power supply unit is configured to supply a voltage having a first level to the second node when the locking completion signal is disabled and then the pulse signal is enabled.
8. The operation mode setting apparatus of claim 6, wherein the first control unit includes a flip-flop configured to latch the phase comparison signal when the pulse signal is enabled, and to connect the first node and the second node.
9. The operation mode setting apparatus of claim 7, wherein the second control unit is configured to supply a voltage having a second level to the second node, when the phase comparison signal and the pulse signal have the first levels.
10. A semiconductor integrated circuit, comprising:
a DLL (delay locked loop) circuit configured to delay a reference clock in response to a locking completion signal to generate a delay clock and a feedback clock, and to generate the locking completion signal in response to the reference clock and the feedback clock; and
a DLL control unit configured to discriminate the phase of the reference clock from the phase of the feedback clock to control the operation mode of the DLL circuit,
wherein the DLL control unit includes:
a latch is configured to latch the locking completion signal and generate an output;
a first detector configured to detect whether the phase of the feedback clock leads the phase of the reference clock by a first time, and to generate a first detection signal;
a second detector configured to detect whether the phase of the reference clock leads the phase of the feedback clock by a second time, and to generate a second detection signal; and
a signal combining unit configured to combine an output signal of the latch, the first detection signal, and the second detection signal to generate the locking suspension signal.
11. The semiconductor integrated circuit of claim 10, wherein the DLL control unit is configured to enable a locking suspension signal when the phase difference between the reference clock and the feedback clock is equal to or larger than a predetermined time.
12. The semiconductor integrated circuit of claim 11, wherein the DLL control unit is configured to enable the locking suspension signal when the locking completion signal is enabled, the phase of the feedback clock leads the phase of the reference clock by the first time, or the phase of the reference clock leads the phase of the feedback clock by the second time.
13. The semiconductor integrated circuit of claim 11, wherein the DLL circuit includes:
a phase comparator configured to compare the phase of the reference clock with the phase of the feedback clock and to generate a phase comparison signal;
an operation mode setting apparatus configured to generate a locking completion signal in response to a reset signal, the phase comparison signal, and the locking suspension signal;
a delay unit configured to delay the reference clock to generate the delay clock in response to the phase comparison signal and the locking completion signal; and
a delay compensating unit configured to delay the delay clock to generate the feedback clock in order to compensate for the delay of the delay clock as it travels to a data output buffer.
14. The semiconductor integrated circuit of claim 13, wherein the operation mode setting apparatus is configured to control the state of the locking completion signal in response to the phase comparison signal after the reset signal is enabled when the locking completion signal is disabled, and resets the state of the locking completion signal in response to the phase comparison signal according to whether the locking suspension signal is enabled when the locking completion signal is enabled.
15. The semiconductor integrated circuit of claim 13, wherein the operation mode setting apparatus includes:
a reset unit configured to control the voltage level of a first node in response to the locking suspension signal, the reset signal, and the locking completion signal;
a power supply unit configured to supply voltage to a second node in response to the locking completion signal and a pulse signal;
a first control unit configured to control the voltage level of the first node in response to the phase comparison signal and the pulse signal;
a second control unit configured to control the voltage level of the second node in response to the phase comparison signal and the pulse signal; and
a latch unit configured to latch the voltage level applied at the first node and outputs the locking completion signal.
16. The semiconductor integrated circuit of claim 15, wherein the reset unit is configured to supply voltage to the first node when the locking completion signal is disabled and then the reset signal is enabled, or when the locking completion signal is enabled and then the locking suspension signal is enabled.
17. The semiconductor integrated circuit of claim 13, wherein the delay unit is configured to operate in a fine locking mode when the locking completion signal is enabled, and operate in a coarse locking mode when the locking completion signal is disabled again.
18. A method of controlling a semiconductor integrated circuit, comprising:
disabling a locking completion signal to perform a coarse locking operation on a reference clock, thereby generating a delay clock and a feedback clock;
enabling the locking completion signal to perform a fine locking operation on the reference clock, thereby generating the delay clock and the feedback clock; and
discriminating the phase of the reference clock from the phase of the feedback clock and re-determining whether to enable the locking completion signal on the basis of the result of the discrimination,
wherein the enabling of the locking suspension signal includes:
latching the locking completion signal;
detecting whether the phase of the feedback clock leads the phase of the reference clock by a first time, and generating a first detection signal;
detecting whether the phase of the reference clock leads the phase of the feedback clock by a second time, and generating a second detection signal; and
combining the latched locking completion signal, the first detection signal, and the second detection signal to generate the locking suspension signal.
19. The method of claim 18, wherein the performing of the coarse locking operation includes:
comparing the phase of the reference clock with the phase of the feedback clock and disabling the locking completion signal;
delaying the reference clock in response to the locking completion signal to generate the delay clock; and
delaying the delay clock to generate the feedback clock in order to compensate for the delay amount of the delay clock on a traveling path to a data output buffer.
20. The method of claim 18, wherein the performing of the fine locking operation includes:
comparing the phase of the reference clock with the phase of the feedback clock and enabling the locking completion signal;
delaying the reference clock in response to the locking completion signal to generate the delay clock; and
delaying the delay clock to generate the feedback clock in order to compensate for the delay amount of the delay clock on a traveling path to a data output buffer.
21. The method of claim 18, wherein the re-determining of whether to enable the locking completion signal includes:
when the phase difference between the reference clock and the feedback clock is equal to or larger than a predetermined time, enabling a locking suspension signal; and
initializing the state of the locking completion signal in response to the locking suspension signal.