All The Claims

1. A method comprising the steps of:
analyzing a printed circuit board design to identify at least one untestable circuit on the printed circuit board;
identifying at least one access point on a surface of the printed circuit board that provides access to the at least one untestable circuit on the board; and
creating at least one new test point by selectively depositing procoat on the surface of the printed circuit board such that no procoat is deposited over the identified at least one access point.
2. The method of claim 1 further comprising the step of providing a test fixture adapted to contact the at least one new test point.
3. The method of claim 1 wherein the at least one new test point is a point on a circuit trace.
4. The method of claim 1 wherein the location of the at least one test point is selected based on its proximity to other circuit components.
5. The method of claim 1 wherein the step of analyzing the printed circuit board design to identify at least one untestable circuit on the board comprises the step of using a gerber tool to analyze the printed circuit board.
6. The method of claim 1 further comprising the step of contacting the at least one new test point using a spring-loaded test probe, the test probe having a substantially planar probe head and a spring force less than four ounces.
7. The method of claim 6 wherein the step of contacting the at least one new test point comprises the step of contacting the at least one new test point with a substantially planar probe head coated with a plurality of dendritic particles.
8. A method for testing circuits, the method comprising the steps of:
analyzing a printed circuit board design to identify at least one circuit on the board as an untestable circuit;
identifying at least one location on the surface of the printed circuit board suitable for providing an access point to the at least one untestable circuit;
providing a printed circuit board constructed according to the printed circuit board design, the printed circuit board having a surface; and
creating at least one new test point on the surface of the printed circuit board by selectively masking the surface of the printed circuit board to prevent the at least one location from being covered by procoat.
9. The method of claim 8 wherein the step of analyzing the printed circuit board to identify at least one circuit on the board as an untestable circuit comprises the step of using visualization software to analyze the printed circuit board.
10. The method of claim 8 further comprising the step of using a test fixture to contact the at least one new test point.
11. The method of claim 8 wherein the step of identifying at least one location on the surface of the printed circuit board further comprises the step of using the location of at least one circuit component to identify the at least one location on the surface of the printed circuit board.
12. The method of claim 8 wherein the at least one additional test point on the surface of the printed circuit board is a point on a circuit trace located on the surface of the circuit board.
13. The method of claim 8 further comprising the step of contacting the at least one new test point using a spring-loaded test probe, the test probe having a substantially planar probe head and a spring force less than four ounces.
14. The method of claim 13 wherein the step of contacting the at least one new test point comprises the step of contacting the at least one new test point with a substantially planar probe head coated with a plurality of dendritic particles.
15. A method for identifying and probing circuit traces comprising:
providing a printed circuit board design, the printed circuit board comprising a plurality of nets and a plurality of existing test points suitable for testing at least one of the plurality of nets;
using a visualization program to locate at least one of the plurality of nets that cannot be tested using the plurality of existing test points;
identifying at least one new test point, suitable for testing the at least one of the plurality of nets that cannot be tested using the plurality of existing test points;
providing a printed circuit board constructed according to the printed circuit board design;
selectively masking the printed circuit board with a protective covering to cover the at least one new test point;
coating the printed circuit board with a coating;
removing the protective covering; and
adjusting a probe in a test fixture to contact the at least one new test point.
16. A method for creating a testing apparatus, the method comprising the steps of:
providing a spring loaded test probe, the test probe comprising:
a substantially planar probe head;
a spring for biasing the probe head, the spring having a spring force of no more than four ounces; and
coating the probe head with dendrites.
17. A test probe comprising:
a probe head with a substantially planar surface;
a spring for biasing the probe head, the spring having a spring force of no more than four ounces; and
a plurality of dendritic protrusions on the substantially planar surface of the probe head.
18. A spring loaded test probe for use in circuit testing, the spring loaded test probe comprising:
a probe head to engage at least one of a plurality of test points, wherein the probe head is substantially planar and covered with dendrites; and
a spring in contact with the probe head, the spring biasing the probe head toward the plurality of test points, the spring having a spring force of less than four ounces.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An antisense compound 8 to 30 nucleobases in length targeted to a nucleic acid molecule encoding human Survivin, wherein said antisense compound inhibits the expression of human Survivin.
2. The antisense compound of claim 1 which is an antisense oligonucleotide.
3. The antisense compound of claim 2 comprising at least an 8-nucleobase portion of SEQ ID NO: 19, 21, 23, 24, 25, 27, 29, 30, 32, 37, 40, 41, 43, 48, 49, 50, 51, 52, 56, 60, 65, 68, 70, 72, 76, 80, 83, 87, 88, 91, 92, 101, 106, 107, 113, 138, 141, 152 or 156.
4. The antisense compound of claim 3 comprising SEQ ID NO: 25, 30, 40, 43, 48, 65, 70, 80, 83 or 88.
5. The antisense compound of claim 2 which comprises at least one modified internucleoside linkage.
6. The antisense compound of claim 5 wherein the modified internucleoside linkage is a phosphorothioate linkage.
7. The antisense compound of claim 2 which comprises at least one modified sugar moiety.
8. The antisense compound of claim 7 wherein the modified sugar moiety is a 2-O-methoxyethyl sugar moiety.
9. The antisense compound of claim 2 which comprises at least one modified nucleobase.
10. The antisense compound of claim 9 wherein the modified nucleobase is a 5-methylcytosine.
11. The antisense compound of claim 2 which is a chimeric oligonucleotide.
12. A composition comprising the antisense compound of claim 1 and a pharmaceutically acceptable carrier or diluent.
13. The composition of claim 12 further comprising a colloidal dispersion system.
14. The composition of claim 12 wherein the antisense compound is an antisense oligonucleotide.
15. A method of inhibiting the expression of Survivin in human cells or tissues comprising contacting human cells or tissues with the antisense compound of claim 1 so that expression of Survivin is inhibited.
16. A method of treating an animal having a disease or condition associated with Survivin comprising administering to an animal having a disease or condition associated with Survivin a therapeutically or prophylactically effective amount of the antisense compound of claim 1 so that expression of Survivin is inhibited.
17. The method of claim 16 wherein the disease or condition is a hyperproliferative condition.
18. The method of claim 17 wherein the hyperproliferative condition is cancer.
19. A method of treating a human having a disease or condition characterized by a reduction in apoptosis comprising administering to a human having a disease or condition characterized by a reduction in apoptosis a prophylactically or therapeutically effective amount of the antisense compound of claim 1.
20. A method of modulating apoptosis in a cell comprising contacting a cell with the antisense compound of claim 1 so that apoptosis is modulated.
21. A method of modulating cytokinesis in a cell comprising contacting a cell with the antisense compound of claim 1 so that cytokinesis is modulated.
22. A method of modulating the cell cycle in a cell comprising contacting a cell with the antisense compound of claim 1 so that the cell cycle is modulated.
23. A method of inhibiting the proliferation of cells comprising contacting cells with an effective amount of the antisense compound of claim 1, so that proliferation of the cells is inhibited.
24. The method of claim 23 wherein said cells are cancer cells.
25. The composition of claim 12 further comprising a chemotherapeutic agent.
26. The method of claim 19 further comprising administering to the patient a chemotherapeutic agent.
27. The method of claim 20 wherein said modulation of apoptosis is sensitization to an apoptotic stimulus.
28. The method of claim 27 wherein said apoptotic stimulus is a cytotoxic chemotherapeutic agent.
29. The method of claim 23 further comprising contacting said cells with a chemotherapeutic agent.
30. The method of claim 29 wherein said chemotherapeutic agent is taxol or cisplatin.

1. A system for cluster configuration information replication, comprising:
a replication component configured to:
evaluate a cluster configuration schema defining a first storage object, of a first storage cluster, that is to be actively monitored for change resulting from a first storage operation;
responsive to determining that the first storage operation was implemented for the first storage object, generate a replication workflow for the first storage object based upon a change to the first storage object by the first storage operation; and
transfer the replication workflow to a second storage cluster for selective implementation of the replication workflow.
2. The system of claim 1, the replication workflow comprising the first storage operation, an input for the first storage operation, and a result of the first storage operation.
3. The system of claim 1, the cluster configuration schema defining a replication domain as comprising the first storage object and a second storage object, and the replication component configured to:
responsive to determining that a second storage operation was implemented for the second storage object, including the second storage operation in the replication workflow.
4. The system of claim 3, the replication component configured to:
define a storage operation replay order for the first storage operation and the second storage operation; and
include the storage operation replay order within the replication workflow.
5. The system of claim 1, the replication component configured to:
facilitate a transformation upon the replication workflow to modify a characteristic of the first storage operation to create a transformed replication workflow for selective implementation by the second storage cluster.
6. The system of claim 5, the transformation comprising at least one of a volume name change, a volume size change, an IP address change, a name change, a destination location change, a policy change, a junction path change, or a storage object property change.
7. The system of claim 1, the replication workflow comprising a set of storage information associated at least one of a set of storage objects or a set of storage operations, and the replication component configured to:
facilitate the selective implementation of a first portion of the set of storage information, but not a second portion of the set of storage information, of the replication workflow by the second storage cluster.
8. The system of claim 1, the replication component configured to:
identify the implementation of the first storage operation in real-time; and
transfer the replication workflow to the second storage cluster in real-time.
9. The system of claim 1, the replication component configured to:
identify a second storage operation that was implemented for a second storage object; and
responsive to the cluster configuration scheme not defining the second storage object as being actively monitored for change by the second storage operation, disqualify the second storage operation for inclusion within the replication workflow.
10. The system of claim 1, the replication workflow comprising an update workflow for the first storage object.
11. The system of claim 1, the replication workflow associated with a set of storage objects, and the replication workflow comprising a baseline workflow for the set of storage objects.
12. The system of claim 1, the replication component configured to:
responsive to identifying a disaster associated with the first storage cluster, invoke the second storage cluster to operate according to a disaster recovery mode in place of the first storage cluster based upon the selective implementation of the replication workflow.
13. The system of claim 12, the replication component configured to:
generate a switchback replication workflow based upon the second storage cluster operating according to the disaster recovery mode; and
transfer the switchback replication workflow to the first storage cluster for switchback operation from the second storage cluster to the first storage cluster upon disaster recovery of the first storage cluster.
14. The system of claim 1, the cluster configuration schema comprising a hierarchical collection of storage objects and storage operations available to perform upon the storage objects that result in a change to a cluster configuration of the first storage cluster.
15. The system of claim 1, the cluster configuration schema specifying a set of object characteristics and a set of storage operations for the first storage object that are to be captured for inclusion within the replication workflow.
16. The system of claim 1, the cluster configuration schema defining semantics of the first storage operation.
17. A method for cluster configuration information replication, comprising:
specifying a cluster configuration schema defining a first storage object, of a first storage cluster, that is to be actively monitored for change resulting from a first storage operation;
receiving, by a second storage cluster, a replication workflow indicating that the first storage operation was implemented for the first storage object; and
selectively implementing a first portion of the replication workflow on the second storage cluster.
18. The method of claim 17, the replication workflow comprising a set of storage information associated with at least one of a set of storage objects or a set of storage operations, and the method comprising:
selectively disqualifying a second portion of the set of storage information for implementation on the second storage cluster.
19. The method of claim 17, the selectively implementing comprising:
applying a transformation upon the replication workflow to modify a characteristic of the first storage operation to create a transformed replication workflow for selective implementation on the second storage cluster.
20. A computer readable medium comprising instructions which when executed perform a method for cluster configuration information replication, comprising:
evaluating a cluster configuration schema defining a first storage object, of a first storage cluster, that is to be actively monitored for change resulting from a first storage operation;
responsive to determining that the first storage operation was implemented for the first storage object, generating a replication workflow for the first storage object based upon a change to the first storage object by the first storage operation; and
transferring the replication workflow to a second storage cluster for selectively implementation of the replication workflow.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An oscillator configured to produce an oscillating signal of arbitrary frequency.
2. The oscillator of claim 1, wherein the oscillator comprises a mechanical resonator configured to produce the oscillating signal of arbitrary frequency.
3. The oscillator of claim 1, wherein the arbitrary frequency differs from a standard oscillator frequency by at least 30 parts per million (ppm).
4. The oscillator of claim 3, wherein the arbitrary frequency differs from a standard oscillator frequency by at least 50 ppm.
5. The oscillator of claim 3, wherein the arbitrary frequency differs from a standard oscillator frequency by at least 100 ppm.
6. The oscillator of claim 5, wherein the arbitrary frequency differs from a standard oscillator frequency by at least 1000 ppm.
7. A system comprising the oscillator of claim 1.
8. The system of claim 7, further comprising receiving circuitry configured to receive and operate on the oscillating signal of arbitrary frequency.
9. The system of claim 8, wherein the receiving circuitry is configured to shift the oscillating signal to adopt a standard oscillator frequency.
10. The system of claim 8, wherein the receiving circuitry is configurable to accommodate the arbitrary frequency.
11. The system of claim 8, wherein the system is configured to receive an indication of a value of the arbitrary frequency.
12. A circuit, comprising:
a reference clock comprising:
a reference oscillator configured to produce a reference oscillator signal having an arbitrary frequency that is not a power of 2; and
counter circuitry configured to receive the reference oscillator signal and count a number of oscillations of the reference oscillator signal,
wherein the reference clock is configured to output a reference clock signal with a time base based on the number of oscillations of the reference oscillator signal counted by the counter circuitry; and

a real time clock coupled to the reference clock and configured to receive the reference clock signal having the time base, and configured to produce an output indicative of current time.
13. The circuit of claim 12, wherein the time base is one second.
14. The circuit of claim 12, wherein the real time clock does not include a divider configured to operate on the reference clock signal.
15. The circuit of claim 12, wherein the reference clock further comprises comparator circuitry configured to compare the number of oscillations of the reference oscillator signal as counted by the counter circuitry to a reference number.
16. The circuit of claim 15, wherein the comparator circuitry is configured to produce a comparator output exhibiting a state change when the number of oscillations of the reference oscillator signal equals or exceeds the reference number.
17. The circuit of claim 16, further comprising a feedback loop between an output of the counter circuitry and a reset port of the counter circuitry.
18. The circuit of claim 17, further comprising a pulse generator coupled to an output of the comparator circuitry to receive the comparator output and configured to produce the reference clock signal.
19. The circuit of claim 16, wherein the reference number is a frequency of the reference oscillator.
20. The circuit of claim 16, wherein the reference number is stored in memory.
21. The circuit of claim 20, wherein the memory is in the reference oscillator.
22. The circuit of claim 16, wherein the reference clock is further configured to determine an accumulated error and to adjust an output of the comparator circuitry based on the accumulated error.
23. The circuit of claim 22, further comprising temperature compensation circuitry configured to compensate the accumulated error or the comparator output based on a measured temperature.
24. The circuit of claim 16, wherein the reference oscillator is frequency tunable, wherein the counter circuitry is an integer counter, and wherein the circuit further comprising tuning circuitry configured to tune a frequency of the reference oscillator to an integer value.
25. The circuit of claim 12, further comprising temperature compensation circuitry configured to generate a tuning signal to tune the arbitrary frequency of the reference oscillator in response to temperature induced variations in the arbitrary frequency.
26. A circuit comprising:
a tunable reference oscillator configured to produce a tunable reference oscillating signal; and
a real time clock configured to receive a reference clock signal derived from the tunable reference oscillating signal and produce an output indicative of current time.
27. The circuit of claim 26, wherein the tunable reference oscillator comprises memory storing an indication of a frequency of operation of the tunable reference oscillator.
28. The circuit of claim 26, wherein the tunable reference oscillator is tuned to an arbitrary frequency N Hz, wherein N is an integer.
29. The circuit of claim 28, further comprising a counter configured to count oscillations of the reference oscillating signal and to produce a clock pulse after N oscillations.
30. The circuit of claim 28, further comprising a counter configured to count oscillations of the reference oscillating signal and to produce a clock pulse after N2x oscillations, where x is an integer.
31. The circuit of claim 26, further comprising circuitry configured to frequency tune the tunable reference oscillator in response to temperature variations.
32. The circuit of claim 31, further comprising a counter and circuitry for comparing an output of the counter to a reference value, and wherein the circuitry configured to frequency tune the tunable reference oscillator does so without altering the counter or the reference value.
33. The circuit of claim 26, further comprising a counter and circuitry for comparing an output of the counter to a reference value, and wherein the circuit is configured to account for temperature drift of the tunable reference oscillator by changing the counter or the reference value.
34. The circuit of claim 33, wherein the circuit is configured to account for temperature drift of the tunable reference oscillator by changing the counter or the reference value and by frequency tuning the tunable reference oscillator.
35. A method of operating clock circuitry, comprising:
generating a reference oscillating signal having an arbitrary frequency that is not a power of 2;
counting a number of oscillations of the reference oscillating signal;
producing a reference clock signal based on the number of oscillations of the reference oscillating signal counted;
providing the reference clock signal to a real time clock; and
generating an output of the real time clock indicative of current time.
36. The method of claim 35, wherein generating the reference oscillating signal comprises using an arbitrary frequency reference oscillator, and wherein the method further comprises frequency tuning the arbitrary frequency reference oscillator in response to temperature variations.
37. The method of claim 35, wherein producing the reference clock signal comprises comparing the number of oscillations of the reference oscillating signal to a reference number using a comparator and changing a state of an output of the comparator when the number of oscillations of the reference oscillating signal equals or exceeds the reference number.
38. The method of claim 37, wherein generating the reference oscillating signal comprises using an arbitrary frequency reference oscillator, and wherein the method further comprises providing the reference number from the arbitrary frequency reference oscillator to the comparator.