All The Claims

1. A multilevel FLASH cell architecture comprising:
at least one FLASH cell;
a plurality of reference generators;
a plurality of comparators coupled to the FLASH cell via a sensing node and coupled to the plurality of reference generators; the plurality of comparators for comparing a signal of the sensing node to a full spectrum of reference voltage signals in parallel from the plurality of reference generators; and providing outputs; and
translation logic coupled to the plurality of comparators for decoding the outputs to determine the state of the FLASH cell, wherein the plurality of reference generators are coupled together such that a first reference generator provides a base current and subsequent reference generators add sequentially increasing amount of delta current to the base current.
2. The FLASH cell architecture of claim 1 wherein the most significant bit (MSB) and the least significant bit (LSB) of the state is provided from the translation logic.
3. The FLASH cell architecture of claim 2 wherein the translation logic detects underprogramming and overprogramming of a FLASH cell by comparing the sensing node to limits for each state.
4. The FLASH cell architecture of claim 2 wherein the translation logic detects when the cell is properly programmed.
5. The FLASH cell architecture of claim 2 wherein the translation logic detects if the current state of the FLASH cell matches the desired data to indicate successful data validation.
6. The FLASH cell architecture of claim 2 wherein if the translation logic detects that the current state of the FLASH cell is less than the desired state further programming is necessary to provide the data within the desired state limits.
7. The FLASH cell architecture of claim 2 wherein if the translator logic detects that the cell is overprogrammed an error signal is detected.
8. The FLASH cell architecture of claim 1 wherein the full spectrum of reference signals include boundary reference voltages between states and upper and lower target voltages within a state.
9. The FLASH cell architecture of claim 1 wherein a margin between reference generators is adjusted by arbitration codes that select currents for summing.
10. The FLASH cell architecture of claim 1 wherein each reference voltage generator generates a current for each boundary between 2n states and for an upper limit and a lower limit for each state.
11. The FLASH cell architecture of claim 1 which includes a control engine for decoding received addresses wherein the row address causes a row of cells to be activated and a column address activates the reference generators and a multichannel cell address.
12. The FLASH cell architecture of claim 1 wherein the at least one FLASH cell comprises a memory cell array.
13. The FLASH cell architecture of claim 12 wherein there are multi-level states per cell.
14. The FLASH cell architecture of claim 12 which includes an IO buffer coupled to the translation logic.
15. The FLASH cell architecture of claim 14 which includes a writecache buffer coupled to the translation logic.
16. The FLASH cell architecture of claim 15 which includes a fast one stage readwrite control engine with progressive state indicators coupled to translation logic.
17. The FLASH cell architecture of claim 16 which includes a set of external and auto calibration registers coupled to the control engine.
18. The FLASH cell architecture of claim 17 which includes a set of reference calibration commands in addition to the read, erase and program commands.
19. The FLASH cell architecture of claim 18 which includes a voltagecurrent reference generator coupled to the FLASH cell memory array and the calibration registers.
20. The FLASH cell architecture of claim 19 which includes a plurality of address registers coupled to a row address decoder and a calendar address decoder.
21. The FLASH memory device of claim 12, further comprising:
a plurality of memory cell strings each connected to x-y addressable word lines and bit lines.
22. A multilevel FLASH cell architecture comprising:
at least one FLASH cell;
a plurality of reference generators;
a plurality of comparators coupled to the FLASH cell via a sensing node and coupled to the plurality of reference generators; the plurality of comparators for comparing a signal of the sensing node to a full spectrum of reference voltage signals in parallel from the plurality of reference generators; and providing outputs; and
translation logic coupled to the plurality of comparators for decoding the outputs to determine the state of the FLASH cell, wherein the translation logic detects underprogramming and overprogramming of a FLASH cell by comparing the sensing node to limits for each state.
23. A multilevel FLASH cell architecture comprising:
at least one FLASH cell;
a plurality of reference generators;
a plurality of comparators coupled to the FLASH cell via a sensing node and coupled to the plurality of reference generators; the plurality of comparators for comparing a signal of the sensing node to a full spectrum of reference voltage signals in parallel from the plurality of reference generators; and providing outputs; and
translation logic coupled to the plurality of comparators for decoding the outputs to determine the state of the FLASH cell, wherein the most significant bit (MSB) and the least significant bit (LSB) of the state is provided from the translation logic, and wherein the translation logic detects if the current state of the FLASH cell matches the desired data to indicate successful data validation.
24. The FLASH cell architecture of claim 23 wherein if the translation logic detects that the current state of the FLASH cell is less than the desired state further programming is necessary to provide the data within the desired state limits.
25. The FLASH cell architecture of claim 24 wherein if the translator logic detects that the cell is overprogrammed an error signal is detected.
26. A multilevel FLASH cell architecture comprising:
at least one FLASH cell;
a plurality of reference generators;
a plurality of comparators coupled to the FLASH cell via a sensing node and coupled to the plurality of reference generators; the plurality of comparators for comparing a signal of the sensing node to a full spectrum of reference voltage signals in parallel from the plurality of reference generators; and providing outputs;
translation logic coupled to the plurality of comparators for decoding the outputs to determine the state of the FLASH cell; and
a control engine for decoding received addresses wherein the row address causes a row of cells to be activated and a column address activates the reference generators and a multichannel cell address.
27. A multilevel FLASH cell architecture comprising:
a memory cell array wherein
a plurality of reference generators;
a plurality of comparators coupled to the memory cell array via a sensing node and coupled to the plurality of reference generators; the plurality of comparators for comparing a signal of the sensing node to a full spectrum of reference voltage signals in parallel from the plurality of reference generators; and providing outputs;

translation logic coupled to the plurality of comparators for decoding the outputs to determine the state of the memory cell array; and
a IO buffer coupled to the translation logic.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. A method of simultaneous trading of a derivative contract andor combinations thereof and a contract in an underlying instrument in an automated exchange system, the system comprising a matching module and a deal capture module, the method comprising the steps of:
forming and displaying a virtual derivative contract andor combinations thereof, the virtual derivative contract implying a simultaneous trade in a derivative contract and its underlying instrument.
receiving bids and offers in said virtual derivative contract
matching the bids and offers in the virtual derivative contract andor combinations thereof in the matching module, and
forwarding the data relating to the matched deal to the deal capture module where a combined deal, one deal in the derivative contract and one deal in its underlying instrument, is formed in accordance with the data related to the from the virtual derivative contract when there is a match in the virtual optionfuture contract andor combinations thereof.
2. A method according to claim 1, wherein the price of the underlying contract and or the delta value is displayed in the same view as the virtual derivative contract.
3. A method according to claim 1, further comprising the step of providing a price feed in the underlying contract from an external execution point, when the underlying contract is not traded on the exchange listing the virtual derivative contract.
4. A method according to claim 1, wherein the virtual derivatives contract corresponds to a covered option contract.
5. A method according to claim 4, wherein the number of contracts traded in the underlying instrument is calculated as: (size of virtual covered option instrument)*(delta value)*(nominal reference contract)(nominal virtual covered option instrument).
6. An automated exchange system for simultaneous trading of a derivative contract andor combinations thereof and a contract in an underlying instrument, the system comprising a matching module and a deal capture module, comprising:
means for forming and displaying a virtual derivative contract andor combinations thereof, the virtual derivative contract implying a simultaneous trade in a derivative contract and its underlying instrument.
means for receiving bids and offers in said virtual derivative contract
means in the matching module for matching the bids and offers in the virtual derivative contract andor combinations thereof, and
means for forwarding the data relating to the matched deal to the deal capture module where a combined deal, one deal in the derivative contract and one deal in its underlying instrument, is formed in accordance with the data related to the from the virtual derivative contract when there is a match in the virtual optionfuture contract andor combinations thereof.
7. A system according to claim 6, wherein the price of the underlying contract and or the delta value is displayed in the same view as the virtual derivative contract.
8. A system according to claim 6, further comprising means for providing a price feed in the underlying contract from an external execution point.
9. A system according to claim 6, wherein the virtual derivatives contract corresponds to a covered option contract.
10. A system according to claim 9, comprising means for calculating the number of contracts traded in the underlying instrument as: (size of virtual covered option instrument)*(delta value)*(nominal reference contract)(nominal virtual covered option instrument).
11. An exchange system, the system comprising a number of remote input terminals for entering bids and offers in a financial instrument implying the simultaneous execution of a derivative contract and a contract underlying said derivative contract (a virtual derivative contract), to be matched by the exchange system, the remote terminals being linked to a central computer server hosting an automated matching process of said entered bids and offers, the system further comprising a deal capture module provided to receive data output from the matching process relating to matched bids and offers given for said virtual derivative contracts, the deal capture module being programmed to capture a deal in the derivative contract and in the contract underlying the derivative contract in accordance with the specification of the particular virtual derivative contract matched by the matching process.
12. A computer program product storing a computer program, which when executed on a computer performs the following steps:
forms and displays a virtual derivative contract andor combinations thereof, the virtual derivative contract implying a simultaneous trade in a derivative contract and its underlying instrument.
receives bids and offers in said virtual derivative contract
matches the bids and offers in the virtual derivative contract andor combinations thereof, and
forwards the data relating to the matched deal to a deal capture module where a combined deal, one deal in the derivative contract and one deal in its underlying instrument, can be formed in accordance with the data related to the from the virtual derivative contract when there is a match in the virtual optionfuture contract andor combinations thereof.

1. A display device comprising:
a gate wiring comprising a first conductive material, over a first substrate;
an insulating film over the gate wiring;
a semiconductor film over the insulating film;
a source region and a drain region over the semiconductor film;
a source electrode and a drain electrode formed over the source region and the drain region, respectively, each of the source electrode and the drain electrode comprising a second conductive material;
a source wiring being continuous to the source electrode;
a pixel electrode comprising a transparent conductive film in contact with the drain electrode;
a first terminal portion electrically connected to the gate wiring, comprising:
a first layer comprising a same material as the first conductive material, over the first substrate; and
a second layer comprising a same material as the transparent conductive film, over the first layer,

a second terminal portion electrically connected to the source wiring, comprising:
a first layer comprising a same material as the second conductive material, over the first substrate; and
a second layer comprising a same material as the transparent conductive film, over the first layer,

a second substrate joined to the first substrate by using a sealing material;
a second electrode formed adjacent to the second substrate so as to be opposed the pixel electrode; and
an IC chip over the first substrate, electrically connected to at least one of the first and second terminal portions,
a first flexible printed circuit electrically connected to the first terminal portion through an anisotropic conductive adhesive; and
a second flexible printed circuit electrically connected to the second terminal portion through an anisotropic conductive adhesive.
2. The display device according to claim 1, wherein the semiconductor film comprises microcrystalline silicon.
3. The display device according to claim 1, wherein the semiconductor film comprises amorphous silicon.
4. The display device according to claim 1, wherein the transparent conductive film is ITO.
5. The display device according to claim 1, wherein the transparent conductive film includes indium oxide and zinc oxide.
6. A display device comprising:
a gate wiring comprising a first conductive material, over a first substrate;
an insulating film over the gate wiring;
a semiconductor film over the insulating film;
a source region and a drain region over the semiconductor film;
a source electrode and a drain electrode formed over the source region and the drain region, respectively, each of the source electrode and the drain electrode comprising a second conductive material;
a source wiring being continuous to the source electrode;
a pixel electrode comprising a transparent conductive film in contact with the drain electrode;
a first terminal portion electrically connected to the gate wiring, comprising:
a first layer comprising a same material as the first conductive material, over the first substrate; and
a second layer comprising a same material as the transparent conductive film, over the first layer,

a second terminal portion electrically connected to the source wiring, comprising:
a first layer comprising a same material as the second conductive material, over the first substrate; and
a second layer comprising a same material as the transparent conductive film, over the first layer,

a second substrate joined to the first substrate by using a sealing material;
a second electrode formed adjacent to the second substrate so as to be opposed the pixel electrode,
a first flexible printed circuit electrically connected to the first terminal portion through an anisotropic conductive adhesive; and
a second flexible printed circuit electrically connected to the second terminal portion through an anisotropic conductive adhesive.
7. The display device according to claim 6, wherein the semiconductor film comprises microcrystalline silicon.
8. The display device according to claim 6, wherein the semiconductor film comprises amorphous silicon.
9. The display device according to claim 6, wherein the transparent conductive film is ITO.
10. The display device according to claim 6, wherein the transparent conductive film includes indium oxide and zinc oxide.
11. A display device comprising:
a gate wiring comprising a first conductive material, over a first substrate;
an insulating film over the gate wiring;
a first semiconductor film over the insulating film;
a source region and a drain region over the first semiconductor film;
a source electrode and a drain electrode formed over the source region and the drain region, respectively, each of the source electrode and the drain electrode comprising a second conductive material;
a source wiring being continuous to the source electrode;
a pixel electrode comprising a transparent conductive film in contact with the drain electrode;
a first terminal portion electrically connected to the gate wiring, comprising:
a first layer comprising a same material as the first conductive material, over the first substrate; and
a second layer comprising a same material as the transparent conductive film, over the first layer,

a second terminal portion electrically connected to the source wiring, comprising:
a first layer over the first substrate, comprising a same material as the first semiconductor film;
a second layer formed on the first layer and comprising a same material as the source region and the drain region;
a third layer formed on the second layer and comprising a same material as the second conductive material; and
a fourth layer formed on the third layer and comprising a same material as the transparent conductive film,

a second substrate joined to the first substrate by using a sealing material;
a second electrode formed adjacent to the second substrate so as to be opposed the pixel electrode;
an IC chip over the first substrate, electrically connected to at least one of the first and second terminal portions,
a first flexible printed circuit electrically connected to the first terminal portion through an anisotropic conductive adhesive; and
a second flexible printed circuit electrically connected to the second terminal portion through an anisotropic conductive adhesive.
12. The display device according to claim 11, wherein the first semiconductor film comprises microcrystalline silicon.
13. The display device according to claim 11, wherein the first semiconductor film comprises amorphous silicon.
14. The display device according to claim 11, wherein the transparent conductive film is ITO.
15. The display device according to claim 11, wherein the transparent conductive film includes indium oxide and zinc oxide.
16. A display device comprising:
a gate wiring comprising a first conductive material, over a first substrate;
an insulating film over the gate wiring;
a first semiconductor film over the insulating film;
a source region and a drain region over the first semiconductor film;
a source electrode and a drain electrode formed over the source region and the drain region, respectively, each of the source electrode and the drain electrode comprising a second conductive material;
a source wiring being continuous to the source electrode;
a pixel electrode comprising a transparent conductive film in contact with the drain electrode;
a first terminal portion electrically connected to the gate wiring, comprising:
a first layer comprising a same material as the first conductive material, over the first substrate; and
a second layer comprising a same material as the transparent conductive film, over the first layer,

a second terminal portion electrically connected to the source wiring, comprising:
a first layer over the first substrate, comprising a same material as the first semiconductor film;
a second layer formed on the first layer and comprising a same material as the source region and the drain region;
a third layer formed on the second layer and comprising a same material as the second conductive material; and
a fourth layer formed on the third layer and comprising a same material as the transparent conductive film,

a second substrate joined to the first substrate by using a sealing material;
a second electrode formed adjacent to the second substrate so as to be opposed the pixel electrode,
a first flexible printed circuit electrically connected to the first terminal portion through an anisotropic conductive adhesive; and
a second flexible printed circuit electrically connected to the second terminal portion through an anisotropic conductive adhesive.
17. The display device according to claim 16, wherein the first semiconductor film comprises microcrystalline silicon.
18. The display device according to claim 16, wherein the first semiconductor film comprises amorphous silicon.
19. The display device according to claim 16, wherein the transparent conductive film is ITO.
20. The display device according to claim 16, wherein the transparent conductive film includes indium oxide and zinc oxide.
21. A display device comprising:
a thin film transistor comprising a gate electrode formed over a substrate, an insulating film formed over the gate electrode, a first semiconductor film formed over the insulating film, source and drain regions formed over the first semiconductor film, and a source electrode over the source region, and a drain electrode formed over the drain region;
a pixel electrode comprising a transparent conductive material, formed over the thin film transistor, and connected to the drain electrode;
a gate wiring formed between the substrate and the insulating film and being continuous to the gate electrode;
a source wiring being continuous to the source electrode, the source wiring comprising a second semiconductor film and a third semiconductor film formed on the second semiconductor film;
a source wiring terminal portion formed over the substrate and including a first layer comprising a same material as the first semiconductor film, a second layer formed on the first layer, the second layer comprising a same material as the source region and the drain region, a third layer formed on the second layer, the third layer comprising a same material as the source electrode, and a fourth layer formed on the third layer, the fourth layer comprising a same material as the transparent conductive material;
a first flexible printed circuit electrically connected to the source wiring terminal portion through an anisotropic conductive adhesive,
wherein the second semiconductor film is continuous to the first semiconductor film, and comprises a same material as the first semiconductor film,
wherein the third semiconductor film is continuous to the source region, and comprises a same material as the source region,
wherein at least a portion of the second semiconductor film is wider than the source wiring and the third semiconductor film at least at an intersection of the gate wiring and the source wiring,
wherein the fourth layer is wider than the third layer in the source wiring terminal portion.
22. The display device according to claim 21, wherein the first semiconductor film comprises microcrystalline silicon.
23. The display device according to claim 21, wherein the first semiconductor film comprises amorphous silicon.
24. The display device according to claim 21, wherein the transparent conductive material is ITO.
25. The display device according to claim 21, wherein the transparent conductive material includes indium oxide and zinc oxide.
26. A display device comprising:
a thin film transistor comprising a gate electrode formed over a substrate, an insulating film formed over the gate electrode, a first semiconductor film formed over the insulating film, source and drain regions formed over the first semiconductor film, and a source electrode over the source region, and a drain electrode formed over the drain region;
a pixel electrode comprising a transparent conductive material, formed over the thin film transistor, and connected to the drain electrode;
a gate wiring formed between the substrate and the insulating film and being continuous to the gate electrode;
a source wiring being continuous to the source electrode, the source wiring comprising a second semiconductor film and a third semiconductor film formed on the second semiconductor film;

a gate wiring terminal portion comprising a first layer comprising a same material as the gate electrode and a second layer comprising a same material as the transparent conductive material;
a source wiring terminal portion formed over the substrate and including a first layer comprising a same material as the first semiconductor film, a second layer formed on the first layer, the second layer comprising a same material as the source region and the drain region, a third layer formed on the second layer, the third layer comprising a same material as the source electrode, and a fourth layer formed on the third layer, the fourth layer comprising a same material as the transparent conductive material;
a first flexible printed circuit electrically connected to the source wiring terminal portion through an anisotropic conductive adhesive; and
a second flexible printed circuit electrically connected to the gate wiring terminal portion through an anisotropic conductive adhesive,
wherein the second semiconductor film is continuous to the first semiconductor film, and comprises a same material as the first semiconductor film,
wherein the third semiconductor film is continuous to the source region, and comprises a same material as the source region,
wherein at least a portion of the second semiconductor film is wider than the source wiring and the third semiconductor film at least at an intersection of the gate wiring and the source wiring,
wherein the fourth layer is wider than the third layer in the source wiring terminal portion.
27. The display device according to claim 26, wherein the first semiconductor film comprises microcrystalline silicon.
28. The display device according to claim 26, wherein the first semiconductor film comprises amorphous silicon.
29. The display device according to claim 26, wherein the transparent conductive material is ITO.
30. The display device according to claim 26, wherein the transparent conductive material includes indium oxide and zinc oxide.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for transmitting signals by a transmitter in a mobile communication system using a Multiple Input Multiple Output (MIMO) scheme, the method comprising:
if a codeword to be transmitted in a first time interval is input, generating a unitary space-time matrix to correspond to the codeword;
multiplying the unitary space-time matrix by a first final transmission matrix denoting signals transmitted in a second time interval before the first time interval, thereby generating a second final transmission matrix denoting signals to be transmitted in the second time interval; and
transmitting signals corresponding to the second final transmission matrix through a plurality of transmit antennas in the second time interval.
2. The method as claimed in claim 1, wherein generating the unitary space-time matrix comprises
generating a first matrix to correspond to the codeword; and
generating the unitary space-time matrix from the first matrix by using a Gram-Schumidt scheme.
3. The method as claimed in claim 2, wherein the first matrix is expressed by
Z

v
+
1
=

(
\u03b1

1
,
1
\u2062

z
v
+
1

,
1
,
1
0
\u2026
0
0
\u03b1

1
,
2
\u2062

z
v
+
1

,
1
,
2
\u03b1

2
,
1
\u2062

z
v
+
1

,
2
,
1
\u2026
0
0
0
\u03b1

2
,
2
\u2062

z
v
+
1

,
2
,
2
\u2026
0
0
0
0
\u2026
0
0
\u22ee
\u22ee
\u22f0
\u22ee
\u22ee
0
0
\u2026
\u03b1
L
–
1

,
1
\u2062

z
v
+
1

,

L
–
1

,
1
0
0
0
\u2026
\u03b1
L
–
1

,
2
\u2062

z
v
+
1

,

L
–
1

,
2
\u03b1

L
,
1
\u2062

z
v
+
1

,
L
,
1
)
,
when a number of transmit antennas is two, wherein, Z(v+1) denotes the first matrix, i denotes an index representing blocks constituting the codeword, v denotes an index representing a time interval, j denotes an index representing a transmit antenna, L denotes a number of blocks constituting the codeword, and \u03b1i,j denotes a normalization weight multiplied to an ith block transmitted through a jth transmit antenna.
4. The method as claimed in claim 3, wherein generating the unitary space-time matrix from the first matrix by using the Gram-Schumidt scheme comprises:
setting respective nonzero column vectors of the first matrix as (v1, v2, v3, . . . , vL) and setting respective column vectors of the unitary space-time matrix as (u1, u2, u3, . . . , uL); and
generating a first column vector u1 of the unitary space-time matrix from the first column vector v1 of the first matrix as expressed by u1=k1v1, and generating a second column vector u2 to an Lth column vector uL of the unitary space-time matrix from the second column vector v2 to an Lth column vector vL of the first matrix as expressed by an =ki(vi\u2212<v1,u1>u1\u2212vi,u2>u2\u2212 . . . \u2212<vi,ui\u22121>ui\u22121),
wherein k1 exceeding zero (k1>0) must be selected so as to satisfy (|u1|=1).
5. The method as claimed in claim 4, wherein the first column vector u1 of the unitary space-time matrix is expressed by
u
1

=
k
1

\u2061

(
\u03b1
11

\u2062

z
v
+
1

,
1
,
1
\u03b1
12

\u2062

z
v
+
1

,
1
,
2
0
\u22ee
0
)
.
6. The method as claimed in claim 4, wherein an ith column vector ui of the unitary space-time matrix is expressed by an
u
i

=
k
i

\u2061

(
\u03b1

i
\u2062

\u2003

\u2062
1
\u2062

z
v
+
1

,
i
,
1
\u2062

u
(

i
–
1

)

\u2062
i

*

\u2062

u
(

i
–
1

)

\u2062
1
\u03b1

i
\u2062

\u2003

\u2062
1
\u2062

z
v
+
1

,
i
,
1
\u2062

u
(

i
–
1

)

\u2062
i

*

\u2062

u
(

i
–
1

)

\u2062
2
\u22ee
\u03b1

i
\u2062

\u2003

\u2062
1
\u2062
z
v
+
1

,
i
,
1
\u2061

(

1
–

E

u
(

i
–
1

)

\u2062
i
)
\u03b1

i
\u2062

\u2003

\u2062
2
\u2062

z
v
+
1

,
i
,
2
0
\u22ee
0
)
7. The method as claimed in claim 4, wherein the Lth column vector uL of the unitary space-time matrix is expressed by an
u
L

=
k
L

\u2061

(
\u03b1

L
\u2062

\u2003

\u2062
1
\u2062

z
v
+
1

,
L
,
1
\u2062

u
(

L
–
1

)

\u2062
L

*

\u2062

u
(

L
–
1

)

\u2062
1
\u03b1

L
\u2062

\u2003

\u2062
1
\u2062

z
v
+
1

,
L
,
1
\u2062

u
(

L
–
1

)

\u2062
L

*

\u2062

u
(

L
–
1

)

\u2062
2
\u22ee
\u03b1

L
\u2062

\u2003

\u2062
1
\u2062
z
v
+
1

,
L
,
1
\u2061

(

1
–

E

u
(

L
–
1

)

\u2062
L
)
)
.
8. The method as claimed in claim 4, wherein the normalization weight \u03b1i,j multiplied to a first block is expressed by an
|\u03b111|2|zv+1,1,1|=|\u03b112|2|zv+1,1,2|=0.5.
9. The method as claimed in claim 4, wherein the normalization weight \u03b1i,j multiplied to a second block to a (L\u22121)th block is expressed by an
\uf603

\u03b1

i
\u2062

\u2003

\u2062
1
\uf604

2

\u2062
\uf603

z
v
+
1

,
i
,
1
\uf604

2

\u2062

{
E

u
(

i
–
1

)

\u2062
i
\u2062
\u2211

j
=
1
i
–
1
\u2062

E

u
(

i
–
1

)

\u2062
i
+
(

1
–

E

u
(

i
–
1

)

\u2062
i
)

2
}
=
\uf603

\u03b1

i
\u2062

\u2003

\u2062
2
\uf604

2

\u2062
\uf603

z
v
+
1

,
i
,
2
\uf604

2
=
0.5
,
wherein, Eu(i\u22121)i denotes energy of u(i\u22121)i.
10. The method as claimed in claim 4, wherein the normalization weight \u03b1i,j multiplied to an Lth block is expressed by an
\uf603

\u03b1

L
\u2062

\u2003

\u2062
1
\uf604

2

\u2062
\uf603

z
v
+
1

,
L
,
1
\uf604

2

\u2062

{
E

u
(

L
–
1

)

\u2062
L
\u2062
\u2211

j
=
1
L
–
1
\u2062

E

u
(

L
–
1

)

\u2062
j
+
(

1
–

E

u
(

L
–
1

)

\u2062
L
)

2
}
=
1

,
wherein, Eu(i\u22121)i denotes energy of u(i\u22121)i.
11. A system for transmitting signals in a mobile communication system using a Multiple Input Multiple Output (MIMO) scheme, the system comprising:
a transmission matrix generator for, if a codeword to be transmitted in a first time-interval is input, generating a unitary space-time matrix to correspond to the codeword;
a multiplier for multiplying the unitary space-time matrix by a first final transmission matrix denoting signals transmitted in a second time interval before the first time interval, thereby generating a second final transmission matrix denoting signals to be transmitted in the second time interval; and
a Radio Frequency (RF) processor for transmitting signals corresponding to the second final transmission matrix through a plurality of transmit antennas in the second time interval.
12. The system as claimed in claim 11, wherein the transmission matrix generator generates a first matrix to correspond to the codeword, and generates the unitary space-time matrix from the first matrix by using a Gram-Schumidt scheme.
13. The system as claimed in claim 12, wherein the first matrix is expressed by
Z

v
+
1
=

(
\u03b1

1
,
1
\u2062

z
v
+
1

,
1
,
1
0
\u2026
0
0
\u03b1

1
,
2
\u2062

z
v
+
1

,
1
,
2
\u03b1

2
,
1
\u2062

z
v
+
1

,
2
,
1
\u2026
0
0
0
\u03b1

2
,
2
\u2062

z
v
+
1

,
2
,
2
\u2026
0
0
0
0
\u2026
0
0
\u22ee
\u22ee
\u22f0
\u22ee
\u22ee
0
0
\u2026
\u03b1
L
–
1

,
1
\u2062

z
v
+
1

,

L
–
1

,
1
0
0
0
\u2026
\u03b1
L
–
1

,
2
\u2062

z
v
+
1

,

L
–
1

,
2
\u03b1

L
,
1
\u2062

z
v
+
1

,
L
,
1
)
,
when a number of transmit antennas is two, wherein, Z(v+1) denotes the first matrix, i denotes an index representing blocks constituting the codeword, v denotes an index representing a time interval, j denotes an index representing a transmit antenna, L denotes a number of blocks constituting the codeword, and \u03b1i,j denotes a normalization weight multiplied to an ith block transmitted through a jth transmit antenna.
14. The system as claimed in claim 13, wherein transmission matrix generator sets respective nonzero column vectors of the first matrix as (v1, v2, v3, . . . , vL), sets respective column vectors of the unitary space-time matrix as (u1, u2, u3, . . . , uL), generates a first column vector uL of the unitary space-time matrix from the first column vector v1 of the first matrix as expressed by u1=k1v1, and generates a second column vector u2 to an Lth column vector UL of the unitary space-time matrix from the second column vector v2 to an Lth column vector vL of the first matrix as expressed by ui=ki(vi\u2212<v1,u1>u1\u2212vi,u2>u2\u2212 . . . \u2212<vi,ui\u22121>ui\u22121),
wherein k1 exceeding zero (k1>0) must be selected so as to satisfy (|u1|=1).
15. The system as claimed in claim 14, wherein the first column vector u1 of the unitary space-time matrix is expressed by
u
1

=
k
1

\u2061

(
\u03b1
11

\u2062

\u2003

\u2062

z
v
\u2062

\u2003

+

\u2003

\u2062
1

,

\u2003

\u2062
1
,

\u2003

\u2062
1
\u03b1
12

\u2062

\u2003

\u2062

z
v
\u2062

\u2003

+

\u2003

\u2062
1

,

\u2003

\u2062
1
,

\u2003

\u2062
2
0
\u22ee
0
)
.
16. The system as claimed in claim 14, wherein an ith column vector ui of the unitary space-time matrix is expressed by
u
i

=
k
i

\u2061

(
\u03b1

i
\u2062

\u2003

\u2062
1
\u2062

z
v
+
1

,
i
,
1
\u2062

u
(

i
–
1

)

\u2062
i

*

\u2062

u
(

i
–
1

)

\u2062
1
\u03b1

i
\u2062

\u2003

\u2062
1
\u2062

z
v
+
1

,
i
,
1
\u2062

u
(

i
–
1

)

\u2062
i

*

\u2062

u
(

i
–
1

)

\u2062
2
\u22ee
\u03b1

i
\u2062

\u2003

\u2062
1
\u2062
z
v
+
1

,
i
,
1
\u2061

(

1
–

E

u
(

i
–
1

)

\u2062
i
)
\u03b1

i
\u2062

\u2003

\u2062
2
\u2062

z
v
+
1

,
i
,
2
0
\u22ee
0
)
.
17. The system as claimed in claim 14, wherein the Lth column vector uL of the unitary space-time matrix is expressed by
u
L

=
k
L

\u2061

(
\u03b1

L
\u2062

\u2003

\u2062
1
\u2062

z
v
+
1

,
L
,
1
\u2062

u
(

L
–
1

)

\u2062
L

*

\u2062

u
(

L
–
1

)

\u2062
1
\u03b1

L
\u2062

\u2003

\u2062
1
\u2062

z
v
+
1

,
L
,
1
\u2062

u
(

L
–
1

)

\u2062
L

*

\u2062

u
(

L
–
1

)

\u2062
2
\u22ee
\u03b1

L
\u2062

\u2003

\u2062
1
\u2062
z
v
+
1

,
L
,
1
\u2061

(

1
–

E

u
(

L
–
1

)

\u2062
L
)
)
.
18. The system as claimed in claim 14, wherein a normalization weight \u03b1i,j multiplied to a first block is expressed by
|\u03b111|2|zv+1,1,1|=|\u03b112|2|zv+1,1,2|=0.5.
19. The system as claimed in claim 14, wherein a normalization weight \u03b1i,j multiplied to a second block to a (L\u22121)th block is expressed by
\uf603

\u03b1

i
\u2062

\u2003

\u2062
1
\uf604

2

\u2062
\uf603

z
v
+
1

,
i
,
1
\uf604

2

\u2062

{
E

u
(

i
–
1

)

\u2062
i
\u2062
\u2211

j
=
1
i
–
1
\u2062

E

u
(

i
–
1

)

\u2062
i
+
(

1
–

E

u
(

i
–
1

)

\u2062
i
)

2
}
=
\uf603

\u03b1

i
\u2062

\u2003

\u2062
2
\uf604

2

\u2062
\uf603

z
v
+
1

,
i
,
2
\uf604

2
=
0.5
,
wherein, Eu(i\u22121)i denotes energy of u(i\u22121)i.
20. The system as claimed in claim 14, wherein a normalization weight \u03b1i,j multiplied to an Lth block is expressed by
\uf603

\u03b1

L
\u2062

\u2003

\u2062
1
\uf604

2

\u2062
\uf603

z
v
+
1

,
L
,
1
\uf604

2

\u2062

{
E

u
(

L
–
1

)

\u2062
L
\u2062
\u2211

j
=
1
L
–
1
\u2062

E

u
(

L
–
1

)

\u2062
j
+
(

1
–

E

u
(

L
–
1

)

\u2062
L
)

2
}
=
1

,
wherein, Eu(i\u22121)i denotes energy of u(i\u22121)i.
21. A method for receiving signals by a receiver in a mobile communication system using a Multiple Input Multiple Output (MIMO) scheme, the method comprising:
if signals are received in a first time interval through a plurality of receive antennas, generating an equivalent channel matrix by using signals received in a second time interval before the first time interval; and
restoring a codeword, which has been transmitted from a transmitter corresponding to the receiver, from the received signals by using the equivalent channel matrix.
22. The method as claimed in claim 21, wherein a linear signal model in a first block is expressed by
\u2003

\u2062
x
v
+
1

,
1
,
1
x
v
+
1

,
1
,
2
\u22ee
x
v
+
1

,
1
,
M
\u2062

\u2003
=
1

2
\u2003

\u2062
x

v
,
1
,
1
x

v
,
2
,
1
x

v
,
1
,
2
x

v
,
2
,
2
\u22ee
\u22ee
x

v
,
1
,
M
x

v
,
2
,
M
\u2062

\u2003
\u2061
z
v
+
1

,
1
,
1
z
v
+
1

,
1
,
2
+
\u2003

\u2062
n
v
+
1

,
1
,
1
n
v
+
1

,
1
,
2
\u22ee
n
v
+
1

,
1
,
M
\u2062

\u2003
\u2261

H
v
+
1

,
1
,
when a number of receive antennas used in the receiver is M and a number of blocks constituting the codeword is L, wherein, v denotes an index representing a time interval, i denotes an index representing blocks constituting the codeword, j denotes an index representing a transmit antenna, p denotes an index representing a receive antenna, xv+1,i,p denotes an ith block received through a pth receive antenna in a (v+1)th time interval, nv+1,i,j denotes noise in the ith block received through the pth receive antenna in the (v+1)th time interval, zv+1,i,j denotes the ith block transmitted from the transmitter through a jth transmit antenna in the (v+1)th time interval, and Hv+1,1 denotes an equivalent channel matrix for the modulated symbols in the first block.
23. The method as claimed in claim 21, wherein a linear signal model in a second block to a (L\u22121)th block is expressed by
\u2003

\u2062
x
v
\u2062

\u2003

+

\u2003

\u2062
1

,

\u2003

\u2062
i
,

\u2003

\u2062
1
x
v
\u2062

\u2003

+

\u2003

\u2062
1

,

\u2003

\u2062
i
,

\u2003

\u2062
2
\u22ee
x
v
\u2062

\u2003

+

\u2003

\u2062
1

,

\u2003

\u2062
i
,

\u2003

\u2062
M
\u2062

\u2003
=

\u2062
\u2003

\u2062
–
\u2211

j
=
1
i
–
1
\u2062
x

v
,
j
,
1
\u2062

u
(

i
–
1

)

\u2062
i

*

\u2062

u
(

i
–
1

)

\u2062
j
+
x

v
,
i
,
1
\u2061

(

1
–

E

u
(

i
–
1

)

\u2062
i
)
\u2062

1

2
\u2062

x

v
,
2
,
1
–
\u2211

j
=
1
i
–
1
\u2062
x

v
,
j
,
2
\u2062

u
(

i
–
1

)

\u2062
i

*

\u2062

u
(

i
–
1

)

\u2062
j
+
x

v
,
i
,
2
\u2062

(

1
–

E

u
(

i
–
1

)

\u2062
i
)
\u2062

1

2
\u2062

x

v
,
2
,
2
\u22ee
–
\u2211

j
=
1
i
–
1
\u2062
x

v
,
j
,
M
\u2062

u
(

i
–
1

)

\u2062
i

*

\u2062

u
(

i
–
1

)

\u2062
j
+
x

v
,
i
,
M
\u2062

(

1
–

E

u
(

i
–
1

)

\u2062
i
)
\u2062

1

2
\u2062

x

v
,
2
,
M
\u2062

\u2003
\u2062
z
v
+
1

,
i
,
1
z
v
+
1

,
i
,
2
+
\u2062
\u2003

\u2062
n
v
+
1

,
i
,
1
n
v
+
1

,
i
,
2
\u22ee
n
v
+
1

,
i
,
M
\u2062

\u2003
\u2261

H
\u2003

\u2062
v
\u2062

\u2003

+

\u2003

\u2062
1

,

\u2003

\u2062
i
when a number of receive antennas used in the receiver is M and a number of blocks constituting the codeword is L,
wherein, v denotes an index representing a time interval, i denotes an index representing blocks constituting the codeword, j denotes an index representing a transmit antenna, p denotes an index representing a receive antenna, xv+1,i,p denotes an ith block received through a pth receive antenna in a (v+1)th time interval, nv+1,i,j denotes noise in the ith block received through the pth receive antenna in the (v+1)th time interval, zv+1,i,j denotes the ith block transmitted from the transmitter through a jth transmit antenna in the (v+1)th time interval, Hv+1,i denotes an equivalent channel matrix for the modulated symbols in the i-th block, and Eu(i\u22121)i denotes energy of u(i\u22121)i.
24. The method as claimed in claim 21, wherein a linear signal model in a second block to a Lth block is expressed by
\u2003

\u2062
x
v
\u2062

\u2003

+

\u2003

\u2062
1

,

\u2003

\u2062
L
,

\u2003

\u2062
1
x
v
\u2062

\u2003

+

\u2003

\u2062
1

,

\u2003

\u2062
L
,

\u2003

\u2062
2
\u22ee
x
v
\u2062

\u2003

+

\u2003

\u2062
1

,

\u2003

\u2062
L
,

\u2003

\u2062
M
\u2062

\u2003
=

\u2062
\u2003

\u2062
–
\u2211

j
=
1
L
–
1
\u2062
x

v
,
j
,
1
\u2062

u
(

L
–
1

)

\u2062
L

*

\u2062

u
(

i
–
1

)

\u2062
j
+
x

v
,
L
,
1
\u2061

(

1
–

E

u
(

L
–
1

)

\u2062
L
)
–
\u2211

j
=
1
L
–
1
\u2062
x

v
,
j
,
2
\u2062

u
(

L
–
1

)

\u2062
L

*

\u2062

u
(

L
–
1

)

\u2062
j
+
x

v
,
L
,
2
\u2062

(

1
–

E

u
(

L
–
1

)

\u2062
L
)
\u22ee
–
\u2211

j
=
1
L
–
1
\u2062
x

v
,
j
,
M
\u2062

u
(

L
–
1

)

\u2062
L

*

\u2062

u
(

L
–
1

)

\u2062
j
+
x

v
,
L
,
M
\u2062

(

1
–

E

u
(

L
–
1

)

\u2062
L
)
\u2062

\u2003
\u2062

z
v
+
1

,
L
,
1
+
\u2062
\u2003

\u2062
n
v
+
1

,
L
,
1
n
v
+
1

,
L
,
2
\u22ee
n
v
+
1

,
L
,
M
\u2062

\u2003
\u2261

H
\u2003

\u2062
v
\u2062

\u2003

+

\u2003

\u2062
1

,

\u2003

\u2062
L
when a number of receive antennas used in the receiver is M and a number of blocks constituting the codeword is L, wherein, v denotes an index representing a time interval, i denotes an index representing blocks constituting the codeword, j denotes an index representing a transmit antenna, p denotes an index representing a receive antenna, xv+1,i,p denotes an ith block received through a pth receive antenna in a (v+1)th time interval, nv+1,i,j denotes noise in the ith block received through the pth receive antenna in the (v+1)th time interval, zv+1,i,j denotes the ith block transmitted from the transmitter through a jth transmit antenna in the (v+1)th time interval, Hv+1,L denotes an equivalent channel matrix for the modulated symbol in the L-th block, and Eu(L\u22121)L denotes energy of u(L\u22121)L.
25. A system for receiving signals in a mobile communication system using a Multiple Input Multiple Output (MIMO) scheme, the system comprising:
an equivalent channel matrix generator for, if signals are received in a first time interval through a plurality of receive antennas, generating an equivalent channel matrix by using signals received in a second time before the first time interval; and
a MIMO detector for restoring a codeword, which has been transmitted from a transmitter corresponding to the receiver, from the received signals by using the equivalent channel matrix.
26. The system as claimed in claim 25, wherein a linear signal model in a first block is expressed by
x
v
+
1

,
1
,
1
x
v
+
1

,
1
,
2
\u22ee
x
v
+
1

,
1
,
M
\u2062

\u2003
=
1

2
\u2003

\u2062
x

v
,
1
,
1
x

v
,
2
,
1
x

v
,
1
,
2
x

v
,
2
,
2
\u22ee
\u22ee
x

v
,
1
,
M
x

v
,
2
,
M
\u2062

\u2003
\u2061
z
v
+
1

,
1
,
1
z
v
+
1

,
1
,
2
+
\u2003

\u2062
n
v
+
1

,
1
,
1
n
v
+
1

,
1
,
2
\u22ee
n
v
+
1

,
1
,
M
\u2062

\u2003
\u2261

H
v
+
1

,
1
when a number of receive antennas used in the receiver is M and a number of blocks constituting the codeword is L, wherein, v denotes an index representing a time interval, i denotes an index representing blocks constituting the codeword, j denotes an index representing a transmit antenna, p denotes an index representing a receive antenna, xv+1,i,p denotes an ith block received through a pth receive antenna in a (v+1)th time interval, nv+1,i,j denotes noise in the ith block received through the pth receive antenna in the (v+1)th time interval, zv+1,i,j denotes the ith block transmitted from the transmitter through a jth transmit antenna in the (v+1)th time interval, and Hv+1,1 denotes an equivalent channel matrix for the modulated symbols for the first block.
27. The system as claimed in claim 25, wherein a linear signal model in a second block to a (L\u22121)th block is expressed by
\u2003

\u2062
x
v
\u2062

\u2003

+

\u2003

\u2062
1

,

\u2003

\u2062
i
,

\u2003

\u2062
1
x
v
\u2062

\u2003

+

\u2003

\u2062
1

,

\u2003

\u2062
i
,

\u2003

\u2062
2
\u22ee
x
v
\u2062

\u2003

+

\u2003

\u2062
1

,

\u2003

\u2062
i
,

\u2003

\u2062
M
\u2062

\u2003
=

\u2062
\u2003

\u2062
–
\u2211

j
=
1
i
–
1
\u2062
x

v
,
j
,
1
\u2062

u
(

i
–
1

)

\u2062
i

*

\u2062

u
(

i
–
1

)

\u2062
j
+
x

v
,
i
,
1
\u2061

(

1
–

E

u
(

i
–
1

)

\u2062
i
)
\u2062

1

2
\u2062

x

v
,
2
,
1
–
\u2211

j
=
1
i
–
1
\u2062
x

v
,
j
,
2
\u2062

u
(

i
–
1

)

\u2062
i

*

\u2062

u
(

i
–
1

)

\u2062
j
+
x

v
,
i
,
2
\u2062

(

1
–

E

u
(

i
–
1

)

\u2062
i
)
\u2062

1

2
\u2062

x

v
,
2
,
2
\u22ee
–
\u2211

j
=
1
i
–
1
\u2062
x

v
,
j
,
M
\u2062

u
(

i
–
1

)

\u2062
i

*

\u2062

u
(

i
–
1

)

\u2062
j
+
x

v
,
i
,
M
\u2062

(

1
–

E

u
(

i
–
1

)

\u2062
i
)
\u2062

1

2
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x

v
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v
+
1

,
i
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1
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2
+
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v
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1

,
i
,
1
n
v
+
1

,
i
,
2
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v
+
1

,
i
,
M
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H
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v
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+

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1

,

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i
when a number of receive antennas used in the receiver is M and a number of blocks constituting the codeword is L, wherein, v denotes an index representing a time interval, i denotes an index representing blocks constituting the codeword, j denotes an index representing a transmit antenna, p denotes an index representing a receive antenna, xv+1,i,p denotes an ith block received through a pth receive antenna in a (v+1)th time interval, nv+1,i,j denotes noise in the ith block received through the pth receive antenna in the (v+1)th time interval, zv+1,i,j denotes the ith block transmitted from the transmitter through a jth transmit antenna in the (v+1)th time interval, Hv+1,i denotes an equivalent channel matrix for the modulated symbol in the i-th block, and Eu(i\u22121)i denotes energy of u(i\u22121)i.
28. The system as claimed in claim 25, wherein a linear signal model in a second block to a Lth block is expressed by
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=

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)
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+

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1

,

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L
when a number of receive antennas used in the receiver is M and a number of blocks constituting the codeword is L, wherein, v denotes an index representing a time interval, i denotes an index representing blocks constituting the codeword, j denotes an index representing a transmit antenna, p denotes an index representing a receive antenna, xv+1,i,p denotes an ith block received through a pth receive antenna in a (v+1)th time interval, nv+1,i,j denotes noise in the ith block received through the pth receive antenna in the (v+1)th time interval, zv+1,i,j denotes the ith block transmitted from the transmitter through a jth transmit antenna in the (v+1)th time interval, Hv+1,L denotes an equivalent channel matrix for the modulated symbol in the L-th block, and Eu(L\u22121)L denotes energy of u(L\u22121)L.