All The Claims

1. A turbidity head for a turbidity sensor or probe comprising:
a light source providing an outgoing light ray toward a fluid sample;
a detector capable of detecting an incoming light ray reflected from the fluid sample;
an isolator separating the light source from the detector portion; and
a first reflector in the path of either the outgoing light ray or the incoming light ray;
wherein the first reflector is positioned to reflect either the outgoing light ray or the incoming light ray to achieve a measurement angle defined between the outgoing light ray and the incoming light ray of ninety degrees plus-or-minus two and a half degrees.
2. The turbidity head of claim 1, wherein the first reflector is positioned at a tilt angle between 0\xb0 to 45\xb0.
3. The turbidity head of claim 2 wherein the first reflector is positioned at a tilt angle between about 10\xb0 to about 30\xb0.
4. The turbidity head of claim 1, wherein the first reflector includes a prism, a reflective film, a reflective coating, and combinations thereof.
5. The turbidity head of claim 4, wherein the first reflector is a prism having one reflective side.
6. The turbidity head of claim 5, wherein the first reflector is positioned to reflect the outgoing light ray and a second reflector is positioned to reflect the incoming light ray.
7. The turbidity head of claim 5, wherein the reflective side includes the reflective coating or the reflective film thereon.
8. The turbidity head of claim 1, wherein the first reflector is positioned such that the incident angle is less than the critical angle.
9. The turbidity head of claim 1, wherein the turbidity head has a central longitudinal axis and whichever of the light source or the photo detector is in the path of the first reflector has a central longitudinal axis that is generally parallel to the central longitudinal axis of the turbidity head.
10. The turbidity head of claim 9, wherein the reflector is a parallelepiped prism, the prism being positioned at a tilt angle between 0\xb0 to 45\xb0 that places the second end of the prism closer to the central longitudinal axis of the turbidity head than the first end of the prism.
11. The turbidity head of claim 1, further comprising a housing having a maximum diameter of about 13 mm, the housing enclosing the light source, the photodetector, the isolator, and the first reflector.
12. The turbidity head of claim 11, wherein the housing is a cap having a closed end that includes an optics aperture.
13. The turbidity head of claim 4, wherein the first reflector is a reflective film.
14. The turbidity head of claim 13, wherein the first reflector is positioned to reflect the outgoing light ray and a second reflector is positioned to reflect the incoming light ray.
15. The turbidity head of claim 1, wherein the turbidity head has a central longitudinal axis and whichever of the light source or the photo detector that does not include the reflector has a central longitudinal axis that is oriented at about a 5\xb0 to about a 60\xb0 angle to the central longitudinal axis of the turbidity head.
16. A turbidity sensor comprising:
a watertight housing that houses a light source providing an outgoing light ray toward a fluid sample, a detector capable of detecting an incoming light ray reflected from the fluid sample, an isolator separating the light source from the detector portion, a first reflector in the path of either the outgoing light ray or the incoming light ray, and a circuit board electrically coupled to the light source and the detector;
wherein the first reflector is positioned to reflect either the outgoing light ray or the incoming light ray to achieve a measurement angle defined between the outgoing light ray and the incoming light ray of ninety degrees plus-or-minus two and a half degrees.
17. The turbidity sensor of claim 16, further comprising an electrical connector electrically coupled to the circuit board, the electrical connector being capable of electrically coupling the circuit board to a water monitoring device.
18. The turbidity sensor of claim 17, wherein the electrical connector is a wet mateable connector.
19. The turbidity sensor of claim 16, wherein the water tight housing includes a cap that covers an optics receptacle that receives the light source, the photodetector, and the reflector.
20. The turbidity sensor of claim 16, further comprising a second reflector, wherein the first reflector is positioned to reflect the outgoing light ray and the second reflector is positioned to reflect the incoming light ray.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An exhaust silencer assembly, comprising:
an eductor disposed downstream of an auxiliary power unit and including an entrance opening at a forward axial end thereof, the entrance opening configured to receive exhaust airflow from the auxiliary power unit;
an acoustic-attenuating porous liner disposed within an interior of the eductor axially downstream of the entrance opening, the porous liner separating a radially outer plenum from a radially inner plenum of the eductor;
a discharge pipe extending from the auxiliary power unit and communicating with the exhaust silencer assembly downstream of the entrance opening of the educator, wherein the discharge pipe extends through both an outer casing of the eductor and the porous liner; and
an air inlet duct secured to the eductor and communicating with the outer plenum of the eductor via a cooling air inlet opening therein.
2. The exhaust silencer assembly of claim 1, wherein the eductor receives a by-pass airflow from the discharge pipe, a cooling airflow from the air inlet duct, and exhaust airflow from the auxiliary power unit and includes a plurality of mixing zones where the airflows are mixed therein.
3. The exhaust silencer assembly of claim 1, wherein the eductor includes a by-pass plenum disposed forward of the outer plenum, the by-pass plenum communicates with the discharge pipe and includes an opening to the inner plenum that is disposed downstream of the entrance opening of the eductor.
4. The exhaust silencer assembly of claim 1, wherein the eductor includes a by-pass plenum disposed aft of the outer plenum, the by-pass plenum communicates with the discharge pipe and includes an opening to the inner plenum that is disposed downstream of the entrance opening of the eductor.
5. An assembly, comprising:
an auxiliary power unit;
an eductor disposed downstream of the auxiliary power unit and including an entrance opening at a forward axial end thereof, the entrance opening configured to receive exhaust airflow from the auxiliary power unit, the eductor including a cooling air inlet opening therein and an acoustic-attenuating porous liner disposed within an interior thereof;
a discharge pipe extending from the auxiliary power unit and communicating with the eductor downstream of the entrance opening; and
an air inlet duct secured to the eductor and communicating with the interior thereof via the cooling air inlet opening;
wherein the eductor receives a by-pass airflow from the discharge pipe, a cooling airflow from the air inlet duct, and exhaust airflow from the auxiliary power unit.
6. The assembly of claim 5, further comprising a heat exchanger disposed along the air inlet duct.
7. The assembly of claim 5, wherein the assembly is disposed in the tail section of an aircraft.
8. The assembly of claim 5, wherein the discharge pipe extends through both an outer casing of the eductor and the porous liner.
9. The assembly of claim 6, wherein the eductor includes a by-pass plenum disposed at a forward end thereof, the by-pass plenum communicates with the discharge pipe and includes an opening to the remainder of the eductor that is disposed downstream of the entrance opening.
10. The assembly of claim 5, wherein the eductor includes a by-pass plenum disposed at an aft end thereof, the by-pass plenum communicates with the discharge pipe and includes an opening to the remainder of the eductor that is disposed downstream of the entrance opening.
11. The assembly of claim 5, further comprising a by-pass plenum disposed forward of the eductor, the by-pass plenum communicates with the discharge pipe and includes an opening that is disposed at or downstream of the termination of a turbine flow casing.
12. The assembly of claim 5, further comprising an exhaust duct and wherein the discharge pipe communicates directly with the exhaust duct downstream of the eductor.
13. An exhaust silencer assembly, comprising:
an eductor disposed downstream of an auxiliary power unit and including an entrance opening at a forward axial end thereof, the entrance opening configured to receive exhaust airflow from the auxiliary power unit;
an acoustic-attenuating porous liner disposed within an interior of the eductor axially downstream of the entrance opening, the porous liner separating a radially outer plenum from a radially inner plenum of the eductor;
an exhaust duct downstream of the eductor, the exhaust duct configured to receive airflow from the eductor; and
a discharge pipe extending from the auxiliary power unit and communicating with the exhaust duct downstream of the eductor.
14. The exhaust silencer assembly of claim 13, wherein the exhaust duct receives a by-pass airflow from the discharge pipe and a by-pass mixing zone occurs downstream of the eductor in the exhaust duct.
15. The exhaust silencer assembly of claim 13, wherein the eductor includes an air inlet duct secured to the eductor and communicating with the outer plenum of the eductor via a cooling air inlet opening.
16. The exhaust silencer assembly of claim 1, wherein the eductor includes a by-pass plenum that communicates with the discharge pipe and includes an opening to the remainder of the eductor that is disposed downstream of the entrance opening.
17. An exhaust silencer assembly, comprising:
an eductor disposed downstream of an auxiliary power unit including an entrance opening configured to receive exhaust airflow from the auxiliary power unit;
an acoustic-attenuating porous liner disposed within an interior of the eductor axially downstream of the entrance opening, the porous liner separating a radially outer plenum from a radially inner plenum of the eductor;
a cooling air inlet opening in the eductor;
a discharge pipe extending from the auxiliary power unit and communicating with the eductor downstream of the entrance opening; and
an annular by-pass plenum within the eductor, the by-pass plenum communicates with the discharge pipe.

1. A non-volatile semiconductor memory device comprising:
a memory cell array having electrically rewritable and non-volatile semiconductor memory cells arranged therein; and a sense amplifier circuit configured to read data of and hold data to be written into the memory cell array,
the device being internally controlled to execute a write sequence with write pulse applications and write-verify operations repeated for writing a set of memory cells selected in the memory cell array,
wherein the sense amplifier circuit performs, after a certain write pulse application at the beginning of the write sequence, a write speed verify operation for detecting write speed of plural memory cells to be written into a certain data state, thereby getting discriminating data for classifying the plural memory cells into first and second cell groups,
the write speed of the memory cell in the second cell group being lower than that in the first cell group, and wherein
after the write speed verify operation, the first and second cell groups are alternately written on different write conditions from each other with reference to the discriminating data.
2. The non-volatile semiconductor memory device according to claim 1, wherein
a first write pulse application for writing the first cell group and a second write pulse application for writing the second cell group are sequentially performed, the first and second write pulses being different in voltage from each other, following it a write verify operation is performed for both of the first and second cell groups on the same condition at a time.
3. The non-volatile semiconductor memory device according to claim 1, wherein
after the write speed verify operation, write data transferred to the first and second cell groups are alternately inverted based on the discriminating data held in the sense amplifier circuit.
4. The non-volatile semiconductor memory device according to claim 1, wherein
after the write-verify operation, a write-completion detection is performed for detecting whether the entire selected memory cells have been written or not.
5. The non-volatile semiconductor memory device according to claim 4, wherein
the write-completion detection is performed during the write pulse application.
6. The non-volatile semiconductor memory device according to claim 1, wherein
after the write verify operation, write-completion detections are performed with respect to the first and second cell groups, respectively, for detecting whether the memory cells have been written or not, and after the write-completion has been detected for one cell group, the write pulse application is successively performed for only the other cell group.
7. The non-volatile semiconductor memory device according to claim 6, wherein
the write-completion detections are performed during the write pulse applications for the first and second cell groups, respectively.
8. The non-volatile semiconductor memory device according to claim 1, wherein
the memory cell array has NAND cell units arranged therein, each NAND cell unit having plural memory cells connected in series and select gate transistors disposed at the both ends thereof.
9. The non-volatile semiconductor memory device according to claim 1, wherein
the sense amplifier circuit has plural sense units for simultaneously reading data of or simultaneously writing data into the set of memory cells selected in the memory cell array, and wherein each the sense unit includes:
a first data latch, in which write data is loaded;
a write-back circuit disposed in association with the first data latch for writing-back write data of the next write cycle into the first data latch based on the write verify-read data;
a second data latch disposed in parallel with the first data latch, to which the write data loaded in the first data latch is transferred at the beginning of the write sequence, and the discriminating data obtained by the write speed verify operation is held in;
a write speed switching circuit disposed in association with the second data latch, which serves for switching bit line control voltage for the purpose of alternately writing the first and second cell groups based on the discriminating data held in the second data latch; and
a bit line drive circuit, which is so controlled by data held in the first and second data latches as to generate a bit line control voltage required at a data write time in corporation with the write speed switching circuit.
10. The non-volatile semiconductor memory device according to claim 9, further comprising a write-completion detection circuit, which checks write data held in the first data latch with reference to the discriminating data held in the second data latch in each the sense unit to detect write-completion for each of the first and second cell groups.
11. The non-volatile semiconductor memory device according to claim 10, wherein the write-completion detection circuit has plural completion detection units for detecting write-completion in the entire sense units, each write-completion detection unit serving for detecting write-completion in plural sense units.
12. The non-volatile semiconductor memory device according to claim 1, wherein
the write sequence is for writing at least two, first and second, data states simultaneously into the set of memory cells, and wherein
the sense amplifier circuit performs a write speed verify operation for detecting write speed of plural memory cells to be written into at least the first data state after a certain write pulse application at the beginning of the write sequence, thereby getting discriminating data for classifying the plural memory cells into first and second cell groups, the write speed of the memory cell in the second cell group being lower than that in the first cell group, and wherein
after the write speed verify operation, the first and second cell groups are alternately written on different write conditions from each other with reference to the discriminating data.
13. The non-volatile semiconductor memory device according to claim 12, wherein
the first and second data states are defined by a first threshold distribution and a second threshold distribution higher than the first threshold distribution, respectively;
in the write cycle of the first data state, the first and second cell groups are alternately written with first and second write pulses each sequentially stepped-up, the second write pulses being higher than the first write pulses, and a first write-verify operation is performed after each of the first and second write pulse applications on the same condition at a time; and wherein
data write in the former half of a write cycle of the second data state is performed with the second write pulses in the write cycle of the first data state, and a second write-verify operation thereof is performed as following the first write verify operation while data write in the latter half thereof is performed with third write pulses as following the second write pulses and third write-verify operations repeated.
14. The non-volatile semiconductor memory device according to claim 13, wherein
write-completion detections for the first data state are performed during the first and second write pulse applications for the first and second cell groups, respectively, within the memory cells to be written into the first data state in the write cycle of the first data state; and wherein
write-completion detections for the second data state are performed during each the second write pulse application in the former half while during each the third write pulse application in the latter half.
15. The non-volatile semiconductor memory device according to claim 1, wherein
the write sequence is for writing at least three, first, second and third, data states simultaneously into the set of memory cells, the three data states being arranged in order of the threshold voltage height, and wherein
the sense amplifier circuit performs a first write speed verify operation for detecting write speed of memory cells to be written into the first data state after a certain write pulse application at the beginning of the write sequence, thereby getting first discriminating data for classifying the memory cells into first and second cell groups, the write speed of the memory cell in the second cell group being lower than that in the first cell group, and performs a second write speed verify operation for detecting write speed of memory cells to be written into the third data state halfway in the write sequence, thereby getting second discriminating data for classifying the memory cells into third and fourth cell groups, the write speed of the fourth cell group being lower than that in the third cell group;
in the former half of the write sequence, the first and second cell groups are alternately written with first and second write pulses, respectively, in the memory cells to be written into the first data state with reference to the first discriminating data, the second write pulses being higher than the first write pulses;
in the latter half of the write sequence, the third and fourth cell groups are alternately written with third and fourth write pulses, respectively, in the memory cells to be written into the third data state with reference to the second discriminating data, the fourth write pulses being higher than the third write pulses; and
the second write pulses applied to the second cell group and the third write pulses applied to the third cell group are used for writing the memory cells to be written into the second data state.
16. The non-volatile semiconductor memory device according to claim 1, wherein the write speed in the write speed verify operation is determined by detecting a threshold voltage shift state of the memory cells.
17. A method of writing data into a set of memory cells in a non-volatile semiconductor memory device with write pulse applications and write-verify operations repeated, comprising:
performing, after a certain write pulse application at the beginning of a write sequence, a write speed verify operation for detecting write speed of plural memory cells to be written into a certain data state, thereby getting discriminating data for classifying the plural memory cells into first and second cell groups, the write speed of the memory cell in the second cell group being lower than that in the first cell group; and
alternately writing the first and second cell groups on different write conditions from each other with reference to the discriminating data after the write speed verify operation.
18. The method of writing data according to claim 17, wherein
the write sequence is for writing at least two, first and second, data states simultaneously into the set of memory cells;
the write speed verify operation is performed for detecting write speed of memory cells to be written into at least the first data state;
with respect to the memory cells to be written into the first data state, the first and second cell groups are alternately written with first and second write pulses, respectively, which are stepped-up as being different from each, with reference to the discriminating data, after the write speed verify operation; and
memory cells to be written into the second data state are written with the second write pulses simultaneously with the second cell group, and successively written with third write pulses stepped-up.
19. The method of writing data according to claim 17, wherein the write sequence is for writing at least three, first, second and third, data states simultaneously into the set of memory cells, the three data states being arranged in order of the threshold voltage height;
a first write speed verify operation is performed for detecting write speed of memory cells to be written into the first data state after a certain write pulse application at the beginning of the write sequence, so as to get first discriminating data for classifying the memory cells into first and second cell groups, the write speed of the memory cell in the second cell group being lower than that in the first cell group;
in the former half of the write sequence, the first and second cell groups are alternately written with first and second write pulses, respectively, in the memory cells to be written into the first data state with reference to the first discriminating data, the second write pulses being higher than the first write pulses;
a second write speed verify operation is performed for detecting write speed of memory cells to be written into the third data state halfway in the write sequence, so as to get second discriminating data for classifying the memory cells into third and fourth cell groups, the write speed of the fourth group being lower than that in the third cell group;
in the latter half of the write sequence, the third and fourth cell groups are alternately written with third and fourth write pulses, respectively, in the memory cells to be written into the third data state with reference to the second discriminating data, the fourth write pulses being higher than the third write pulses; and
the second write pulses applied to the second cell group and the third write pulses applied to the third cell group are used for writing the memory cells to be written into the second data state.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for estimating a position where noise enters a telecommunications transmission line said line having first digital subscriber line (DSL) communications equipment connected to a first end of the line and second DSL communications equipment connected to a second, opposite end of the line the method comprising the following steps:
receiving, via the line, a first result of a measurement of a noise level at the first end of the transmission line made by the first DSL equipment;
receiving a second result of a measurement of a noise level at the second end of the transmission line made by the second DSL equipment; and
generating an estimate of the position where the noise enters the transmission line based on the relationship between the first and the second noise level measurement results where the first and second noise level measurements are made at the same frequency or frequency band and said frequency or frequency band falls within a transmit band of at least one of said first and second DSL equipment.
2. The method according to claim 1 wherein a position estimate is generated as
d
R

=
1
2
d
+

(
N
R

\u2061

(
f
)
–
N
O

\u2061

(
f
)
)
)

\u2062

d

H
\u2061

(
f
)
where dR is a distance from the first end to the estimated position, d is a length of the line from the first end to the second end, NR(f) is the measured first result of the measurement of the noise level at the first end at frequency f, NO(f) is the second result of the measurement of the noise level at the second end at said frequency f, and H(f) is the magnitude of the transmission line’s transfer function from the first end to the second end at said frequency f.
3. The method according to claim 2, wherein the position estimate is generated for different frequencies and a further position estimate is generated as an average of the position estimates generated for the different frequencies.
4. The method according to claim 1, further comprising the step of generating an estimate of a noise power spectral distribution at the position where the noise enters the line, based on the relationship between the first and the second noise level measurement results.
5. The method according to claim 4 wherein the estimate of the noise power spectral distribution (PSD) is generated as
N
\u2061

(
f
)
=
N
R

\u2061

(
f
)
–
d
R

d

\u2062
H
\u2061

(
f
)
.
6. The method according to claim 1, wherein the first DSL equipment is a xDSL consumer premises equipment (CPE).
7. The method according to claim 1, wherein the second DSL equipment is a xDSL digital subscriber line access multiplexer (DSLAM).
8. The method according to claim 6, where xDSL is very high bit rate digital subscriber line (VDSL2).
9. A device for estimating a position where noise enters a telecommunications transmission line said line having first digital subscriber line (DSL) communications equipment connected to a first end of the line and second DSL communications equipment connected to a second end, opposite to the first end of the line, the device comprising:
means for receiving, via the line, a first result of a measurement of a noise level at the first end of the transmission line made by the first DSL equipment;
means for receiving a second result of a measurement of a noise level at the second end of the transmission line made by the second DSL equipment; and
means for generating an estimate of the position where the noise enters the transmission line based on the relationship between the first and the second noise level measurement results where the first and second noise level measurements are made at the same frequency or frequency band and said frequency or frequency band falls within a transmit band of at least on of said first and second DSL equipments.
10. The device according to claim 9, further having means for generating an estimate of a noise power spectral distribution at the position where the noise enters the line, based on the relationship between the first and the second noise level measurement results.
11. A DSL communications equipment having a plurality of transmit bands and adapted for use with the method of claim 1, wherein the DSL communications equipment is adapted to measure quiet line noise (QLN) in at least one of the transmit bands.
12. The equipment according to claim 11 being adapted to measure the QLN at a plurality of frequencies used for reception or transmission of data.
13. The equipment according to claim 11, wherein the equipment is a xDSL consumer premises equipment (CPE).
14. The equipment according to claim 11, wherein the equipment is a xDSL digital subscriber line access multiplexer (DSLAM).
15. The equipment according to claim 13, wherein xDSL is very high bit rate digital subscriber line (VDSL2).
16. The equipment according to claim 11, wherein said equipment is adapted to make said transmit band QLN measurement in a passband of a filter through which the measurement is made.
17. The method of claim 1, further comprising:
measuring, by the DSL communications equipment having a plurality of transmit bands, quiet line noise (QLN) in at least one of the transmit bands.
18. The method according to claim 17 wherein the QLN is measured at a plurality of frequencies used for reception or transmission of data.
19. The method according to claim 17, wherein said transmit band QLN measurement is made in a passband of a filter through which the measurement is made.
20. A method of estimating a position where noise enters a telecommunications transmission line, the method comprising the steps of:
measuring a first noise level at a first frequency or frequency band at a first end of the transmission line by a digital subscriber line (DSL) consumer premises equipment (CPE);
communicating the measured first noise level over the line to a digital subscriber line access multiplexer (DSLAM) at a second end of the transmission line, opposite the first end;
measuring a second noise level at the first frequency or frequency band at the second end by the DSLAM; and
estimating, based on the relationship between the first and second noise level, the position where the noise enters the transmission line wherein said first frequency or frequency band falls within a transmit band of at least one of said CPE and said DSLAM.