All The Claims

1. A piezoelectric micromechanical ultrasonic transducer (PMUT) comprising:
a multilayer stack disposed on a substrate and including:
an anchor structure disposed over the substrate;
a piezoelectric layer stack disposed over the anchor structure; and
a mechanical layer disposed proximate to the piezoelectric layer stack;

wherein:
the piezoelectric layer stack is disposed over a cavity; and
the mechanical layer seals the cavity and, together with the piezoelectric layer stack, is supported by the anchor structure and forms a membrane over the cavity, the membrane being configured to undergo one or both of flexural motion and vibration when the PMUT receives or transmits ultrasonic signals.
2. The PMUT of claim 1, wherein the mechanical layer has a thickness such that a neutral axis of the multilayer stack is displaced, relative to a neutral axis of the piezoelectric layer stack, towards the mechanical layer to allow an out-of-plane bending mode.
3. The PMUT of claim 2, wherein the mechanical layer is substantially thicker than the piezoelectric layer stack.
4. The PMUT of claim 2, wherein the neutral axis passes through the mechanical layer.
5. The PMUT of claim 1, wherein:
the cavity is formed by removing a sacrificial material through at least one release hole;
the mechanical layer is formed after removing the sacrificial material; and
forming the mechanical layer seals the cavity by sealing the at least one release hole.
6. The PMUT of claim 1, wherein the piezoelectric layer stack includes a piezoelectric layer, a lower electrode disposed below the piezoelectric layer, and an upper electrode disposed above the piezoelectric layer.
7. The PMUT of claim 1, wherein the mechanical layer includes a recess where the mechanical layer is locally thinned.
8. The PMUT of claim 1, wherein the mechanical layer is disposed over a side of the piezoelectric stack opposite to the substrate.
9. The PMUT of claim 1, wherein the mechanical layer is disposed below a side of the piezoelectric stack facing the substrate.
10. The PMUT of claim 1, further comprising an acoustic coupling medium disposed above the piezoelectric layer stack, wherein the PMUT is configured to receive or transmit ultrasonic signals through the coupling medium.
11. A piezoelectric micromechanical ultrasonic transducer (PMUT) comprising:
a multilayer stack disposed on a substrate and including:
an anchor structure disposed over the substrate;
a piezoelectric layer stack disposed over the anchor structure; and
a mechanical layer disposed proximate to the piezoelectric layer stack, the mechanical layer including a recess where the mechanical layer is locally thinned; wherein
the piezoelectric layer stack is disposed over a cavity; and
the mechanical layer, together with the piezoelectric layer stack, is supported by the anchor structure and forms a membrane over the cavity, the membrane being configured to undergo one or both of flexural motion and vibration when the PMUT receives or transmits ultrasonic signals.
12. The PMUT of claim 11, wherein:
the cavity is formed by removing a sacrificial material through at least one release hole;
the mechanical layer is formed after removing the sacrificial material; and
forming the mechanical layer seals the cavity by sealing the at least one release hole.
13. The PMUT of claim 11, wherein the mechanical layer is disposed over a side of the piezoelectric stack opposite to the substrate.
14. The PMUT of claim 11, wherein the mechanical layer is disposed below a side of the piezoelectric stack facing the substrate.
15. The PMUT of claim 11, further comprising an acoustic coupling medium disposed above the piezoelectric layer stack, wherein the PMUT is configured to receive or transmit ultrasonic signals through the coupling medium.
16. A method of making a piezoelectric micromechanical ultrasonic transducer (PMUT) comprising:
forming an anchor structure over a substrate, the anchor structure disposed proximate to regions of sacrificial material;
forming a piezoelectric layer stack over the anchor structure;
removing the sacrificial material so as to form a cavity under the piezoelectric layer stack; and
disposing a mechanical layer proximate to the piezoelectric layer stack, wherein the piezoelectric layer stack and the mechanical layer form part of a multilayer stack, the mechanical layer seals the cavity and, together with the piezoelectric layer stack, is supported by the anchor structure and forms a membrane over the cavity, the membrane being configured to undergo one or both of flexural motion and vibration when the PMUT receives or transmits ultrasonic signals.
17. The method of claim 16, wherein removing the sacrificial material includes removing the sacrificial material through at least one release hole and the mechanical layer seals the at least one release hole.
18. The method of claim 16, wherein the anchor structure is disposed in a lower layer, the lower layer being parallel to the piezoelectric layer stack and including the regions of sacrificial material.
19. The PMUT of claim 16, wherein the mechanical layer has a thickness such that a neutral axis of the multilayer stack is displaced, relative to a neutral axis of the piezoelectric layer stack, towards the mechanical layer to allow an out-of-plane bending mode.
20. The PMUT of claim 19, wherein the mechanical layer is substantially thicker than the piezoelectric layer stack.
21. The PMUT of claim 19, wherein the neutral axis passes through the mechanical layer.
22. An apparatus comprising:
an array of piezoelectric micromechanical ultrasonic transducer (PMUT) sensors; and
an acoustic coupling medium, wherein:
at least one PMUT includes a multilayer stack disposed on a substrate and including an anchor structure disposed over the substrate, a piezoelectric layer stack disposed over the anchor structure and a cavity, and a mechanical layer disposed proximate to the piezoelectric layer stack, the mechanical layer sealing the cavity;
the acoustic coupling medium is disposed above the piezoelectric layer stack; and
the PMUT is configured to receive or transmit ultrasonic signals through the coupling medium.
23. The apparatus of claim 22, wherein the mechanical layer, together with the piezoelectric layer stack, forms a membrane over the cavity, the membrane being configured to undergo one or both of flexural motion and vibration when the PMUT receives or transmits ultrasonic signals.
24. The apparatus of claim 22, wherein the mechanical layer has a thickness such that a neutral axis of the multilayer stack is displaced, relative to a neutral axis of the piezoelectric layer stack, towards the mechanical layer to allow an out-of-plane bending mode.
25. The apparatus of claim 24, wherein the mechanical layer is substantially thicker than the piezoelectric layer stack.
26. The apparatus of claim 24, wherein the neutral axis passes through the mechanical layer.
27. The apparatus of claim 22, wherein:
the cavity is formed by removing a sacrificial material through at least one release hole;
the mechanical layer is formed after removing the sacrificial material; and
the mechanical layer seals the cavity by sealing the at least one release hole.
28. The apparatus of claim 22, wherein the mechanical layer includes a recess where the mechanical layer is locally thinned.
29. The apparatus of claim 22, wherein the mechanical layer is disposed over a side of the piezoelectric stack opposite to the substrate or below a side of the piezoelectric stack facing the substrate.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An image forming apparatus system, including an image forming apparatus comprising:
communication means for communicating through a network;
printing means for forming an image on a recording sheet in accordance with image data so as to output said image;
inputting means for inputting information transfer items corresponding respectively to a plurality of specific events and for inputting an information transfer target address on said network to correspond to one of the specific events;
a table for recording a plurality of settings inputted via said inputting means, each said setting corresponding to one of the specific events and comprising the information transfer target address corresponding individually to said one of the specific events and the information transfer item corresponding said one of the specific events;
control means for controlling an image forming operation of said printing means and for, when one of the specific events occurs, referring to said table and controlling transfer of contents of the information transfer item corresponding to said one of the specific events to said information transfer target address corresponding to said one of the specific events; and
display means for displaying various displays;
wherein said control means indicates said information transfer items and said information transfer target address, both recorded on said table via said display means, and updates said information transfer items and said information transfer target address in accordance with input from said inputting means via said display means;
wherein when one of the specific events occurs, an internal code corresponding to the specific event is transferred simultaneously with said information transfer item corresponding to the specific event; and
further comprising a web server for indicating a state of said image forming apparatus, wherein when one of the specific events occurs, said control means transfers a URL of said web server simultaneously with said information transfer item corresponding to the specific event.
2. The image forming apparatus system of claim 1, wherein said web server and said control means commonly refer to said table with respect to said state of said apparatus.
3. An image forming apparatus system, including an image forming apparatus comprising:
a communication section which communicates through a network;
a printing section which forms an image on a recording sheet in accordance with image data so as to output said image;
an inputting section which inputs information transfer items corresponding respectively to a plurality of specific events and which inputs an information transfer target address on said network to correspond to one of the specific events;
a table which records a plurality of settings inputted via said inputting section, each said setting corresponding to one of the specific events and comprising the information transfer target address corresponding individually to said one of the specific events and the information transfer item corresponding to said one of the specific events;
a controller which controls an image forming operation of said printing section and which, when one of the specific events occurs, refers to said table and controls transferring of contents of said information transfer item corresponding to said one of the specific events to said information transfer target address corresponding to said one of the specific events; and
a display;
wherein said controller indicates said information transfer items and said information transfer target address, both recorded on said table via said display, and updates said information transfer items and said information transfer target address in accordance with input from said inputting section via said display;
wherein when one of the specific events occurs, an internal code corresponding to the specific event is transferred simultaneously with said information transfer item corresponding to the specific event; and
further comprising a web server for indicating a state of said image forming apparatus, wherein when one of the specific events occurs, said controller transfers a URL of said web server simultaneously with said information transfer item corresponding to the specific event.
4. The image forming apparatus system of claim 3, wherein said web server and said controller commonly refer to said table with respect to said state of said apparatus.

1. A memory system comprising:
a semiconductor memory comprising a first memory block and a second memory block each including a plurality of nonvolatile memory cells each configured to hold i-bit data (where i is natural number greater than or equal to 2), data in the first memory block and data in the second memory block being each respectively erased at a time; and
a controller configured to access the semiconductor memory, wherein:
the controller is configured to write first data received from outside of the memory system in the first memory block such that the memory cells written with the first data in the first memory block respectively stores j-bit data (where j is natural number lower than i); and
the controller is configured to copy the first data in the first memory block to the second memory block such that the memory cells written with the first data in the second memory block respectively stores k-bit data (where k is natural number lower than i).
2. The system according to claim 1, wherein the memory cells written with the first data in the first memory block are assigned to i number of first pages,
the memory cells written with the first data in the second memory block are assigned to i number of second pages;
the controller is configured to write the first data in the first memory block using j number of first pages among the i number of first pages, and
the controller is configured to write the first data in the second memory block using k number of second pages among the i number of second pages.
3. The system according to claim 1, wherein the semiconductor memory further comprises a third memory block, and
the controller is configured to write second data received from outside of the memory system in the third memory block such that each of the memory cells in the third memory block stores i-bit data.
4. The system according to claim 3, wherein the memory cells written with the second data in the third memory block are assigned to i number pages, and
the controller is configured to write the second data in the third memory block using all of the i number of first pages.
5. The system according to claim 1, wherein the first data includes boot information, partition management information, and a file allocation table.
6. The system according to claim 4, wherein the third memory block includes a plurality of areas each including a plurality of the memory cells, and
the controller is configured to copy the second data in one of the areas to the first or second memory block in accordance with a frequency of the write access to each of the areas.
7. The system according to claim 6, wherein the controller includes:
a counter which counts the number of write accesses to each of the areas;
a threshold holding unit which has a threshold for a write access frequency;
a comparator which compares a count in the counter with the threshold held in the threshold holding unit; and
an instruction output section which, if the count corresponding to any of the areas exceeds the threshold, instructs the semiconductor memory to copy the data in the area to the first or second memory block.
8. The system according to claim 6, wherein the controller includes a table which holds information indicating the number of bits each held in the memory cells in the first, second, and third memory block.
9. The system according to claim 7, wherein the counter counts the number of the write accesses to the first or second memory block to which the data in the area is copied,
the comparator is configured to compare the number of the write accesses to the first or second memory block to which the data in the area is copied with the threshold; and
if the number of the write accesses is smaller than the threshold, the instruction output section instructs the semiconductor memory to write the data in the first or second memory block back to the third memory block.
10. The system according to claim 4, wherein the controller
writes data received from a host apparatus to the third memory block, and
writes management information of the data received from the host apparatus to the first memory block.
11. A memory system comprising:
a semiconductor memory comprising a first memory block and a second memory block each including a plurality of nonvolatile memory cells each configured to hold i-bit data (where i is natural number greater than or equal to 2), data in the first memory block and data in the second memory block being each respectively erased at a time; and
a controller configured to access the semiconductor memory, wherein:
the controller is configured to write first data received from outside of the memory system in the first memory block such that the memory cells written with the first data in the first memory block respectively stores j-bit data (where j is natural number lower than i);
the controller is configured to write second data received from outside of the memory system in the first memory block such that the memory cells written with the second data in the first memory block respectively stores j-bit data, the second data updating the first data written in the first memory block; and
the controller is configured to copy the second data in the first memory block to the second memory block such that the memory cells written with the second data in the second memory block respectively stores k-bit data (where k is natural number lower than i).
12. The system according to claim 11, wherein the memory cells in the first memory block comprises a first group of memory cells and a second group of memory cells different from the first group of memory cells,
the controller is configured to write the first data in the first group of the memory cells, and
the controller is configured to write the second data in the second group of memory cells.
13. The system according to claim 11, wherein the memory cells written with the first data in the first memory block are assigned to i number of first pages,
the memory cells written with the second data in the first memory block are assigned to i number of second pages;
the controller is configured to write the first and second data in the first memory block using j number of first pages among the i number of first pages, and
the controller is configured to write the second data in the second memory block using k number of second pages among the i number of second pages.
14. The system according to claim 11, wherein the semiconductor memory further comprises a third memory block, and
the controller is configured to write third data received from outside of the memory system in the third memory block such that each of the memory cells in the third memory block stores i-bit data.
15. The system according to claim 14, wherein the memory cells written with the third data in the third memory block are assigned to i number pages, and
the controller is configured to write the third data in the third memory block using all of the i number of first pages.
16. The system according to claim 11, wherein the first data and the second data include boot information, partition management information, and a file allocation table.
17. The system according to claim 15, wherein the third memory block includes a plurality of areas each including a plurality of the memory cells, and
the controller is configured to copy the third data in one of the areas to the first or second memory block in accordance with a frequency of the write access to each of the areas.
18. The system according to claim 17, wherein the controller includes:
a counter configured to count the number of write accesses to each of the areas;
a threshold holding unit which has a threshold for a write access frequency;
a comparator configured to compare a count in the counter with the threshold held in the threshold holding unit; and
an instruction output section configured to instruct the semiconductor memory to copy the data in the area to the first or second memory block if the count corresponding to any of the areas exceeds the threshold.
19. The system according to claim 17, wherein the controller includes a table which holds information indicating the number of bits each held in the memory cells in the first, second, and third memory block.
20. The system according to claim 15, wherein the controller is configured to write data received from a host apparatus to the third memory block, and
to write management information of the data received from the host apparatus to the first or second memory block.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A process for producing an optically active 1-alkyl-substituted 2,2,2-trifluoroethylamine represented by the formula 3,
wherein
R represents a lower alkyl group of a carbon number of 1 to 6, and
* represents an asymmetric carbon, or its salt by subjecting an optically active imine represented by the formula 1,
wherein
R represents a lower alkyl group of a carbon number of 1 to 6,
Ph represents a phenyl group,
a wavy line represents E configuration or Z configuration, and
* represents an asymmetric carbon, to an asymmetric reduction under hydrogen atmosphere using a metal catalyst of Group VIII to convert it into an optically active secondary amine represented by the formula 2,
wherein
R represents a lower alkyl group of a carbon number of 1 to 6,
Ph represents a phenyl group, and
* represents an asymmetric carbon, and then by subjecting the secondary amine or its salt to hydrogenolysis.
2. A production process according to claim 1, wherein the asymmetric reduction is conducted under a temperature condition of not higher than 10\xb0 C.
3. A production process according to claim 1, wherein R of the optically active imine represented by the formula 1, the optically active secondary amine represented by the formula 2 and the optically active 1-alkyl-substituted 2,2,2-trifluoroethylamine represented by the formula 3 is a methyl group.
4. A production process according to claim 1, wherein the optically active imine represented by the formula 1 is an optically active imine obtained by subjecting
a trifluoromethyl alkyl ketone represented by the formula 4
wherein
R represents a lower alkyl group of a carbon number of 1 to 6, and an optically active 1-phenylethylamine represented by the formula 5
wherein
Ph represents a phenyl group, and
* represents an asymmetric carbon, to dehydration and condensation in the presence of an acid catalyst.
5. A purification process characterized in that an optically active secondary amine represented by the formula 2
wherein
R represents a lower alkyl group of a carbon number of 1 to 6,
Ph represents a phenyl group, and
* represents an asymmetric carbon, is converted into its salt, followed by a recrystallization purification.
6. A purification process according to claim 5, wherein R of the optically active secondary amine represented by the formula 2 is a methyl group, and the salt is a, hydrobromide.
7. A purification process according to claim 5, wherein R of the optically active secondary amine represented by the formula 2 is a methyl group, and the salt is an optically active 10-camphorsulfonate.
8. A process for producing an optically active 1-alkyl-substituted 2,2,2-trifluoroethylamine represented by the formula 3 or its salt, according to claim 1, which is characterized in that, after an optically active secondary amine represented by the formula 2 is obtained by a production process according to claim 1, the secondary amine is purified by converting the secondary amine into its salt, followed by a recrystallization purification.
9. An optically active secondary amine represented by the formula 2
wherein
R represents a lower alkyl group of a carbon number of 1 to 6,
Ph represents a phenyl group, and
* represents an asymmetric carbon, or a salt thereof.
10. An optically active secondary amine according to claim 9, wherein R of the optically active secondary amine represented by the formula 2 is a methyl group.
11. A hydrobromide of the optically active secondary amine according to claim 9, wherein R of the optically active secondary amine represented by the formula 2 is a methyl group.
12. An optically active 1-camphorsulfonate of the optically active secondary amine according to claim 9, wherein R of the optically active secondary amine represented by the formula 2 is a methyl group.