All The Claims

1. A heat shielding member, which thermally shields the periphery of a single crystal, which is used in a Czochralski single crystal pulling device that pulls the single crystal from a melt that is collected in a crucible, comprising:
a substantially cylindrical main body portion arranged so as to surround the single crystal, with a lower end portion thereof extending to the vicinity of the melt;
a substantially annular bottom plate portion that extends in the diameter direction from the bottom end portion of the main body portion to cover the melt, and
a support portion that extends to the inner circumference side of the main body portion provided in the bottom end portion of the main body portion,
wherein the bottom plate portion is detachably placed on the support portion and is attached to the main body portion in the state of being severed in the circumferential direction at at least one location.
2. The heat shielding member according to claim 1, wherein the bottom plate portion further comprises a notch portion, and the bottom plate portion is severed along a line that passes through the notch portion.
3. A Czochralski single crystal pulling device that pulls a single crystal from a melt that is collected in a crucible, in which the heat shielding member according to claim 1 or claim 2 is employed as a heat shielding member that surrounds the periphery of the single crystal.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A semiconductor device comprising:
one or more memory blocks each including a block state confirmation cell and one or more memory cells, the block state confirmation cell to store information indicating a number of data bits written to the one or more memory cells; and
a controller reading only the stored data bits from the one or more memory blocks, based on the information stored in the block state confirmation cells.
2. The semiconductor device of claim 1, wherein a number of bits stored in each of the block state confirmation cells is one bit less than a number of data bits stored in the memory cells of each of the corresponding memory blocks.
3. The semiconductor device of claim 1, wherein each of the block state confirmation cells belongs to a first data page of the corresponding memory block.
4. The semiconductor device of claim 1, wherein each of the block state confirmation cells is connected to a first word line from among a plurality of word lines connected to the corresponding memory block.
5. The semiconductor device of claim 1, wherein each of the one or more memory blocks further includes at least one spare cell that replaces a defective memory cell from among the one or more memory cells, and
a total number of spare cells and block state confirmation cells in a row is equal to a total number of the memory cells in the row.
6. The semiconductor device of claim 1, wherein the controller verifies the data bits written to the one or more memory cells, based on the information stored in the corresponding block state confirmation cell.
7. The semiconductor device of claim 1, wherein the one or more memory cells include NAND flash memory cells.
8. A memory reading method of reading data from one or more memory cells, the method comprising:
detecting a number of data bits written to one or more memory cells; and
reading only the detected data bits from the one or more memory cells.
9. The method of claim 8, wherein the detecting of the number of data bits written includes detecting the number of bits indicated by a block state confirmation cell.
10. The method of claim 9, wherein the number of bits indicated in the block state confirmation cell is one bit less than a number of data bits stored in one of the one or more memory cells.
11. The method of claim 10, wherein at least one memory block includes the one or more memory cells and the block state confirmation cell.
12. The method of claim 8, wherein the one or more memory cells include multi-level flash memory cells capable of storing of M data bits.
13. The method of claim 8, wherein the read data bits are used to verify the data written to the one or more memory cells, and
the verification is performed on only the data bits written to the memory cells based on the detected number of data bits.
14. The method of claim 13, wherein the verification includes a controller reading information stored in the block state confirmation cell.
15. A memory programming method comprising:
writing data to a plurality of memory cells;
storing information indicating a number of data bits written to the plurality of memory cells; and
verifying only the written data bits, which are indicated by the stored information.
16. The method of claim 15, wherein the storing information indicating a number of data bits written includes storing a number of bits to a block state confirmation cell.
17. The method of claim 15, wherein the plurality of memory cells include multi-level flash memory cells capable of storing M data bits.
18. The method of claim 16, wherein during the storing of the information, a number of bits of the stored information is one bit less than a number of data bits stored in each of the plurality of memory cells.
19. The method of claim 18, wherein at least one memory block includes the plurality of memory cells and the block state confirmation cell.
20. The method of claim 18, wherein the verifying includes a controller verifying the data bits written to the one or more memory cells, based on the information stored in the corresponding block state confirmation cell.

1. A method for preventing andor treating a degenerative disorder of the central nervous system in a patient at risk for developing or diagnosed with the same, which comprises administering to the patient in need thereof an effective amount of a therapeutic agent which is 5-(fluoromethyl)piperidine-3,4-diol, 5-(chloromethyl)piperidine-3,4-diol, or a pharmaceutically acceptable salt, solvate, or prodrug thereof, or any combination of two or more thereof.
2. The method of claim 1, which comprises administering 5-(fluoromethyl)piperidine-3,4-diol or a pharmaceutically acceptable salt, solvate, or prodrug thereof.
3. The method of claim 1, which comprises administering (3R,4R,5R)-5-(fluoromethyl)piperidine-3,4-diol or a pharmaceutically acceptable salt, solvate, or prodrug thereof.
4. The method of claim 1, which comprises administering (3R,4R,5R)-5-(fluoromethyl)piperidine-3,4-diol hydrochloride.
5. The method of claim 1, which comprises administering 5-(chloromethyl)piperidine-3,4-diol or a pharmaceutically acceptable salt, solvate, or prodrug thereof.
6. The method of claim 1, which comprises administering (3R,4R,5S)-5-(chloromethyl)piperidine-3,4-diol or a pharmaceutically acceptable salt, solvate, or prodrug thereof.
7. The method of claim 1, which comprises administering (3R,4R,5S)-5-(chloromethyl)piperidine-3,4-diol.
8. The method of claim 1, wherein the degenerative disorder is a synucleinopathy.
9. The method of claim 1, wherein the degenerative disorder is characterized by Lewy bodies.
10. The method of claim 1, wherein the degenerative disorder is Parkinson’s disease, dementia with Lewy bodies, multiple system atrophy or Alzheimer’s disease.
12. The method of claim 1, wherein the degenerative disorder is associated with aggregation of at least one protein.
13. The method of claim 1, wherein the degenerative disorder is associated with aggregation of alpha-synuclein.
14. The method of claim 1, wherein the degenerative disorder is associated with aggregation of non-Abeta component.
15. The method of claim 1, wherein the degenerative disorder is associated with accumulation of at least one glycolipid.
16. The method of claim 1, wherein the degenerative disorder is associated with accumulation of at least one glycosphingolipid.
17. The method of claim 1, wherein the degenerative disorder is associated with accumulation of glucocerebroside.
18. The method of claim 1, wherein the degenerative disorder is associated with a mutation in glucocerebrosidase.
19. The method of claim 1, further comprising administering an effective amount of at least one other therapeutic agent.
20. The method of claim 19, wherein at least one other therapeutic agent is levodopa, an anticholinergic, a catechol-O-methyl transferase inhibitor, a dopamine receptor agonist, a monoamine oxidase inhibitor, a peripheral decarboxylase inhibitor, or an anti-inflammatory agent.
21. A method for preventing andor treating Parkinson’s disease in a patient at risk for developing or diagnosed with the same, which comprises administering to the patient in need thereof an effective amount of (3R,4R,5R)-5-(fluoromethyl)piperidine-3,4-diol, (3R,4R,5S)-5-(chloromethyl)piperidine-3,4-diol, or a pharmaceutically acceptable salt, solvate, or prodrug thereof, or any combination of two or more thereof.
22. The method of claim 21, which comprises administering (3R,4R,5R)-5-(fluoromethyl)piperidine-3,4-diol or a pharmaceutically acceptable salt, solvate, or prodrug thereof.
23. The method of claim 21, which comprises administering (3R,4R,5R)-5-(fluoromethyl)piperidine-3,4-diol hydrochloride.
24. The method of claim 21, which comprises administering (3R,4R,5S)-5-(chloromethyl)piperidine-3,4-diol or a pharmaceutically acceptable salt, solvate, or prodrug thereof.
25. The method of claim 21, which comprises administering (3R,4R,5S)-5-(chloromethyl)piperidine-3,4-diol.
26. The method of claim 21, further comprising administering an effective amount of at least one other therapeutic agent.
27. The method of claim 26, wherein at least one other therapeutic agent is levodopa, an anticholinergic, a catechol-O-methyl transferase inhibitor, a dopamine receptor agonist, a monoamine oxidase inhibitor, a peripheral decarboxylase inhibitor, or an anti-inflammatory agent.
28. A kit comprising:
a container having an effective amount of 5-(fluoromethyl)piperidine-3,4-diol, 5-(chloromethyl)piperidine-3,4-diol, or a pharmaceutically acceptable salt, solvate, or prodrug thereof, or any combination of two or more thereof;
instructions for using the same to prevent andor treat a degenerative disorder of the central nervous system.
29. The kit of claim 28, wherein the degenerative disorder of the central nervous system is Parkinson’s disease.
30. The kit of claim 28, wherein the degenerative disorder of the central nervous system is Alzheimer’s disease.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A controller driver, comprising:
a timing control circuit, outputting a plurality of control signals;
a data memory unit, storing image data;
a data selection unit, coupled to the data memory unit, and selecting to output the image data provided by the data memory unit as display data, or generating the display data according to a command or a test pattern provided from an external processor; and
a data line driving circuit, coupled to the timing control circuit and the data selection unit, receiving the display data from the data selection unit, and outputting a grayscale voltage according to the control signals.
2. The controller driver as claimed in claim 1, wherein the data selection unit directly transmits the image data outputted by the data memory unit to the data line driving circuit to serve as the display data when the controller driver is operated in a normal operation mode, and the data selection unit generates the display data to the data line driving circuit according to the command or the test pattern provided by the external processor when the controller driver is operated in a test operation mode.
3. The controller driver as claimed in claim 2, wherein when the controller driver is operated in the test operation mode, the data selection unit provides the test pattern outputted by the external processor to the data line driving circuit to serve as the display data.
4. The controller driver as claimed in claim 2, wherein when the controller driver is operated in the test operation mode, the data selection unit generates a corresponding test pattern to the data line driving circuit to serve as the display data according to the command outputted by the external processor.
5. The controller driver as claimed in claim 2, wherein when the controller driver is operated in the test operation mode, the data selection unit decodes the command and selectively provides the test pattern to a part of or all of channels of the data line driving circuit to serve as the display data according to a decoding result.
6. The controller driver as claimed in claim 1, wherein the data selection unit comprises:
a plurality of logic units, each having an output terminal connected to one of a plurality of output stage circuits of the data line driving circuit,
wherein the logic units select to output the image data provided by the data memory unit to the output stage circuits, or generate the display data to the output stage circuits according to the command or the test pattern provided by the external processor.
7. The controller driver as claimed in claim 1, further comprising:
a system interface circuit, coupled to the data memory unit, the data selection unit and the timing control circuit,
wherein the external processor transmits the command or the test pattern to the data selection unit through the system interface circuit.
8. The controller driver as claimed in claim 1, wherein the data memory unit comprises:
an image data memory, storing the image data; and
a memory control circuit, coupled between the image data memory and the data selection unit.